//------------------------------------------------------------------------------
// <auto-generated>
//     This code was generated by a tool.
//     Date: 02 Dec 2022
//
//     Changes to this file may cause incorrect behavior and will be lost if
//     the code is regenerated.
// </auto-generated>
//------------------------------------------------------------------------------
using System;

namespace Kalk.Core.Modules.HardwareIntrinsics.Arm
{
    public partial class AdvSimdArm64IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("vabd_f64", (Func<object, object, object>)vabd_f64);
            RegisterFunction("vabdq_f64", (Func<object, object, object>)vabdq_f64);
            RegisterFunction("vabds_f32", (Func<object, object, object>)vabds_f32);
            RegisterFunction("vabs_s64", (Func<object, object>)vabs_s64);
            RegisterFunction("vabsq_f64", (Func<object, object>)vabsq_f64);
            RegisterFunction("vabsq_s64", (Func<object, object>)vabsq_s64);
            RegisterFunction("vaddlv_s16", (Func<object, object>)vaddlv_s16);
            RegisterFunction("vaddlv_s8", (Func<object, object>)vaddlv_s8);
            RegisterFunction("vaddlv_u16", (Func<object, object>)vaddlv_u16);
            RegisterFunction("vaddlv_u8", (Func<object, object>)vaddlv_u8);
            RegisterFunction("vaddlvq_s16", (Func<object, object>)vaddlvq_s16);
            RegisterFunction("vaddlvq_s32", (Func<object, object>)vaddlvq_s32);
            RegisterFunction("vaddlvq_s8", (Func<object, object>)vaddlvq_s8);
            RegisterFunction("vaddlvq_u16", (Func<object, object>)vaddlvq_u16);
            RegisterFunction("vaddlvq_u32", (Func<object, object>)vaddlvq_u32);
            RegisterFunction("vaddlvq_u8", (Func<object, object>)vaddlvq_u8);
            RegisterFunction("vaddq_f64", (Func<object, object, object>)vaddq_f64);
            RegisterFunction("vaddv_s16", (Func<object, object>)vaddv_s16);
            RegisterFunction("vaddv_s8", (Func<object, object>)vaddv_s8);
            RegisterFunction("vaddv_u16", (Func<object, object>)vaddv_u16);
            RegisterFunction("vaddv_u8", (Func<object, object>)vaddv_u8);
            RegisterFunction("vaddvq_s16", (Func<object, object>)vaddvq_s16);
            RegisterFunction("vaddvq_s32", (Func<object, object>)vaddvq_s32);
            RegisterFunction("vaddvq_s8", (Func<object, object>)vaddvq_s8);
            RegisterFunction("vaddvq_u16", (Func<object, object>)vaddvq_u16);
            RegisterFunction("vaddvq_u32", (Func<object, object>)vaddvq_u32);
            RegisterFunction("vaddvq_u8", (Func<object, object>)vaddvq_u8);
            RegisterFunction("vcage_f64", (Func<object, object, object>)vcage_f64);
            RegisterFunction("vcageq_f64", (Func<object, object, object>)vcageq_f64);
            RegisterFunction("vcages_f32", (Func<object, object, object>)vcages_f32);
            RegisterFunction("vcagt_f64", (Func<object, object, object>)vcagt_f64);
            RegisterFunction("vcagtq_f64", (Func<object, object, object>)vcagtq_f64);
            RegisterFunction("vcagts_f32", (Func<object, object, object>)vcagts_f32);
            RegisterFunction("vcale_f64", (Func<object, object, object>)vcale_f64);
            RegisterFunction("vcaleq_f64", (Func<object, object, object>)vcaleq_f64);
            RegisterFunction("vcales_f32", (Func<object, object, object>)vcales_f32);
            RegisterFunction("vcalt_f64", (Func<object, object, object>)vcalt_f64);
            RegisterFunction("vcaltq_f64", (Func<object, object, object>)vcaltq_f64);
            RegisterFunction("vcalts_f32", (Func<object, object, object>)vcalts_f32);
            RegisterFunction("vceq_f64", (Func<object, object, object>)vceq_f64);
            RegisterFunction("vceq_s64", (Func<object, object, object>)vceq_s64);
            RegisterFunction("vceq_u64", (Func<object, object, object>)vceq_u64);
            RegisterFunction("vceqq_f64", (Func<object, object, object>)vceqq_f64);
            RegisterFunction("vceqq_s64", (Func<object, object, object>)vceqq_s64);
            RegisterFunction("vceqq_u64", (Func<object, object, object>)vceqq_u64);
            RegisterFunction("vceqs_f32", (Func<object, object, object>)vceqs_f32);
            RegisterFunction("vcge_f64", (Func<object, object, object>)vcge_f64);
            RegisterFunction("vcge_s64", (Func<object, object, object>)vcge_s64);
            RegisterFunction("vcge_u64", (Func<object, object, object>)vcge_u64);
            RegisterFunction("vcgeq_f64", (Func<object, object, object>)vcgeq_f64);
            RegisterFunction("vcgeq_s64", (Func<object, object, object>)vcgeq_s64);
            RegisterFunction("vcgeq_u64", (Func<object, object, object>)vcgeq_u64);
            RegisterFunction("vcges_f32", (Func<object, object, object>)vcges_f32);
            RegisterFunction("vcgt_f64", (Func<object, object, object>)vcgt_f64);
            RegisterFunction("vcgt_s64", (Func<object, object, object>)vcgt_s64);
            RegisterFunction("vcgt_u64", (Func<object, object, object>)vcgt_u64);
            RegisterFunction("vcgtq_f64", (Func<object, object, object>)vcgtq_f64);
            RegisterFunction("vcgtq_s64", (Func<object, object, object>)vcgtq_s64);
            RegisterFunction("vcgtq_u64", (Func<object, object, object>)vcgtq_u64);
            RegisterFunction("vcgts_f32", (Func<object, object, object>)vcgts_f32);
            RegisterFunction("vcle_f64", (Func<object, object, object>)vcle_f64);
            RegisterFunction("vcle_s64", (Func<object, object, object>)vcle_s64);
            RegisterFunction("vcle_u64", (Func<object, object, object>)vcle_u64);
            RegisterFunction("vcleq_f64", (Func<object, object, object>)vcleq_f64);
            RegisterFunction("vcleq_s64", (Func<object, object, object>)vcleq_s64);
            RegisterFunction("vcleq_u64", (Func<object, object, object>)vcleq_u64);
            RegisterFunction("vcles_f32", (Func<object, object, object>)vcles_f32);
            RegisterFunction("vclt_f64", (Func<object, object, object>)vclt_f64);
            RegisterFunction("vclt_s64", (Func<object, object, object>)vclt_s64);
            RegisterFunction("vclt_u64", (Func<object, object, object>)vclt_u64);
            RegisterFunction("vcltq_f64", (Func<object, object, object>)vcltq_f64);
            RegisterFunction("vcltq_s64", (Func<object, object, object>)vcltq_s64);
            RegisterFunction("vcltq_u64", (Func<object, object, object>)vcltq_u64);
            RegisterFunction("vclts_f32", (Func<object, object, object>)vclts_f32);
            RegisterFunction("vcopy_lane_f32", (Func<object, byte, object, byte, object>)vcopy_lane_f32);
            RegisterFunction("vcopy_lane_s16", (Func<object, byte, object, byte, object>)vcopy_lane_s16);
            RegisterFunction("vcopy_lane_s32", (Func<object, byte, object, byte, object>)vcopy_lane_s32);
            RegisterFunction("vcopy_lane_s8", (Func<object, byte, object, byte, object>)vcopy_lane_s8);
            RegisterFunction("vcopy_lane_u16", (Func<object, byte, object, byte, object>)vcopy_lane_u16);
            RegisterFunction("vcopy_lane_u32", (Func<object, byte, object, byte, object>)vcopy_lane_u32);
            RegisterFunction("vcopy_lane_u8", (Func<object, byte, object, byte, object>)vcopy_lane_u8);
            RegisterFunction("vcopy_laneq_f32", (Func<object, byte, object, byte, object>)vcopy_laneq_f32);
            RegisterFunction("vcopy_laneq_s16", (Func<object, byte, object, byte, object>)vcopy_laneq_s16);
            RegisterFunction("vcopy_laneq_s32", (Func<object, byte, object, byte, object>)vcopy_laneq_s32);
            RegisterFunction("vcopy_laneq_s8", (Func<object, byte, object, byte, object>)vcopy_laneq_s8);
            RegisterFunction("vcopy_laneq_u16", (Func<object, byte, object, byte, object>)vcopy_laneq_u16);
            RegisterFunction("vcopy_laneq_u32", (Func<object, byte, object, byte, object>)vcopy_laneq_u32);
            RegisterFunction("vcopy_laneq_u8", (Func<object, byte, object, byte, object>)vcopy_laneq_u8);
            RegisterFunction("vcopyq_lane_f32", (Func<object, byte, object, byte, object>)vcopyq_lane_f32);
            RegisterFunction("vcopyq_lane_s16", (Func<object, byte, object, byte, object>)vcopyq_lane_s16);
            RegisterFunction("vcopyq_lane_s32", (Func<object, byte, object, byte, object>)vcopyq_lane_s32);
            RegisterFunction("vcopyq_lane_s8", (Func<object, byte, object, byte, object>)vcopyq_lane_s8);
            RegisterFunction("vcopyq_lane_u16", (Func<object, byte, object, byte, object>)vcopyq_lane_u16);
            RegisterFunction("vcopyq_lane_u32", (Func<object, byte, object, byte, object>)vcopyq_lane_u32);
            RegisterFunction("vcopyq_lane_u8", (Func<object, byte, object, byte, object>)vcopyq_lane_u8);
            RegisterFunction("vcopyq_laneq_f32", (Func<object, byte, object, byte, object>)vcopyq_laneq_f32);
            RegisterFunction("vcopyq_laneq_f64", (Func<object, byte, object, byte, object>)vcopyq_laneq_f64);
            RegisterFunction("vcopyq_laneq_s16", (Func<object, byte, object, byte, object>)vcopyq_laneq_s16);
            RegisterFunction("vcopyq_laneq_s32", (Func<object, byte, object, byte, object>)vcopyq_laneq_s32);
            RegisterFunction("vcopyq_laneq_s64", (Func<object, byte, object, byte, object>)vcopyq_laneq_s64);
            RegisterFunction("vcopyq_laneq_s8", (Func<object, byte, object, byte, object>)vcopyq_laneq_s8);
            RegisterFunction("vcopyq_laneq_u16", (Func<object, byte, object, byte, object>)vcopyq_laneq_u16);
            RegisterFunction("vcopyq_laneq_u32", (Func<object, byte, object, byte, object>)vcopyq_laneq_u32);
            RegisterFunction("vcopyq_laneq_u64", (Func<object, byte, object, byte, object>)vcopyq_laneq_u64);
            RegisterFunction("vcopyq_laneq_u8", (Func<object, byte, object, byte, object>)vcopyq_laneq_u8);
            RegisterFunction("vcvt_f32_f64", (Func<object, object>)vcvt_f32_f64);
            RegisterFunction("vcvt_f64_f32", (Func<object, object>)vcvt_f64_f32);
            RegisterFunction("vcvt_f64_s64", (Func<object, object>)vcvt_f64_s64);
            RegisterFunction("vcvt_f64_u64", (Func<object, object>)vcvt_f64_u64);
            RegisterFunction("vcvt_high_f32_f64", (Func<object, object, object>)vcvt_high_f32_f64);
            RegisterFunction("vcvt_high_f64_f32", (Func<object, object>)vcvt_high_f64_f32);
            RegisterFunction("vcvt_s64_f64", (Func<object, object>)vcvt_s64_f64);
            RegisterFunction("vcvt_u64_f64", (Func<object, object>)vcvt_u64_f64);
            RegisterFunction("vcvta_s64_f64", (Func<object, object>)vcvta_s64_f64);
            RegisterFunction("vcvta_u64_f64", (Func<object, object>)vcvta_u64_f64);
            RegisterFunction("vcvtaq_s64_f64", (Func<object, object>)vcvtaq_s64_f64);
            RegisterFunction("vcvtaq_u64_f64", (Func<object, object>)vcvtaq_u64_f64);
            RegisterFunction("vcvtm_s64_f64", (Func<object, object>)vcvtm_s64_f64);
            RegisterFunction("vcvtm_u64_f64", (Func<object, object>)vcvtm_u64_f64);
            RegisterFunction("vcvtmq_s64_f64", (Func<object, object>)vcvtmq_s64_f64);
            RegisterFunction("vcvtmq_u64_f64", (Func<object, object>)vcvtmq_u64_f64);
            RegisterFunction("vcvtn_s64_f64", (Func<object, object>)vcvtn_s64_f64);
            RegisterFunction("vcvtn_u64_f64", (Func<object, object>)vcvtn_u64_f64);
            RegisterFunction("vcvtnq_s64_f64", (Func<object, object>)vcvtnq_s64_f64);
            RegisterFunction("vcvtnq_u64_f64", (Func<object, object>)vcvtnq_u64_f64);
            RegisterFunction("vcvtp_s64_f64", (Func<object, object>)vcvtp_s64_f64);
            RegisterFunction("vcvtp_u64_f64", (Func<object, object>)vcvtp_u64_f64);
            RegisterFunction("vcvtpq_s64_f64", (Func<object, object>)vcvtpq_s64_f64);
            RegisterFunction("vcvtpq_u64_f64", (Func<object, object>)vcvtpq_u64_f64);
            RegisterFunction("vcvtq_f64_s64", (Func<object, object>)vcvtq_f64_s64);
            RegisterFunction("vcvtq_f64_u64", (Func<object, object>)vcvtq_f64_u64);
            RegisterFunction("vcvtq_s64_f64", (Func<object, object>)vcvtq_s64_f64);
            RegisterFunction("vcvtq_u64_f64", (Func<object, object>)vcvtq_u64_f64);
            RegisterFunction("vcvtx_f32_f64", (Func<object, object>)vcvtx_f32_f64);
            RegisterFunction("vcvtx_high_f32_f64", (Func<object, object, object>)vcvtx_high_f32_f64);
            RegisterFunction("vdiv_f32", (Func<object, object, object>)vdiv_f32);
            RegisterFunction("vdivq_f32", (Func<object, object, object>)vdivq_f32);
            RegisterFunction("vdivq_f64", (Func<object, object, object>)vdivq_f64);
            RegisterFunction("vdupq_laneq_f64", (Func<object, byte, object>)vdupq_laneq_f64);
            RegisterFunction("vdupq_laneq_s64", (Func<object, byte, object>)vdupq_laneq_s64);
            RegisterFunction("vdupq_laneq_u64", (Func<object, byte, object>)vdupq_laneq_u64);
            RegisterFunction("vdupq_n_f64", (Func<double, object>)vdupq_n_f64);
            RegisterFunction("vdupq_n_s64", (Func<long, object>)vdupq_n_s64);
            RegisterFunction("vfma_lane_f32", (Func<object, object, object, byte, object>)vfma_lane_f32);
            RegisterFunction("vfma_laneq_f32", (Func<object, object, object, byte, object>)vfma_laneq_f32);
            RegisterFunction("vfma_n_f32", (Func<object, object, object, object>)vfma_n_f32);
            RegisterFunction("vfmad_laneq_f64", (Func<object, object, object, byte, object>)vfmad_laneq_f64);
            RegisterFunction("vfmaq_f64", (Func<object, object, object, object>)vfmaq_f64);
            RegisterFunction("vfmaq_lane_f32", (Func<object, object, object, byte, object>)vfmaq_lane_f32);
            RegisterFunction("vfmaq_laneq_f32", (Func<object, object, object, byte, object>)vfmaq_laneq_f32);
            RegisterFunction("vfmaq_laneq_f64", (Func<object, object, object, byte, object>)vfmaq_laneq_f64);
            RegisterFunction("vfmaq_n_f32", (Func<object, object, object, object>)vfmaq_n_f32);
            RegisterFunction("vfmaq_n_f64", (Func<object, object, object, object>)vfmaq_n_f64);
            RegisterFunction("vfmas_lane_f32", (Func<object, object, object, byte, object>)vfmas_lane_f32);
            RegisterFunction("vfmas_laneq_f32", (Func<object, object, object, byte, object>)vfmas_laneq_f32);
            RegisterFunction("vfms_lane_f32", (Func<object, object, object, byte, object>)vfms_lane_f32);
            RegisterFunction("vfms_laneq_f32", (Func<object, object, object, byte, object>)vfms_laneq_f32);
            RegisterFunction("vfms_n_f32", (Func<object, object, object, object>)vfms_n_f32);
            RegisterFunction("vfmsd_laneq_f64", (Func<object, object, object, byte, object>)vfmsd_laneq_f64);
            RegisterFunction("vfmsq_f64", (Func<object, object, object, object>)vfmsq_f64);
            RegisterFunction("vfmsq_lane_f32", (Func<object, object, object, byte, object>)vfmsq_lane_f32);
            RegisterFunction("vfmsq_laneq_f32", (Func<object, object, object, byte, object>)vfmsq_laneq_f32);
            RegisterFunction("vfmsq_laneq_f64", (Func<object, object, object, byte, object>)vfmsq_laneq_f64);
            RegisterFunction("vfmsq_n_f32", (Func<object, object, object, object>)vfmsq_n_f32);
            RegisterFunction("vfmsq_n_f64", (Func<object, object, object, object>)vfmsq_n_f64);
            RegisterFunction("vfmss_lane_f32", (Func<object, object, object, byte, object>)vfmss_lane_f32);
            RegisterFunction("vfmss_laneq_f32", (Func<object, object, object, byte, object>)vfmss_laneq_f32);
            RegisterFunction("vld1q_dup_f64", (Func<object, object>)vld1q_dup_f64);
            RegisterFunction("vld1q_dup_s64", (Func<object, object>)vld1q_dup_s64);
            RegisterFunction("vld1q_dup_u64", (Func<object, object>)vld1q_dup_u64);
            RegisterFunction("vmax_f64", (Func<object, object, object>)vmax_f64);
            RegisterFunction("vmaxnmq_f64", (Func<object, object, object>)vmaxnmq_f64);
            RegisterFunction("vmaxnmvq_f32", (Func<object, object>)vmaxnmvq_f32);
            RegisterFunction("vmaxq_f64", (Func<object, object, object>)vmaxq_f64);
            RegisterFunction("vmaxs_f32", (Func<object, object, object>)vmaxs_f32);
            RegisterFunction("vmaxv_s16", (Func<object, object>)vmaxv_s16);
            RegisterFunction("vmaxv_s8", (Func<object, object>)vmaxv_s8);
            RegisterFunction("vmaxv_u16", (Func<object, object>)vmaxv_u16);
            RegisterFunction("vmaxv_u8", (Func<object, object>)vmaxv_u8);
            RegisterFunction("vmaxvq_f32", (Func<object, object>)vmaxvq_f32);
            RegisterFunction("vmaxvq_s16", (Func<object, object>)vmaxvq_s16);
            RegisterFunction("vmaxvq_s32", (Func<object, object>)vmaxvq_s32);
            RegisterFunction("vmaxvq_s8", (Func<object, object>)vmaxvq_s8);
            RegisterFunction("vmaxvq_u16", (Func<object, object>)vmaxvq_u16);
            RegisterFunction("vmaxvq_u32", (Func<object, object>)vmaxvq_u32);
            RegisterFunction("vmaxvq_u8", (Func<object, object>)vmaxvq_u8);
            RegisterFunction("vmin_f64", (Func<object, object, object>)vmin_f64);
            RegisterFunction("vminnmq_f64", (Func<object, object, object>)vminnmq_f64);
            RegisterFunction("vminnmvq_f32", (Func<object, object>)vminnmvq_f32);
            RegisterFunction("vminq_f64", (Func<object, object, object>)vminq_f64);
            RegisterFunction("vmins_f32", (Func<object, object, object>)vmins_f32);
            RegisterFunction("vminv_s16", (Func<object, object>)vminv_s16);
            RegisterFunction("vminv_s8", (Func<object, object>)vminv_s8);
            RegisterFunction("vminv_u16", (Func<object, object>)vminv_u16);
            RegisterFunction("vminv_u8", (Func<object, object>)vminv_u8);
            RegisterFunction("vminvq_f32", (Func<object, object>)vminvq_f32);
            RegisterFunction("vminvq_s16", (Func<object, object>)vminvq_s16);
            RegisterFunction("vminvq_s8", (Func<object, object>)vminvq_s8);
            RegisterFunction("vminvq_u16", (Func<object, object>)vminvq_u16);
            RegisterFunction("vminvq_u32", (Func<object, object>)vminvq_u32);
            RegisterFunction("vminvq_u8", (Func<object, object>)vminvq_u8);
            RegisterFunction("vmuld_laneq_f64", (Func<object, object, byte, object>)vmuld_laneq_f64);
            RegisterFunction("vmulq_f64", (Func<object, object, object>)vmulq_f64);
            RegisterFunction("vmulq_laneq_f64", (Func<object, object, byte, object>)vmulq_laneq_f64);
            RegisterFunction("vmulq_n_f64", (Func<object, object, object>)vmulq_n_f64);
            RegisterFunction("vmulx_f32", (Func<object, object, object>)vmulx_f32);
            RegisterFunction("vmulx_f64", (Func<object, object, object>)vmulx_f64);
            RegisterFunction("vmulx_lane_f32", (Func<object, object, byte, object>)vmulx_lane_f32);
            RegisterFunction("vmulx_laneq_f32", (Func<object, object, byte, object>)vmulx_laneq_f32);
            RegisterFunction("vmulxd_laneq_f64", (Func<object, object, byte, object>)vmulxd_laneq_f64);
            RegisterFunction("vmulxq_f32", (Func<object, object, object>)vmulxq_f32);
            RegisterFunction("vmulxq_f64", (Func<object, object, object>)vmulxq_f64);
            RegisterFunction("vmulxq_lane_f32", (Func<object, object, byte, object>)vmulxq_lane_f32);
            RegisterFunction("vmulxq_lane_f64", (Func<object, object, object>)vmulxq_lane_f64);
            RegisterFunction("vmulxq_laneq_f32", (Func<object, object, byte, object>)vmulxq_laneq_f32);
            RegisterFunction("vmulxq_laneq_f64", (Func<object, object, byte, object>)vmulxq_laneq_f64);
            RegisterFunction("vmulxs_f32", (Func<object, object, object>)vmulxs_f32);
            RegisterFunction("vmulxs_lane_f32", (Func<object, object, byte, object>)vmulxs_lane_f32);
            RegisterFunction("vmulxs_laneq_f32", (Func<object, object, byte, object>)vmulxs_laneq_f32);
            RegisterFunction("vneg_s64", (Func<object, object>)vneg_s64);
            RegisterFunction("vnegq_f64", (Func<object, object>)vnegq_f64);
            RegisterFunction("vnegq_s64", (Func<object, object>)vnegq_s64);
            RegisterFunction("vpaddd_f64", (Func<object, object>)vpaddd_f64);
            RegisterFunction("vpaddd_s64", (Func<object, object>)vpaddd_s64);
            RegisterFunction("vpaddd_u64", (Func<object, object>)vpaddd_u64);
            RegisterFunction("vpaddq_f32", (Func<object, object, object>)vpaddq_f32);
            RegisterFunction("vpaddq_f64", (Func<object, object, object>)vpaddq_f64);
            RegisterFunction("vpaddq_s16", (Func<object, object, object>)vpaddq_s16);
            RegisterFunction("vpaddq_s32", (Func<object, object, object>)vpaddq_s32);
            RegisterFunction("vpaddq_s64", (Func<object, object, object>)vpaddq_s64);
            RegisterFunction("vpaddq_s8", (Func<object, object, object>)vpaddq_s8);
            RegisterFunction("vpaddq_u16", (Func<object, object, object>)vpaddq_u16);
            RegisterFunction("vpaddq_u32", (Func<object, object, object>)vpaddq_u32);
            RegisterFunction("vpaddq_u64", (Func<object, object, object>)vpaddq_u64);
            RegisterFunction("vpaddq_u8", (Func<object, object, object>)vpaddq_u8);
            RegisterFunction("vpadds_f32", (Func<object, object>)vpadds_f32);
            RegisterFunction("vpmaxnm_f32", (Func<object, object, object>)vpmaxnm_f32);
            RegisterFunction("vpmaxnmq_f32", (Func<object, object, object>)vpmaxnmq_f32);
            RegisterFunction("vpmaxnmq_f64", (Func<object, object, object>)vpmaxnmq_f64);
            RegisterFunction("vpmaxnmqd_f64", (Func<object, object>)vpmaxnmqd_f64);
            RegisterFunction("vpmaxnms_f32", (Func<object, object>)vpmaxnms_f32);
            RegisterFunction("vpmaxq_f32", (Func<object, object, object>)vpmaxq_f32);
            RegisterFunction("vpmaxq_f64", (Func<object, object, object>)vpmaxq_f64);
            RegisterFunction("vpmaxq_s16", (Func<object, object, object>)vpmaxq_s16);
            RegisterFunction("vpmaxq_s32", (Func<object, object, object>)vpmaxq_s32);
            RegisterFunction("vpmaxq_s8", (Func<object, object, object>)vpmaxq_s8);
            RegisterFunction("vpmaxq_u16", (Func<object, object, object>)vpmaxq_u16);
            RegisterFunction("vpmaxq_u32", (Func<object, object, object>)vpmaxq_u32);
            RegisterFunction("vpmaxq_u8", (Func<object, object, object>)vpmaxq_u8);
            RegisterFunction("vpmaxqd_f64", (Func<object, object>)vpmaxqd_f64);
            RegisterFunction("vpmaxs_f32", (Func<object, object>)vpmaxs_f32);
            RegisterFunction("vpminnm_f32", (Func<object, object, object>)vpminnm_f32);
            RegisterFunction("vpminnmq_f32", (Func<object, object, object>)vpminnmq_f32);
            RegisterFunction("vpminnmq_f64", (Func<object, object, object>)vpminnmq_f64);
            RegisterFunction("vpminnmqd_f64", (Func<object, object>)vpminnmqd_f64);
            RegisterFunction("vpminnms_f32", (Func<object, object>)vpminnms_f32);
            RegisterFunction("vpminq_f32", (Func<object, object, object>)vpminq_f32);
            RegisterFunction("vpminq_f64", (Func<object, object, object>)vpminq_f64);
            RegisterFunction("vpminq_s16", (Func<object, object, object>)vpminq_s16);
            RegisterFunction("vpminq_s32", (Func<object, object, object>)vpminq_s32);
            RegisterFunction("vpminq_s8", (Func<object, object, object>)vpminq_s8);
            RegisterFunction("vpminq_u16", (Func<object, object, object>)vpminq_u16);
            RegisterFunction("vpminq_u32", (Func<object, object, object>)vpminq_u32);
            RegisterFunction("vpminq_u8", (Func<object, object, object>)vpminq_u8);
            RegisterFunction("vpminqd_f64", (Func<object, object>)vpminqd_f64);
            RegisterFunction("vpmins_f32", (Func<object, object>)vpmins_f32);
            RegisterFunction("vqabsb_s8", (Func<object, object>)vqabsb_s8);
            RegisterFunction("vqabsd_s64", (Func<object, object>)vqabsd_s64);
            RegisterFunction("vqabsh_s16", (Func<object, object>)vqabsh_s16);
            RegisterFunction("vqabsq_s64", (Func<object, object>)vqabsq_s64);
            RegisterFunction("vqabss_s32", (Func<object, object>)vqabss_s32);
            RegisterFunction("vqaddb_s8", (Func<object, object, object>)vqaddb_s8);
            RegisterFunction("vqaddb_u8", (Func<object, object, object>)vqaddb_u8);
            RegisterFunction("vqaddh_s16", (Func<object, object, object>)vqaddh_s16);
            RegisterFunction("vqaddh_u16", (Func<object, object, object>)vqaddh_u16);
            RegisterFunction("vqadds_s32", (Func<object, object, object>)vqadds_s32);
            RegisterFunction("vqadds_u32", (Func<object, object, object>)vqadds_u32);
            RegisterFunction("vqnegb_s8", (Func<object, object>)vqnegb_s8);
            RegisterFunction("vqnegd_s64", (Func<object, object>)vqnegd_s64);
            RegisterFunction("vqnegh_s16", (Func<object, object>)vqnegh_s16);
            RegisterFunction("vqnegq_s64", (Func<object, object>)vqnegq_s64);
            RegisterFunction("vqnegs_s32", (Func<object, object>)vqnegs_s32);
            RegisterFunction("vqrshlb_s8", (Func<object, object, object>)vqrshlb_s8);
            RegisterFunction("vqrshlb_u8", (Func<object, object, object>)vqrshlb_u8);
            RegisterFunction("vqrshlh_s16", (Func<object, object, object>)vqrshlh_s16);
            RegisterFunction("vqrshlh_u16", (Func<object, object, object>)vqrshlh_u16);
            RegisterFunction("vqrshls_s32", (Func<object, object, object>)vqrshls_s32);
            RegisterFunction("vqrshls_u32", (Func<object, object, object>)vqrshls_u32);
            RegisterFunction("vqrshrnd_n_s64", (Func<object, byte, object>)vqrshrnd_n_s64);
            RegisterFunction("vqrshrnd_n_u64", (Func<object, byte, object>)vqrshrnd_n_u64);
            RegisterFunction("vqrshrnh_n_s16", (Func<object, byte, object>)vqrshrnh_n_s16);
            RegisterFunction("vqrshrnh_n_u16", (Func<object, byte, object>)vqrshrnh_n_u16);
            RegisterFunction("vqrshrns_n_s32", (Func<object, byte, object>)vqrshrns_n_s32);
            RegisterFunction("vqrshrns_n_u32", (Func<object, byte, object>)vqrshrns_n_u32);
            RegisterFunction("vqrshrund_n_s64", (Func<object, byte, object>)vqrshrund_n_s64);
            RegisterFunction("vqrshrunh_n_s16", (Func<object, byte, object>)vqrshrunh_n_s16);
            RegisterFunction("vqrshruns_n_s32", (Func<object, byte, object>)vqrshruns_n_s32);
            RegisterFunction("vqshlb_n_s8", (Func<object, byte, object>)vqshlb_n_s8);
            RegisterFunction("vqshlb_n_u8", (Func<object, byte, object>)vqshlb_n_u8);
            RegisterFunction("vqshlb_s8", (Func<object, object, object>)vqshlb_s8);
            RegisterFunction("vqshlb_u8", (Func<object, object, object>)vqshlb_u8);
            RegisterFunction("vqshlh_n_s16", (Func<object, byte, object>)vqshlh_n_s16);
            RegisterFunction("vqshlh_n_u16", (Func<object, byte, object>)vqshlh_n_u16);
            RegisterFunction("vqshlh_s16", (Func<object, object, object>)vqshlh_s16);
            RegisterFunction("vqshlh_u16", (Func<object, object, object>)vqshlh_u16);
            RegisterFunction("vqshls_n_s32", (Func<object, byte, object>)vqshls_n_s32);
            RegisterFunction("vqshls_n_u32", (Func<object, byte, object>)vqshls_n_u32);
            RegisterFunction("vqshls_s32", (Func<object, object, object>)vqshls_s32);
            RegisterFunction("vqshls_u32", (Func<object, object, object>)vqshls_u32);
            RegisterFunction("vqshlub_n_s8", (Func<object, byte, object>)vqshlub_n_s8);
            RegisterFunction("vqshluh_n_s16", (Func<object, byte, object>)vqshluh_n_s16);
            RegisterFunction("vqshlus_n_s32", (Func<object, byte, object>)vqshlus_n_s32);
            RegisterFunction("vqshrnd_n_s64", (Func<object, byte, object>)vqshrnd_n_s64);
            RegisterFunction("vqshrnd_n_u64", (Func<object, byte, object>)vqshrnd_n_u64);
            RegisterFunction("vqshrnh_n_s16", (Func<object, byte, object>)vqshrnh_n_s16);
            RegisterFunction("vqshrnh_n_u16", (Func<object, byte, object>)vqshrnh_n_u16);
            RegisterFunction("vqshrns_n_s32", (Func<object, byte, object>)vqshrns_n_s32);
            RegisterFunction("vqshrns_n_u32", (Func<object, byte, object>)vqshrns_n_u32);
            RegisterFunction("vqshrund_n_s64", (Func<object, byte, object>)vqshrund_n_s64);
            RegisterFunction("vqshrunh_n_s16", (Func<object, byte, object>)vqshrunh_n_s16);
            RegisterFunction("vqshruns_n_s32", (Func<object, byte, object>)vqshruns_n_s32);
            RegisterFunction("vqsubb_s8", (Func<object, object, object>)vqsubb_s8);
            RegisterFunction("vqsubb_u8", (Func<object, object, object>)vqsubb_u8);
            RegisterFunction("vqsubh_s16", (Func<object, object, object>)vqsubh_s16);
            RegisterFunction("vqsubh_u16", (Func<object, object, object>)vqsubh_u16);
            RegisterFunction("vqsubs_s32", (Func<object, object, object>)vqsubs_s32);
            RegisterFunction("vqsubs_u32", (Func<object, object, object>)vqsubs_u32);
            RegisterFunction("vqvtbl1q_s8", (Func<object, object, object>)vqvtbl1q_s8);
            RegisterFunction("vqvtbl1q_u8", (Func<object, object, object>)vqvtbl1q_u8);
            RegisterFunction("vqvtbx1q_s8", (Func<object, object, object, object>)vqvtbx1q_s8);
            RegisterFunction("vqvtbx1q_u8", (Func<object, object, object, object>)vqvtbx1q_u8);
            RegisterFunction("vrbit_s8", (Func<object, object>)vrbit_s8);
            RegisterFunction("vrbit_u8", (Func<object, object>)vrbit_u8);
            RegisterFunction("vrbitq_s8", (Func<object, object>)vrbitq_s8);
            RegisterFunction("vrbitq_u8", (Func<object, object>)vrbitq_u8);
            RegisterFunction("vrecpe_f64", (Func<object, object>)vrecpe_f64);
            RegisterFunction("vrecpeq_f64", (Func<object, object>)vrecpeq_f64);
            RegisterFunction("vrecpes_f32", (Func<object, object>)vrecpes_f32);
            RegisterFunction("vrecps_f64", (Func<object, object, object>)vrecps_f64);
            RegisterFunction("vrecpsq_f64", (Func<object, object, object>)vrecpsq_f64);
            RegisterFunction("vrecpss_f32", (Func<object, object, object>)vrecpss_f32);
            RegisterFunction("vrecpxd_f64", (Func<object, object>)vrecpxd_f64);
            RegisterFunction("vrecpxs_f32", (Func<object, object>)vrecpxs_f32);
            RegisterFunction("vrndaq_f64", (Func<object, object>)vrndaq_f64);
            RegisterFunction("vrndmq_f64", (Func<object, object>)vrndmq_f64);
            RegisterFunction("vrndnq_f64", (Func<object, object>)vrndnq_f64);
            RegisterFunction("vrndpq_f64", (Func<object, object>)vrndpq_f64);
            RegisterFunction("vrndq_f64", (Func<object, object>)vrndq_f64);
            RegisterFunction("vrsqrte_f64", (Func<object, object>)vrsqrte_f64);
            RegisterFunction("vrsqrteq_f64", (Func<object, object>)vrsqrteq_f64);
            RegisterFunction("vrsqrtes_f32", (Func<object, object>)vrsqrtes_f32);
            RegisterFunction("vrsqrts_f64", (Func<object, object, object>)vrsqrts_f64);
            RegisterFunction("vrsqrtsq_f64", (Func<object, object, object>)vrsqrtsq_f64);
            RegisterFunction("vrsqrtss_f32", (Func<object, object, object>)vrsqrtss_f32);
            RegisterFunction("vsqadd_u16", (Func<object, object, object>)vsqadd_u16);
            RegisterFunction("vsqadd_u32", (Func<object, object, object>)vsqadd_u32);
            RegisterFunction("vsqadd_u64", (Func<object, object, object>)vsqadd_u64);
            RegisterFunction("vsqadd_u8", (Func<object, object, object>)vsqadd_u8);
            RegisterFunction("vsqaddb_u8", (Func<object, object, object>)vsqaddb_u8);
            RegisterFunction("vsqaddh_u16", (Func<object, object, object>)vsqaddh_u16);
            RegisterFunction("vsqaddq_u16", (Func<object, object, object>)vsqaddq_u16);
            RegisterFunction("vsqaddq_u32", (Func<object, object, object>)vsqaddq_u32);
            RegisterFunction("vsqaddq_u64", (Func<object, object, object>)vsqaddq_u64);
            RegisterFunction("vsqaddq_u8", (Func<object, object, object>)vsqaddq_u8);
            RegisterFunction("vsqadds_u32", (Func<object, object, object>)vsqadds_u32);
            RegisterFunction("vsqrt_f32", (Func<object, object>)vsqrt_f32);
            RegisterFunction("vsqrtq_f32", (Func<object, object>)vsqrtq_f32);
            RegisterFunction("vsqrtq_f64", (Func<object, object>)vsqrtq_f64);
            RegisterFunction("vsubq_f64", (Func<object, object, object>)vsubq_f64);
            RegisterFunction("vtrn1_f32", (Func<object, object, object>)vtrn1_f32);
            RegisterFunction("vtrn1_s16", (Func<object, object, object>)vtrn1_s16);
            RegisterFunction("vtrn1_s32", (Func<object, object, object>)vtrn1_s32);
            RegisterFunction("vtrn1_s8", (Func<object, object, object>)vtrn1_s8);
            RegisterFunction("vtrn1_u16", (Func<object, object, object>)vtrn1_u16);
            RegisterFunction("vtrn1_u32", (Func<object, object, object>)vtrn1_u32);
            RegisterFunction("vtrn1_u8", (Func<object, object, object>)vtrn1_u8);
            RegisterFunction("vtrn1q_f32", (Func<object, object, object>)vtrn1q_f32);
            RegisterFunction("vtrn1q_f64", (Func<object, object, object>)vtrn1q_f64);
            RegisterFunction("vtrn1q_s16", (Func<object, object, object>)vtrn1q_s16);
            RegisterFunction("vtrn1q_s32", (Func<object, object, object>)vtrn1q_s32);
            RegisterFunction("vtrn1q_s64", (Func<object, object, object>)vtrn1q_s64);
            RegisterFunction("vtrn1q_u16", (Func<object, object, object>)vtrn1q_u16);
            RegisterFunction("vtrn1q_u32", (Func<object, object, object>)vtrn1q_u32);
            RegisterFunction("vtrn1q_u64", (Func<object, object, object>)vtrn1q_u64);
            RegisterFunction("vtrn1q_u8", (Func<object, object, object>)vtrn1q_u8);
            RegisterFunction("vtrn2_f32", (Func<object, object, object>)vtrn2_f32);
            RegisterFunction("vtrn2_s16", (Func<object, object, object>)vtrn2_s16);
            RegisterFunction("vtrn2_s32", (Func<object, object, object>)vtrn2_s32);
            RegisterFunction("vtrn2_s8", (Func<object, object, object>)vtrn2_s8);
            RegisterFunction("vtrn2_u16", (Func<object, object, object>)vtrn2_u16);
            RegisterFunction("vtrn2_u32", (Func<object, object, object>)vtrn2_u32);
            RegisterFunction("vtrn2_u8", (Func<object, object, object>)vtrn2_u8);
            RegisterFunction("vtrn2q_f32", (Func<object, object, object>)vtrn2q_f32);
            RegisterFunction("vtrn2q_f64", (Func<object, object, object>)vtrn2q_f64);
            RegisterFunction("vtrn2q_s16", (Func<object, object, object>)vtrn2q_s16);
            RegisterFunction("vtrn2q_s32", (Func<object, object, object>)vtrn2q_s32);
            RegisterFunction("vtrn2q_s64", (Func<object, object, object>)vtrn2q_s64);
            RegisterFunction("vtrn2q_u16", (Func<object, object, object>)vtrn2q_u16);
            RegisterFunction("vtrn2q_u8", (Func<object, object, object>)vtrn2q_u8);
            RegisterFunction("vtst_f64", (Func<object, object, object>)vtst_f64);
            RegisterFunction("vtst_s64", (Func<object, object, object>)vtst_s64);
            RegisterFunction("vtst_u64", (Func<object, object, object>)vtst_u64);
            RegisterFunction("vtstq_f64", (Func<object, object, object>)vtstq_f64);
            RegisterFunction("vtstq_s64", (Func<object, object, object>)vtstq_s64);
            RegisterFunction("vtstq_u64", (Func<object, object, object>)vtstq_u64);
            RegisterFunction("vuqadd_s16", (Func<object, object, object>)vuqadd_s16);
            RegisterFunction("vuqadd_s32", (Func<object, object, object>)vuqadd_s32);
            RegisterFunction("vuqadd_s64", (Func<object, object, object>)vuqadd_s64);
            RegisterFunction("vuqadd_s8", (Func<object, object, object>)vuqadd_s8);
            RegisterFunction("vuqaddb_s8", (Func<object, object, object>)vuqaddb_s8);
            RegisterFunction("vuqaddh_s16", (Func<object, object, object>)vuqaddh_s16);
            RegisterFunction("vuqaddq_s16", (Func<object, object, object>)vuqaddq_s16);
            RegisterFunction("vuqaddq_s32", (Func<object, object, object>)vuqaddq_s32);
            RegisterFunction("vuqaddq_s64", (Func<object, object, object>)vuqaddq_s64);
            RegisterFunction("vuqaddq_s8", (Func<object, object, object>)vuqaddq_s8);
            RegisterFunction("vuqadds_s32", (Func<object, object, object>)vuqadds_s32);
            RegisterFunction("vuzp1_f32", (Func<object, object, object>)vuzp1_f32);
            RegisterFunction("vuzp1_s16", (Func<object, object, object>)vuzp1_s16);
            RegisterFunction("vuzp1_s32", (Func<object, object, object>)vuzp1_s32);
            RegisterFunction("vuzp1_s8", (Func<object, object, object>)vuzp1_s8);
            RegisterFunction("vuzp1_u16", (Func<object, object, object>)vuzp1_u16);
            RegisterFunction("vuzp1_u32", (Func<object, object, object>)vuzp1_u32);
            RegisterFunction("vuzp1_u8", (Func<object, object, object>)vuzp1_u8);
            RegisterFunction("vuzp1q_f32", (Func<object, object, object>)vuzp1q_f32);
            RegisterFunction("vuzp1q_f64", (Func<object, object, object>)vuzp1q_f64);
            RegisterFunction("vuzp1q_s16", (Func<object, object, object>)vuzp1q_s16);
            RegisterFunction("vuzp1q_s32", (Func<object, object, object>)vuzp1q_s32);
            RegisterFunction("vuzp1q_s64", (Func<object, object, object>)vuzp1q_s64);
            RegisterFunction("vuzp1q_u16", (Func<object, object, object>)vuzp1q_u16);
            RegisterFunction("vuzp1q_u32", (Func<object, object, object>)vuzp1q_u32);
            RegisterFunction("vuzp1q_u64", (Func<object, object, object>)vuzp1q_u64);
            RegisterFunction("vuzp1q_u8", (Func<object, object, object>)vuzp1q_u8);
            RegisterFunction("vuzp2_f32", (Func<object, object, object>)vuzp2_f32);
            RegisterFunction("vuzp2_s16", (Func<object, object, object>)vuzp2_s16);
            RegisterFunction("vuzp2_s32", (Func<object, object, object>)vuzp2_s32);
            RegisterFunction("vuzp2_s8", (Func<object, object, object>)vuzp2_s8);
            RegisterFunction("vuzp2_u16", (Func<object, object, object>)vuzp2_u16);
            RegisterFunction("vuzp2_u32", (Func<object, object, object>)vuzp2_u32);
            RegisterFunction("vuzp2_u8", (Func<object, object, object>)vuzp2_u8);
            RegisterFunction("vuzp2q_f64", (Func<object, object, object>)vuzp2q_f64);
            RegisterFunction("vuzp2q_s16", (Func<object, object, object>)vuzp2q_s16);
            RegisterFunction("vuzp2q_s32", (Func<object, object, object>)vuzp2q_s32);
            RegisterFunction("vuzp2q_s64", (Func<object, object, object>)vuzp2q_s64);
            RegisterFunction("vuzp2q_u16", (Func<object, object, object>)vuzp2q_u16);
            RegisterFunction("vuzp2q_u32", (Func<object, object, object>)vuzp2q_u32);
            RegisterFunction("vuzp2q_u64", (Func<object, object, object>)vuzp2q_u64);
            RegisterFunction("vuzp2q_u8", (Func<object, object, object>)vuzp2q_u8);
            RegisterFunction("vzip1_f32", (Func<object, object, object>)vzip1_f32);
            RegisterFunction("vzip1_s16", (Func<object, object, object>)vzip1_s16);
            RegisterFunction("vzip1_s32", (Func<object, object, object>)vzip1_s32);
            RegisterFunction("vzip1_s8", (Func<object, object, object>)vzip1_s8);
            RegisterFunction("vzip1_u16", (Func<object, object, object>)vzip1_u16);
            RegisterFunction("vzip1_u32", (Func<object, object, object>)vzip1_u32);
            RegisterFunction("vzip1_u8", (Func<object, object, object>)vzip1_u8);
            RegisterFunction("vzip1q_f32", (Func<object, object, object>)vzip1q_f32);
            RegisterFunction("vzip1q_f64", (Func<object, object, object>)vzip1q_f64);
            RegisterFunction("vzip1q_s16", (Func<object, object, object>)vzip1q_s16);
            RegisterFunction("vzip1q_s32", (Func<object, object, object>)vzip1q_s32);
            RegisterFunction("vzip1q_s64", (Func<object, object, object>)vzip1q_s64);
            RegisterFunction("vzip1q_u16", (Func<object, object, object>)vzip1q_u16);
            RegisterFunction("vzip1q_u32", (Func<object, object, object>)vzip1q_u32);
            RegisterFunction("vzip1q_u64", (Func<object, object, object>)vzip1q_u64);
            RegisterFunction("vzip1q_u8", (Func<object, object, object>)vzip1q_u8);
            RegisterFunction("vzip2_f32", (Func<object, object, object>)vzip2_f32);
            RegisterFunction("vzip2_s16", (Func<object, object, object>)vzip2_s16);
            RegisterFunction("vzip2_s32", (Func<object, object, object>)vzip2_s32);
            RegisterFunction("vzip2_s8", (Func<object, object, object>)vzip2_s8);
            RegisterFunction("vzip2_u16", (Func<object, object, object>)vzip2_u16);
            RegisterFunction("vzip2_u32", (Func<object, object, object>)vzip2_u32);
            RegisterFunction("vzip2_u8", (Func<object, object, object>)vzip2_u8);
            RegisterFunction("vzip2q_f32", (Func<object, object, object>)vzip2q_f32);
            RegisterFunction("vzip2q_f64", (Func<object, object, object>)vzip2q_f64);
            RegisterFunction("vzip2q_s16", (Func<object, object, object>)vzip2q_s16);
            RegisterFunction("vzip2q_s32", (Func<object, object, object>)vzip2q_s32);
            RegisterFunction("vzip2q_s64", (Func<object, object, object>)vzip2q_s64);
            RegisterFunction("vzip2q_u16", (Func<object, object, object>)vzip2q_u16);
            RegisterFunction("vzip2q_u32", (Func<object, object, object>)vzip2q_u32);
            RegisterFunction("vzip2q_u64", (Func<object, object, object>)vzip2q_u64);
            RegisterFunction("vzip2q_u8", (Func<object, object, object>)vzip2q_u8);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["vabd_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vabd_f64 (float64x1_t a, float64x1_t b)
    A64: FABD Dd, Dn, Dm
    
    
    Instruction Documentation: [vabd_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vabdq_f64 (float64x2_t a, float64x2_t b)
    A64: FABD Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vabdq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabds_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vabds_f32 (float32_t a, float32_t b)
    A64: FABD Sd, Sn, Sm
    
    
    Instruction Documentation: [vabds_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabds_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabs_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vabs_s64 (int64x1_t a)
    A64: ABS Dd, Dn
    
    
    Instruction Documentation: [vabs_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabsq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vabsq_f64 (float64x2_t a)
    A64: FABS Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vabsq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabsq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vabsq_s64 (int64x2_t a)
    A64: ABS Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vabsq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddlv_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vaddlv_s16 (int16x4_t a)
    A64: SADDLV Sd, Vn.4H
    
    
    Instruction Documentation: [vaddlv_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddlv_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vaddlv_s8 (int8x8_t a)
    A64: SADDLV Hd, Vn.8B
    
    
    Instruction Documentation: [vaddlv_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddlv_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vaddlv_u16 (uint16x4_t a)
    A64: UADDLV Sd, Vn.4H
    
    
    Instruction Documentation: [vaddlv_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddlv_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vaddlv_u8 (uint8x8_t a)
    A64: UADDLV Hd, Vn.8B
    
    
    Instruction Documentation: [vaddlv_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlv_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddlvq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vaddlvq_s16 (int16x8_t a)
    A64: SADDLV Sd, Vn.8H
    
    
    Instruction Documentation: [vaddlvq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddlvq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64_t vaddlvq_s32 (int32x4_t a)
    A64: SADDLV Dd, Vn.4S
    
    
    Instruction Documentation: [vaddlvq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddlvq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vaddlvq_s8 (int8x16_t a)
    A64: SADDLV Hd, Vn.16B
    
    
    Instruction Documentation: [vaddlvq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddlvq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vaddlvq_u16 (uint16x8_t a)
    A64: UADDLV Sd, Vn.8H
    
    
    Instruction Documentation: [vaddlvq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddlvq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64_t vaddlvq_u32 (uint32x4_t a)
    A64: UADDLV Dd, Vn.4S
    
    
    Instruction Documentation: [vaddlvq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddlvq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vaddlvq_u8 (uint8x16_t a)
    A64: UADDLV Hd, Vn.16B
    
    
    Instruction Documentation: [vaddlvq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddlvq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vaddq_f64 (float64x2_t a, float64x2_t b)
    A64: FADD Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vaddq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddv_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vaddv_s16 (int16x4_t a)
    A64: ADDV Hd, Vn.4H
    
    
    Instruction Documentation: [vaddv_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddv_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vaddv_s8 (int8x8_t a)
    A64: ADDV Bd, Vn.8B
    
    
    Instruction Documentation: [vaddv_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddv_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vaddv_u16 (uint16x4_t a)
    A64: ADDV Hd, Vn.4H
    
    
    Instruction Documentation: [vaddv_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddv_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vaddv_u8 (uint8x8_t a)
    A64: ADDV Bd, Vn.8B
    
    
    Instruction Documentation: [vaddv_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddv_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddvq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vaddvq_s16 (int16x8_t a)
    A64: ADDV Hd, Vn.8H
    
    
    Instruction Documentation: [vaddvq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddvq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vaddvq_s32 (int32x4_t a)
    A64: ADDV Sd, Vn.4S
    
    
    Instruction Documentation: [vaddvq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddvq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vaddvq_s8 (int8x16_t a)
    A64: ADDV Bd, Vn.16B
    
    
    Instruction Documentation: [vaddvq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddvq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vaddvq_u16 (uint16x8_t a)
    A64: ADDV Hd, Vn.8H
    
    
    Instruction Documentation: [vaddvq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddvq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vaddvq_u32 (uint32x4_t a)
    A64: ADDV Sd, Vn.4S
    
    
    Instruction Documentation: [vaddvq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddvq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vaddvq_u8 (uint8x16_t a)
    A64: ADDV Bd, Vn.16B
    
    
    Instruction Documentation: [vaddvq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddvq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcage_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcage_f64 (float64x1_t a, float64x1_t b)
    A64: FACGE Dd, Dn, Dm
    
    
    Instruction Documentation: [vcage_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcageq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcageq_f64 (float64x2_t a, float64x2_t b)
    A64: FACGE Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcageq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcages_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcages_f32 (float32_t a, float32_t b)
    A64: FACGE Sd, Sn, Sm
    
    
    Instruction Documentation: [vcages_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcages_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcagt_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcagt_f64 (float64x1_t a, float64x1_t b)
    A64: FACGT Dd, Dn, Dm
    
    
    Instruction Documentation: [vcagt_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcagtq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcagtq_f64 (float64x2_t a, float64x2_t b)
    A64: FACGT Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcagtq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcagts_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcagts_f32 (float32_t a, float32_t b)
    A64: FACGT Sd, Sn, Sm
    
    
    Instruction Documentation: [vcagts_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagts_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcale_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcale_f64 (float64x1_t a, float64x1_t b)
    A64: FACGE Dd, Dn, Dm
    
    
    Instruction Documentation: [vcale_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcaleq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcaleq_f64 (float64x2_t a, float64x2_t b)
    A64: FACGE Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcaleq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcales_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcales_f32 (float32_t a, float32_t b)
    A64: FACGE Sd, Sn, Sm
    
    
    Instruction Documentation: [vcales_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcales_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcalt_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcalt_f64 (float64x1_t a, float64x1_t b)
    A64: FACGT Dd, Dn, Dm
    
    
    Instruction Documentation: [vcalt_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcaltq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcaltq_f64 (float64x2_t a, float64x2_t b)
    A64: FACGT Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcaltq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcalts_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcalts_f32 (float32_t a, float32_t b)
    A64: FACGT Sd, Sn, Sm
    
    
    Instruction Documentation: [vcalts_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalts_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vceq_f64 (float64x1_t a, float64x1_t b)
    A64: FCMEQ Dd, Dn, Dm
    
    
    Instruction Documentation: [vceq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vceq_s64 (int64x1_t a, int64x1_t b)
    A64: CMEQ Dd, Dn, Dm
    
    
    Instruction Documentation: [vceq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vceq_u64 (uint64x1_t a, uint64x1_t b)
    A64: CMEQ Dd, Dn, Dm
    
    
    Instruction Documentation: [vceq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceqq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vceqq_f64 (float64x2_t a, float64x2_t b)
    A64: FCMEQ Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vceqq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceqq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vceqq_s64 (int64x2_t a, int64x2_t b)
    A64: CMEQ Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vceqq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceqq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vceqq_u64 (uint64x2_t a, uint64x2_t b)
    A64: CMEQ Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vceqq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceqs_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vceqs_f32 (float32_t a, float32_t b)
    A64: FCMEQ Sd, Sn, Sm
    
    
    Instruction Documentation: [vceqs_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqs_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcge_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcge_f64 (float64x1_t a, float64x1_t b)
    A64: FCMGE Dd, Dn, Dm
    
    
    Instruction Documentation: [vcge_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcge_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcge_s64 (int64x1_t a, int64x1_t b)
    A64: CMGE Dd, Dn, Dm
    
    
    Instruction Documentation: [vcge_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcge_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcge_u64 (uint64x1_t a, uint64x1_t b)
    A64: CMHS Dd, Dn, Dm
    
    
    Instruction Documentation: [vcge_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgeq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcgeq_f64 (float64x2_t a, float64x2_t b)
    A64: FCMGE Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcgeq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgeq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcgeq_s64 (int64x2_t a, int64x2_t b)
    A64: CMGE Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcgeq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgeq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcgeq_u64 (uint64x2_t a, uint64x2_t b)
    A64: CMHS Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcgeq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcges_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcges_f32 (float32_t a, float32_t b)
    A64: FCMGE Sd, Sn, Sm
    
    
    Instruction Documentation: [vcges_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcges_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgt_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcgt_f64 (float64x1_t a, float64x1_t b)
    A64: FCMGT Dd, Dn, Dm
    
    
    Instruction Documentation: [vcgt_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgt_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcgt_s64 (int64x1_t a, int64x1_t b)
    A64: CMGT Dd, Dn, Dm
    
    
    Instruction Documentation: [vcgt_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgt_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcgt_u64 (uint64x1_t a, uint64x1_t b)
    A64: CMHI Dd, Dn, Dm
    
    
    Instruction Documentation: [vcgt_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgtq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcgtq_f64 (float64x2_t a, float64x2_t b)
    A64: FCMGT Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcgtq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgtq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcgtq_s64 (int64x2_t a, int64x2_t b)
    A64: CMGT Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcgtq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgtq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcgtq_u64 (uint64x2_t a, uint64x2_t b)
    A64: CMHI Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcgtq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgts_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcgts_f32 (float32_t a, float32_t b)
    A64: FCMGT Sd, Sn, Sm
    
    
    Instruction Documentation: [vcgts_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgts_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcle_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcle_f64 (float64x1_t a, float64x1_t b)
    A64: FCMGE Dd, Dn, Dm
    
    
    Instruction Documentation: [vcle_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcle_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcle_s64 (int64x1_t a, int64x1_t b)
    A64: CMGE Dd, Dn, Dm
    
    
    Instruction Documentation: [vcle_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcle_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcle_u64 (uint64x1_t a, uint64x1_t b)
    A64: CMHS Dd, Dn, Dm
    
    
    Instruction Documentation: [vcle_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcleq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcleq_f64 (float64x2_t a, float64x2_t b)
    A64: FCMGE Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcleq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcleq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcleq_s64 (int64x2_t a, int64x2_t b)
    A64: CMGE Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcleq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcleq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcleq_u64 (uint64x2_t a, uint64x2_t b)
    A64: CMHS Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcleq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcles_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcles_f32 (float32_t a, float32_t b)
    A64: FCMGE Sd, Sn, Sm
    
    
    Instruction Documentation: [vcles_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcles_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclt_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vclt_f64 (float64x1_t a, float64x1_t b)
    A64: FCMGT Dd, Dn, Dm
    
    
    Instruction Documentation: [vclt_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclt_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vclt_s64 (int64x1_t a, int64x1_t b)
    A64: CMGT Dd, Dn, Dm
    
    
    Instruction Documentation: [vclt_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclt_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vclt_u64 (uint64x1_t a, uint64x1_t b)
    A64: CMHI Dd, Dn, Dm
    
    
    Instruction Documentation: [vclt_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcltq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcltq_f64 (float64x2_t a, float64x2_t b)
    A64: FCMGT Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcltq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcltq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcltq_s64 (int64x2_t a, int64x2_t b)
    A64: CMGT Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcltq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcltq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcltq_u64 (uint64x2_t a, uint64x2_t b)
    A64: CMHI Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vcltq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclts_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vclts_f32 (float32_t a, float32_t b)
    A64: FCMGT Sd, Sn, Sm
    
    
    Instruction Documentation: [vclts_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclts_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vcopy_lane_f32 (float32x2_t a, const int lane1, float32x2_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopy_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vcopy_lane_s16 (int16x4_t a, const int lane1, int16x4_t b, const int lane2)
    A64: INS Vd.H[lane1], Vn.H[lane2]
    
    
    Instruction Documentation: [vcopy_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vcopy_lane_s32 (int32x2_t a, const int lane1, int32x2_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopy_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vcopy_lane_s8 (int8x8_t a, const int lane1, int8x8_t b, const int lane2)
    A64: INS Vd.B[lane1], Vn.B[lane2]
    
    
    Instruction Documentation: [vcopy_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vcopy_lane_u16 (uint16x4_t a, const int lane1, uint16x4_t b, const int lane2)
    A64: INS Vd.H[lane1], Vn.H[lane2]
    
    
    Instruction Documentation: [vcopy_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcopy_lane_u32 (uint32x2_t a, const int lane1, uint32x2_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopy_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vcopy_lane_u8 (uint8x8_t a, const int lane1, uint8x8_t b, const int lane2)
    A64: INS Vd.B[lane1], Vn.B[lane2]
    
    
    Instruction Documentation: [vcopy_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_lane_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vcopy_laneq_f32 (float32x2_t a, const int lane1, float32x4_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopy_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vcopy_laneq_s16 (int16x4_t a, const int lane1, int16x8_t b, const int lane2)
    A64: INS Vd.H[lane1], Vn.H[lane2]
    
    
    Instruction Documentation: [vcopy_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vcopy_laneq_s32 (int32x2_t a, const int lane1, int32x4_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopy_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_laneq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vcopy_laneq_s8 (int8x8_t a, const int lane1, int8x16_t b, const int lane2)
    A64: INS Vd.B[lane1], Vn.B[lane2]
    
    
    Instruction Documentation: [vcopy_laneq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vcopy_laneq_u16 (uint16x4_t a, const int lane1, uint16x8_t b, const int lane2)
    A64: INS Vd.H[lane1], Vn.H[lane2]
    
    
    Instruction Documentation: [vcopy_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcopy_laneq_u32 (uint32x2_t a, const int lane1, uint32x4_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopy_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopy_laneq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vcopy_laneq_u8 (uint8x8_t a, const int lane1, uint8x16_t b, const int lane2)
    A64: INS Vd.B[lane1], Vn.B[lane2]
    
    
    Instruction Documentation: [vcopy_laneq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopy_laneq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vcopyq_lane_f32 (float32x4_t a, const int lane1, float32x2_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopyq_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vcopyq_lane_s16 (int16x8_t a, const int lane1, int16x4_t b, const int lane2)
    A64: INS Vd.H[lane1], Vn.H[lane2]
    
    
    Instruction Documentation: [vcopyq_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vcopyq_lane_s32 (int32x4_t a, const int lane1, int32x2_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopyq_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vcopyq_lane_s8 (int8x16_t a, const int lane1, int8x8_t b, const int lane2)
    A64: INS Vd.B[lane1], Vn.B[lane2]
    
    
    Instruction Documentation: [vcopyq_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vcopyq_lane_u16 (uint16x8_t a, const int lane1, uint16x4_t b, const int lane2)
    A64: INS Vd.H[lane1], Vn.H[lane2]
    
    
    Instruction Documentation: [vcopyq_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcopyq_lane_u32 (uint32x4_t a, const int lane1, uint32x2_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopyq_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vcopyq_lane_u8 (uint8x16_t a, const int lane1, uint8x8_t b, const int lane2)
    A64: INS Vd.B[lane1], Vn.B[lane2]
    
    
    Instruction Documentation: [vcopyq_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_lane_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vcopyq_laneq_f32 (float32x4_t a, const int lane1, float32x4_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopyq_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_laneq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vcopyq_laneq_f64 (float64x2_t a, const int lane1, float64x2_t b, const int lane2)
    A64: INS Vd.D[lane1], Vn.D[lane2]
    
    
    Instruction Documentation: [vcopyq_laneq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vcopyq_laneq_s16 (int16x8_t a, const int lane1, int16x8_t b, const int lane2)
    A64: INS Vd.H[lane1], Vn.H[lane2]
    
    
    Instruction Documentation: [vcopyq_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vcopyq_laneq_s32 (int32x4_t a, const int lane1, int32x4_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopyq_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_laneq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vcopyq_laneq_s64 (int64x2_t a, const int lane1, int64x2_t b, const int lane2)
    A64: INS Vd.D[lane1], Vn.D[lane2]
    
    
    Instruction Documentation: [vcopyq_laneq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_laneq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vcopyq_laneq_s8 (int8x16_t a, const int lane1, int8x16_t b, const int lane2)
    A64: INS Vd.B[lane1], Vn.B[lane2]
    
    
    Instruction Documentation: [vcopyq_laneq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vcopyq_laneq_u16 (uint16x8_t a, const int lane1, uint16x8_t b, const int lane2)
    A64: INS Vd.H[lane1], Vn.H[lane2]
    
    
    Instruction Documentation: [vcopyq_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcopyq_laneq_u32 (uint32x4_t a, const int lane1, uint32x4_t b, const int lane2)
    A64: INS Vd.S[lane1], Vn.S[lane2]
    
    
    Instruction Documentation: [vcopyq_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_laneq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcopyq_laneq_u64 (uint64x2_t a, const int lane1, uint64x2_t b, const int lane2)
    A64: INS Vd.D[lane1], Vn.D[lane2]
    
    
    Instruction Documentation: [vcopyq_laneq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcopyq_laneq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vcopyq_laneq_u8 (uint8x16_t a, const int lane1, uint8x16_t b, const int lane2)
    A64: INS Vd.B[lane1], Vn.B[lane2]
    
    
    Instruction Documentation: [vcopyq_laneq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcopyq_laneq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_f32_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vcvt_f32_f64 (float64x2_t a)
    A64: FCVTN Vd.2S, Vn.2D
    
    
    Instruction Documentation: [vcvt_f32_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_f64_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vcvt_f64_f32 (float32x2_t a)
    A64: FCVTL Vd.2D, Vn.2S
    
    
    Instruction Documentation: [vcvt_f64_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_f64_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vcvt_f64_s64 (int64x1_t a)
    A64: SCVTF Dd, Dn
    
    
    Instruction Documentation: [vcvt_f64_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_f64_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vcvt_f64_u64 (uint64x1_t a)
    A64: UCVTF Dd, Dn
    
    
    Instruction Documentation: [vcvt_f64_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f64_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_high_f32_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vcvt_high_f32_f64 (float32x2_t r, float64x2_t a)
    A64: FCVTN2 Vd.4S, Vn.2D
    
    
    Instruction Documentation: [vcvt_high_f32_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f32_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_high_f64_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vcvt_high_f64_f32 (float32x4_t a)
    A64: FCVTL2 Vd.2D, Vn.4S
    
    
    Instruction Documentation: [vcvt_high_f64_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_high_f64_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_s64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vcvt_s64_f64 (float64x1_t a)
    A64: FCVTZS Dd, Dn
    
    
    Instruction Documentation: [vcvt_s64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_u64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcvt_u64_f64 (float64x1_t a)
    A64: FCVTZU Dd, Dn
    
    
    Instruction Documentation: [vcvt_u64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvta_s64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vcvta_s64_f64 (float64x1_t a)
    A64: FCVTAS Dd, Dn
    
    
    Instruction Documentation: [vcvta_s64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvta_u64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcvta_u64_f64 (float64x1_t a)
    A64: FCVTAU Dd, Dn
    
    
    Instruction Documentation: [vcvta_u64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtaq_s64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vcvtaq_s64_f64 (float64x2_t a)
    A64: FCVTAS Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtaq_s64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtaq_u64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcvtaq_u64_f64 (float64x2_t a)
    A64: FCVTAU Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtaq_u64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtm_s64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vcvtm_s64_f64 (float64x1_t a)
    A64: FCVTMS Dd, Dn
    
    
    Instruction Documentation: [vcvtm_s64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtm_u64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcvtm_u64_f64 (float64x1_t a)
    A64: FCVTMU Dd, Dn
    
    
    Instruction Documentation: [vcvtm_u64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtmq_s64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vcvtmq_s64_f64 (float64x2_t a)
    A64: FCVTMS Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtmq_s64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtmq_u64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcvtmq_u64_f64 (float64x2_t a)
    A64: FCVTMU Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtmq_u64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtn_s64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vcvtn_s64_f64 (float64x1_t a)
    A64: FCVTNS Dd, Dn
    
    
    Instruction Documentation: [vcvtn_s64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtn_u64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcvtn_u64_f64 (float64x1_t a)
    A64: FCVTNU Dd, Dn
    
    
    Instruction Documentation: [vcvtn_u64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtnq_s64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vcvtnq_s64_f64 (float64x2_t a)
    A64: FCVTNS Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtnq_s64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtnq_u64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcvtnq_u64_f64 (float64x2_t a)
    A64: FCVTNU Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtnq_u64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtp_s64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vcvtp_s64_f64 (float64x1_t a)
    A64: FCVTPS Dd, Dn
    
    
    Instruction Documentation: [vcvtp_s64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtp_u64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vcvtp_u64_f64 (float64x1_t a)
    A64: FCVTPU Dd, Dn
    
    
    Instruction Documentation: [vcvtp_u64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtpq_s64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vcvtpq_s64_f64 (float64x2_t a)
    A64: FCVTPS Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtpq_s64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtpq_u64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcvtpq_u64_f64 (float64x2_t a)
    A64: FCVTPU Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtpq_u64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtq_f64_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vcvtq_f64_s64 (int64x2_t a)
    A64: SCVTF Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtq_f64_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtq_f64_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vcvtq_f64_u64 (uint64x2_t a)
    A64: UCVTF Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtq_f64_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f64_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtq_s64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vcvtq_s64_f64 (float64x2_t a)
    A64: FCVTZS Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtq_s64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtq_u64_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vcvtq_u64_f64 (float64x2_t a)
    A64: FCVTZU Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vcvtq_u64_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u64_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtx_f32_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vcvtx_f32_f64 (float64x2_t a)
    A64: FCVTXN Vd.2S, Vn.2D
    
    
    Instruction Documentation: [vcvtx_f32_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_f32_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtx_high_f32_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vcvtx_high_f32_f64 (float32x2_t r, float64x2_t a)
    A64: FCVTXN2 Vd.4S, Vn.2D
    
    
    Instruction Documentation: [vcvtx_high_f32_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtx_high_f32_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdiv_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vdiv_f32 (float32x2_t a, float32x2_t b)
    A64: FDIV Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vdiv_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdivq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vdivq_f32 (float32x4_t a, float32x4_t b)
    A64: FDIV Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vdivq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdivq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vdivq_f64 (float64x2_t a, float64x2_t b)
    A64: FDIV Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vdivq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_laneq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vdupq_laneq_f64 (float64x2_t vec, const int lane)
    A64: DUP Vd.2D, Vn.D[index]
    
    
    Instruction Documentation: [vdupq_laneq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_laneq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vdupq_laneq_s64 (int64x2_t vec, const int lane)
    A64: DUP Vd.2D, Vn.D[index]
    
    
    Instruction Documentation: [vdupq_laneq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_laneq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vdupq_laneq_u64 (uint64x2_t vec, const int lane)
    A64: DUP Vd.2D, Vn.D[index]
    
    
    Instruction Documentation: [vdupq_laneq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_laneq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_n_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vdupq_n_f64 (float64_t value)
    A64: DUP Vd.2D, Vn.D[0]
    
    
    Instruction Documentation: [vdupq_n_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vdupq_n_s64 (int64_t value)
    A64: DUP Vd.2D, Rn
    
    
    Instruction Documentation: [vdupq_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfma_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vfma_lane_f32 (float32x2_t a, float32x2_t b, float32x2_t v, const int lane)
    A64: FMLA Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vfma_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfma_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vfma_laneq_f32 (float32x2_t a, float32x2_t b, float32x4_t v, const int lane)
    A64: FMLA Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vfma_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfma_n_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vfma_n_f32 (float32x2_t a, float32x2_t b, float32_t n)
    A64: FMLA Vd.2S, Vn.2S, Vm.S[0]
    
    
    Instruction Documentation: [vfma_n_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_n_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmad_laneq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64_t vfmad_laneq_f64 (float64_t a, float64_t b, float64x2_t v, const int lane)
    A64: FMLA Dd, Dn, Vm.D[lane]
    
    
    Instruction Documentation: [vfmad_laneq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmad_laneq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmaq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vfmaq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
    A64: FMLA Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vfmaq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmaq_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vfmaq_lane_f32 (float32x4_t a, float32x4_t b, float32x2_t v, const int lane)
    A64: FMLA Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vfmaq_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmaq_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vfmaq_laneq_f32 (float32x4_t a, float32x4_t b, float32x4_t v, const int lane)
    A64: FMLA Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vfmaq_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmaq_laneq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vfmaq_laneq_f64 (float64x2_t a, float64x2_t b, float64x2_t v, const int lane)
    A64: FMLA Vd.2D, Vn.2D, Vm.D[lane]
    
    
    Instruction Documentation: [vfmaq_laneq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_laneq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmaq_n_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vfmaq_n_f32 (float32x4_t a, float32x4_t b, float32_t n)
    A64: FMLA Vd.4S, Vn.4S, Vm.S[0]
    
    
    Instruction Documentation: [vfmaq_n_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmaq_n_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vfmaq_n_f64 (float64x2_t a, float64x2_t b, float64_t n)
    A64: FMLA Vd.2D, Vn.2D, Vm.D[0]
    
    
    Instruction Documentation: [vfmaq_n_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_n_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmas_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vfmas_lane_f32 (float32_t a, float32_t b, float32x2_t v, const int lane)
    A64: FMLA Sd, Sn, Vm.S[lane]
    
    
    Instruction Documentation: [vfmas_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmas_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vfmas_laneq_f32 (float32_t a, float32_t b, float32x4_t v, const int lane)
    A64: FMLA Sd, Sn, Vm.S[lane]
    
    
    Instruction Documentation: [vfmas_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfms_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vfms_lane_f32 (float32x2_t a, float32x2_t b, float32x2_t v, const int lane)
    A64: FMLS Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vfms_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfms_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vfms_laneq_f32 (float32x2_t a, float32x2_t b, float32x4_t v, const int lane)
    A64: FMLS Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vfms_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfms_n_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vfms_n_f32 (float32x2_t a, float32x2_t b, float32_t n)
    A64: FMLS Vd.2S, Vn.2S, Vm.S[0]
    
    
    Instruction Documentation: [vfms_n_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_n_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmsd_laneq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64_t vfmsd_laneq_f64 (float64_t a, float64_t b, float64x2_t v, const int lane)
    A64: FMLS Dd, Dn, Vm.D[lane]
    
    
    Instruction Documentation: [vfmsd_laneq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsd_laneq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmsq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vfmsq_f64 (float64x2_t a, float64x2_t b, float64x2_t c)
    A64: FMLS Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vfmsq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmsq_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vfmsq_lane_f32 (float32x4_t a, float32x4_t b, float32x2_t v, const int lane)
    A64: FMLS Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vfmsq_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmsq_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vfmsq_laneq_f32 (float32x4_t a, float32x4_t b, float32x4_t v, const int lane)
    A64: FMLS Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vfmsq_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmsq_laneq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vfmsq_laneq_f64 (float64x2_t a, float64x2_t b, float64x2_t v, const int lane)
    A64: FMLS Vd.2D, Vn.2D, Vm.D[lane]
    
    
    Instruction Documentation: [vfmsq_laneq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_laneq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmsq_n_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vfmsq_n_f32 (float32x4_t a, float32x4_t b, float32_t n)
    A64: FMLS Vd.4S, Vn.4S, Vm.S[0]
    
    
    Instruction Documentation: [vfmsq_n_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmsq_n_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vfmsq_n_f64 (float64x2_t a, float64x2_t b, float64_t n)
    A64: FMLS Vd.2D, Vn.2D, Vm.D[0]
    
    
    Instruction Documentation: [vfmsq_n_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_n_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmss_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vfmss_lane_f32 (float32_t a, float32_t b, float32x2_t v, const int lane)
    A64: FMLS Sd, Sn, Vm.S[lane]
    
    
    Instruction Documentation: [vfmss_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmss_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vfmss_laneq_f32 (float32_t a, float32_t b, float32x4_t v, const int lane)
    A64: FMLS Sd, Sn, Vm.S[lane]
    
    
    Instruction Documentation: [vfmss_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_dup_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vld1q_dup_f64 (float64_t const * ptr)
    A64: LD1R { Vt.2D }, [Xn]
    
    
    Instruction Documentation: [vld1q_dup_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_dup_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vld1q_dup_s64 (int64_t const * ptr)
    A64: LD1R { Vt.2D }, [Xn]
    
    
    Instruction Documentation: [vld1q_dup_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_dup_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vld1q_dup_u64 (uint64_t const * ptr)
    A64: LD1R { Vt.2D }, [Xn]
    
    
    Instruction Documentation: [vld1q_dup_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmax_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vmax_f64 (float64x1_t a, float64x1_t b)
    A64: FMAX Dd, Dn, Dm
    
    
    Instruction Documentation: [vmax_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxnmq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vmaxnmq_f64 (float64x2_t a, float64x2_t b)
    A64: FMAXNM Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vmaxnmq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxnmvq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vmaxnmvq_f32 (float32x4_t a)
    A64: FMAXNMV Sd, Vn.4S
    
    
    Instruction Documentation: [vmaxnmvq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmvq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vmaxq_f64 (float64x2_t a, float64x2_t b)
    A64: FMAX Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vmaxq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxs_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vmaxs_f32 (float32_t a, float32_t b)
    A64: FMAX Sd, Sn, Sm The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vmaxs_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxs_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxv_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vmaxv_s16 (int16x4_t a)
    A64: SMAXV Hd, Vn.4H
    
    
    Instruction Documentation: [vmaxv_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxv_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vmaxv_s8 (int8x8_t a)
    A64: SMAXV Bd, Vn.8B
    
    
    Instruction Documentation: [vmaxv_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxv_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vmaxv_u16 (uint16x4_t a)
    A64: UMAXV Hd, Vn.4H
    
    
    Instruction Documentation: [vmaxv_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxv_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vmaxv_u8 (uint8x8_t a)
    A64: UMAXV Bd, Vn.8B
    
    
    Instruction Documentation: [vmaxv_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxv_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxvq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vmaxvq_f32 (float32x4_t a)
    A64: FMAXV Sd, Vn.4S
    
    
    Instruction Documentation: [vmaxvq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxvq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vmaxvq_s16 (int16x8_t a)
    A64: SMAXV Hd, Vn.8H
    
    
    Instruction Documentation: [vmaxvq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxvq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vmaxvq_s32 (int32x4_t a)
    A64: SMAXV Sd, Vn.4S
    
    
    Instruction Documentation: [vmaxvq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxvq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vmaxvq_s8 (int8x16_t a)
    A64: SMAXV Bd, Vn.16B
    
    
    Instruction Documentation: [vmaxvq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxvq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vmaxvq_u16 (uint16x8_t a)
    A64: UMAXV Hd, Vn.8H
    
    
    Instruction Documentation: [vmaxvq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxvq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vmaxvq_u32 (uint32x4_t a)
    A64: UMAXV Sd, Vn.4S
    
    
    Instruction Documentation: [vmaxvq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxvq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vmaxvq_u8 (uint8x16_t a)
    A64: UMAXV Bd, Vn.16B
    
    
    Instruction Documentation: [vmaxvq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxvq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmin_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vmin_f64 (float64x1_t a, float64x1_t b)
    A64: FMIN Dd, Dn, Dm
    
    
    Instruction Documentation: [vmin_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminnmq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vminnmq_f64 (float64x2_t a, float64x2_t b)
    A64: FMINNM Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vminnmq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminnmvq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vminnmvq_f32 (float32x4_t a)
    A64: FMINNMV Sd, Vn.4S
    
    
    Instruction Documentation: [vminnmvq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmvq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vminq_f64 (float64x2_t a, float64x2_t b)
    A64: FMIN Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vminq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmins_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vmins_f32 (float32_t a, float32_t b)
    A64: FMIN Sd, Sn, Sm The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vmins_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmins_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminv_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vminv_s16 (int16x4_t a)
    A64: SMINV Hd, Vn.4H
    
    
    Instruction Documentation: [vminv_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminv_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vminv_s8 (int8x8_t a)
    A64: SMINV Bd, Vn.8B
    
    
    Instruction Documentation: [vminv_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminv_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vminv_u16 (uint16x4_t a)
    A64: UMINV Hd, Vn.4H
    
    
    Instruction Documentation: [vminv_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminv_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vminv_u8 (uint8x8_t a)
    A64: UMINV Bd, Vn.8B
    
    
    Instruction Documentation: [vminv_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminv_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminvq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vminvq_f32 (float32x4_t a)
    A64: FMINV Sd, Vn.4S
    
    
    Instruction Documentation: [vminvq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminvq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vminvq_s16 (int16x8_t a)
    A64: SMINV Hd, Vn.8H
    
    
    Instruction Documentation: [vminvq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminvq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vminvq_s8 (int8x16_t a)
    A64: SMINV Bd, Vn.16B
    
    
    Instruction Documentation: [vminvq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminvq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vminvq_u16 (uint16x8_t a)
    A64: UMINV Hd, Vn.8H
    
    
    Instruction Documentation: [vminvq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminvq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vminvq_u32 (uint32x4_t a)
    A64: UMINV Sd, Vn.4S
    
    
    Instruction Documentation: [vminvq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminvq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vminvq_u8 (uint8x16_t a)
    A64: UMINV Bd, Vn.16B
    
    
    Instruction Documentation: [vminvq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminvq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmuld_laneq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64_t vmuld_laneq_f64 (float64_t a, float64x2_t v, const int lane)
    A64: FMUL Dd, Dn, Vm.D[lane]
    
    
    Instruction Documentation: [vmuld_laneq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuld_laneq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vmulq_f64 (float64x2_t a, float64x2_t b)
    A64: FMUL Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vmulq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_laneq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vmulq_laneq_f64 (float64x2_t a, float64x2_t v, const int lane)
    A64: FMUL Vd.2D, Vn.2D, Vm.D[lane]
    
    
    Instruction Documentation: [vmulq_laneq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_n_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vmulq_n_f64 (float64x2_t a, float64_t b)
    A64: FMUL Vd.2D, Vn.2D, Vm.D[0]
    
    
    Instruction Documentation: [vmulq_n_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulx_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vmulx_f32 (float32x2_t a, float32x2_t b)
    A64: FMULX Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmulx_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulx_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vmulx_f64 (float64x1_t a, float64x1_t b)
    A64: FMULX Dd, Dn, Dm
    
    
    Instruction Documentation: [vmulx_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulx_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vmulx_lane_f32 (float32x2_t a, float32x2_t v, const int lane)
    A64: FMULX Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmulx_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulx_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vmulx_laneq_f32 (float32x2_t a, float32x4_t v, const int lane)
    A64: FMULX Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmulx_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulx_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulxd_laneq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64_t vmulxd_laneq_f64 (float64_t a, float64x2_t v, const int lane)
    A64: FMULX Dd, Dn, Vm.D[lane]
    
    
    Instruction Documentation: [vmulxd_laneq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxd_laneq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulxq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vmulxq_f32 (float32x4_t a, float32x4_t b)
    A64: FMULX Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmulxq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulxq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vmulxq_f64 (float64x2_t a, float64x2_t b)
    A64: FMULX Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vmulxq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulxq_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vmulxq_lane_f32 (float32x4_t a, float32x2_t v, const int lane)
    A64: FMULX Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmulxq_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulxq_lane_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vmulxq_lane_f64 (float64x2_t a, float64x1_t v, const int lane)
    A64: FMULX Vd.2D, Vn.2D, Vm.D[0]
    
    
    Instruction Documentation: [vmulxq_lane_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_lane_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulxq_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vmulxq_laneq_f32 (float32x4_t a, float32x4_t v, const int lane)
    A64: FMULX Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmulxq_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulxq_laneq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vmulxq_laneq_f64 (float64x2_t a, float64x2_t v, const int lane)
    A64: FMULX Vd.2D, Vn.2D, Vm.D[lane]
    
    
    Instruction Documentation: [vmulxq_laneq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxq_laneq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulxs_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vmulxs_f32 (float32_t a, float32_t b)
    A64: FMULX Sd, Sn, Sm
    
    
    Instruction Documentation: [vmulxs_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulxs_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vmulxs_lane_f32 (float32_t a, float32x2_t v, const int lane)
    A64: FMULX Sd, Sn, Vm.S[lane]
    
    
    Instruction Documentation: [vmulxs_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulxs_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vmulxs_laneq_f32 (float32_t a, float32x4_t v, const int lane)
    A64: FMULX Sd, Sn, Vm.S[lane]
    
    
    Instruction Documentation: [vmulxs_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulxs_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vneg_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vneg_s64 (int64x1_t a)
    A64: NEG Dd, Dn
    
    
    Instruction Documentation: [vneg_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vnegq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vnegq_f64 (float64x2_t a)
    A64: FNEG Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vnegq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vnegq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vnegq_s64 (int64x2_t a)
    A64: NEG Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vnegq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddd_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64_t vpaddd_f64 (float64x2_t a)
    A64: FADDP Dd, Vn.2D
    
    
    Instruction Documentation: [vpaddd_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddd_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64_t vpaddd_s64 (int64x2_t a)
    A64: ADDP Dd, Vn.2D
    
    
    Instruction Documentation: [vpaddd_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddd_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64_t vpaddd_u64 (uint64x2_t a)
    A64: ADDP Dd, Vn.2D
    
    
    Instruction Documentation: [vpaddd_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddd_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vpaddq_f32 (float32x4_t a, float32x4_t b)
    A64: FADDP Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vpaddq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vpaddq_f64 (float64x2_t a, float64x2_t b)
    A64: FADDP Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vpaddq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vpaddq_s16 (int16x8_t a, int16x8_t b)
    A64: ADDP Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vpaddq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vpaddq_s32 (int32x4_t a, int32x4_t b)
    A64: ADDP Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vpaddq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vpaddq_s64 (int64x2_t a, int64x2_t b)
    A64: ADDP Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vpaddq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vpaddq_s8 (int8x16_t a, int8x16_t b)
    A64: ADDP Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vpaddq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vpaddq_u16 (uint16x8_t a, uint16x8_t b)
    A64: ADDP Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vpaddq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vpaddq_u32 (uint32x4_t a, uint32x4_t b)
    A64: ADDP Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vpaddq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vpaddq_u64 (uint64x2_t a, uint64x2_t b)
    A64: ADDP Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vpaddq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vpaddq_u8 (uint8x16_t a, uint8x16_t b)
    A64: ADDP Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vpaddq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadds_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vpadds_f32 (float32x2_t a)
    A64: FADDP Sd, Vn.2S
    
    
    Instruction Documentation: [vpadds_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadds_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxnm_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vpmaxnm_f32 (float32x2_t a, float32x2_t b)
    A64: FMAXNMP Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vpmaxnm_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnm_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxnmq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vpmaxnmq_f32 (float32x4_t a, float32x4_t b)
    A64: FMAXNMP Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vpmaxnmq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxnmq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vpmaxnmq_f64 (float64x2_t a, float64x2_t b)
    A64: FMAXNMP Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vpmaxnmq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxnmqd_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64_t vpmaxnmqd_f64 (float64x2_t a)
    A64: FMAXNMP Dd, Vn.2D
    
    
    Instruction Documentation: [vpmaxnmqd_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnmqd_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxnms_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vpmaxnms_f32 (float32x2_t a)
    A64: FMAXNMP Sd, Vn.2S
    
    
    Instruction Documentation: [vpmaxnms_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxnms_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vpmaxq_f32 (float32x4_t a, float32x4_t b)
    A64: FMAXP Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vpmaxq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vpmaxq_f64 (float64x2_t a, float64x2_t b)
    A64: FMAXP Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vpmaxq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vpmaxq_s16 (int16x8_t a, int16x8_t b)
    A64: SMAXP Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vpmaxq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vpmaxq_s32 (int32x4_t a, int32x4_t b)
    A64: SMAXP Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vpmaxq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vpmaxq_s8 (int8x16_t a, int8x16_t b)
    A64: SMAXP Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vpmaxq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vpmaxq_u16 (uint16x8_t a, uint16x8_t b)
    A64: UMAXP Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vpmaxq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vpmaxq_u32 (uint32x4_t a, uint32x4_t b)
    A64: UMAXP Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vpmaxq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vpmaxq_u8 (uint8x16_t a, uint8x16_t b)
    A64: UMAXP Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vpmaxq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxqd_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64_t vpmaxqd_f64 (float64x2_t a)
    A64: FMAXP Dd, Vn.2D
    
    
    Instruction Documentation: [vpmaxqd_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxqd_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmaxs_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vpmaxs_f32 (float32x2_t a)
    A64: FMAXP Sd, Vn.2S
    
    
    Instruction Documentation: [vpmaxs_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmaxs_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminnm_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vpminnm_f32 (float32x2_t a, float32x2_t b)
    A64: FMINNMP Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vpminnm_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnm_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminnmq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vpminnmq_f32 (float32x4_t a, float32x4_t b)
    A64: FMINNMP Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vpminnmq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminnmq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vpminnmq_f64 (float64x2_t a, float64x2_t b)
    A64: FMINNMP Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vpminnmq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminnmqd_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64_t vpminnmqd_f64 (float64x2_t a)
    A64: FMINNMP Dd, Vn.2D
    
    
    Instruction Documentation: [vpminnmqd_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnmqd_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminnms_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vpminnms_f32 (float32x2_t a)
    A64: FMINNMP Sd, Vn.2S
    
    
    Instruction Documentation: [vpminnms_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminnms_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vpminq_f32 (float32x4_t a, float32x4_t b)
    A64: FMINP Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vpminq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vpminq_f64 (float64x2_t a, float64x2_t b)
    A64: FMINP Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vpminq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vpminq_s16 (int16x8_t a, int16x8_t b)
    A64: SMINP Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vpminq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vpminq_s32 (int32x4_t a, int32x4_t b)
    A64: SMINP Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vpminq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vpminq_s8 (int8x16_t a, int8x16_t b)
    A64: SMINP Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vpminq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vpminq_u16 (uint16x8_t a, uint16x8_t b)
    A64: UMINP Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vpminq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vpminq_u32 (uint32x4_t a, uint32x4_t b)
    A64: UMINP Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vpminq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vpminq_u8 (uint8x16_t a, uint8x16_t b)
    A64: UMINP Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vpminq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpminqd_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64_t vpminqd_f64 (float64x2_t a)
    A64: FMINP Dd, Vn.2D
    
    
    Instruction Documentation: [vpminqd_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpminqd_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmins_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vpmins_f32 (float32x2_t a)
    A64: FMINP Sd, Vn.2S
    
    
    Instruction Documentation: [vpmins_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmins_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqabsb_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vqabsb_s8 (int8_t a)
    A64: SQABS Bd, Bn
    
    
    Instruction Documentation: [vqabsb_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsb_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqabsd_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64_t vqabsd_s64 (int64_t a)
    A64: SQABS Dd, Dn
    
    
    Instruction Documentation: [vqabsd_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsd_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqabsh_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vqabsh_s16 (int16_t a)
    A64: SQABS Hd, Hn
    
    
    Instruction Documentation: [vqabsh_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsh_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqabsq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vqabsq_s64 (int64x2_t a)
    A64: SQABS Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vqabsq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqabss_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vqabss_s32 (int32_t a)
    A64: SQABS Sd, Sn
    
    
    Instruction Documentation: [vqabss_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabss_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddb_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vqaddb_s8 (int8_t a, int8_t b)
    A64: SQADD Bd, Bn, Bm
    
    
    Instruction Documentation: [vqaddb_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddb_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vqaddb_u8 (uint8_t a, uint8_t b)
    A64: UQADD Bd, Bn, Bm
    
    
    Instruction Documentation: [vqaddb_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddb_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddh_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vqaddh_s16 (int16_t a, int16_t b)
    A64: SQADD Hd, Hn, Hm
    
    
    Instruction Documentation: [vqaddh_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddh_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vqaddh_u16 (uint16_t a, uint16_t b)
    A64: UQADD Hd, Hn, Hm
    
    
    Instruction Documentation: [vqaddh_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddh_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqadds_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vqadds_s32 (int32_t a, int32_t b)
    A64: SQADD Sd, Sn, Sm
    
    
    Instruction Documentation: [vqadds_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqadds_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vqadds_u32 (uint32_t a, uint32_t b)
    A64: UQADD Sd, Sn, Sm
    
    
    Instruction Documentation: [vqadds_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadds_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqnegb_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vqnegb_s8 (int8_t a)
    A64: SQNEG Bd, Bn
    
    
    Instruction Documentation: [vqnegb_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegb_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqnegd_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64_t vqnegd_s64 (int64_t a)
    A64: SQNEG Dd, Dn
    
    
    Instruction Documentation: [vqnegd_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegd_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqnegh_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vqnegh_s16 (int16_t a)
    A64: SQNEG Hd, Hn
    
    
    Instruction Documentation: [vqnegh_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegh_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqnegq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vqnegq_s64 (int64x2_t a)
    A64: SQNEG Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vqnegq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqnegs_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vqnegs_s32 (int32_t a)
    A64: SQNEG Sd, Sn
    
    
    Instruction Documentation: [vqnegs_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegs_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlb_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vqrshlb_s8 (int8_t a, int8_t b)
    A64: SQRSHL Bd, Bn, Bm
    
    
    Instruction Documentation: [vqrshlb_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlb_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vqrshlb_u8 (uint8_t a, int8_t b)
    A64: UQRSHL Bd, Bn, Bm
    
    
    Instruction Documentation: [vqrshlb_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlb_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlh_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vqrshlh_s16 (int16_t a, int16_t b)
    A64: SQRSHL Hd, Hn, Hm
    
    
    Instruction Documentation: [vqrshlh_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlh_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vqrshlh_u16 (uint16_t a, int16_t b)
    A64: UQRSHL Hd, Hn, Hm
    
    
    Instruction Documentation: [vqrshlh_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlh_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshls_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vqrshls_s32 (int32_t a, int32_t b)
    A64: SQRSHL Sd, Sn, Sm
    
    
    Instruction Documentation: [vqrshls_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshls_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vqrshls_u32 (uint32_t a, int32_t b)
    A64: UQRSHL Sd, Sn, Sm
    
    
    Instruction Documentation: [vqrshls_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshls_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrnd_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vqrshrnd_n_s64 (int64_t a, const int n)
    A64: SQRSHRN Sd, Dn, #n
    
    
    Instruction Documentation: [vqrshrnd_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrnd_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vqrshrnd_n_u64 (uint64_t a, const int n)
    A64: UQRSHRN Sd, Dn, #n
    
    
    Instruction Documentation: [vqrshrnd_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnd_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrnh_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vqrshrnh_n_s16 (int16_t a, const int n)
    A64: SQRSHRN Bd, Hn, #n
    
    
    Instruction Documentation: [vqrshrnh_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrnh_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vqrshrnh_n_u16 (uint16_t a, const int n)
    A64: UQRSHRN Bd, Hn, #n
    
    
    Instruction Documentation: [vqrshrnh_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrnh_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrns_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vqrshrns_n_s32 (int32_t a, const int n)
    A64: SQRSHRN Hd, Sn, #n
    
    
    Instruction Documentation: [vqrshrns_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrns_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vqrshrns_n_u32 (uint32_t a, const int n)
    A64: UQRSHRN Hd, Sn, #n
    
    
    Instruction Documentation: [vqrshrns_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrns_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrund_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vqrshrund_n_s64 (int64_t a, const int n)
    A64: SQRSHRUN Sd, Dn, #n
    
    
    Instruction Documentation: [vqrshrund_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrund_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrunh_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vqrshrunh_n_s16 (int16_t a, const int n)
    A64: SQRSHRUN Bd, Hn, #n
    
    
    Instruction Documentation: [vqrshrunh_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrunh_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshruns_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vqrshruns_n_s32 (int32_t a, const int n)
    A64: SQRSHRUN Hd, Sn, #n
    
    
    Instruction Documentation: [vqrshruns_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshruns_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlb_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vqshlb_n_s8 (int8_t a, const int n)
    A64: SQSHL Bd, Bn, #n
    
    
    Instruction Documentation: [vqshlb_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlb_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vqshlb_n_u8 (uint8_t a, const int n)
    A64: UQSHL Bd, Bn, #n
    
    
    Instruction Documentation: [vqshlb_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlb_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vqshlb_s8 (int8_t a, int8_t b)
    A64: SQSHL Bd, Bn, Bm
    
    
    Instruction Documentation: [vqshlb_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlb_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vqshlb_u8 (uint8_t a, int8_t b)
    A64: UQSHL Bd, Bn, Bm
    
    
    Instruction Documentation: [vqshlb_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlb_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlh_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vqshlh_n_s16 (int16_t a, const int n)
    A64: SQSHL Hd, Hn, #n
    
    
    Instruction Documentation: [vqshlh_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlh_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vqshlh_n_u16 (uint16_t a, const int n)
    A64: UQSHL Hd, Hn, #n
    
    
    Instruction Documentation: [vqshlh_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlh_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vqshlh_s16 (int16_t a, int16_t b)
    A64: SQSHL Hd, Hn, Hm
    
    
    Instruction Documentation: [vqshlh_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlh_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vqshlh_u16 (uint16_t a, int16_t b)
    A64: UQSHL Hd, Hn, Hm
    
    
    Instruction Documentation: [vqshlh_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlh_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshls_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vqshls_n_s32 (int32_t a, const int n)
    A64: SQSHL Sd, Sn, #n
    
    
    Instruction Documentation: [vqshls_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshls_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vqshls_n_u32 (uint32_t a, const int n)
    A64: UQSHL Sd, Sn, #n
    
    
    Instruction Documentation: [vqshls_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshls_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vqshls_s32 (int32_t a, int32_t b)
    A64: SQSHL Sd, Sn, Sm
    
    
    Instruction Documentation: [vqshls_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshls_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vqshls_u32 (uint32_t a, int32_t b)
    A64: UQSHL Sd, Sn, Sm
    
    
    Instruction Documentation: [vqshls_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshls_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlub_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vqshlub_n_s8 (int8_t a, const int n)
    A64: SQSHLU Bd, Bn, #n
    
    
    Instruction Documentation: [vqshlub_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlub_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshluh_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vqshluh_n_s16 (int16_t a, const int n)
    A64: SQSHLU Hd, Hn, #n
    
    
    Instruction Documentation: [vqshluh_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluh_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlus_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vqshlus_n_s32 (int32_t a, const int n)
    A64: SQSHLU Sd, Sn, #n
    
    
    Instruction Documentation: [vqshlus_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlus_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrnd_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vqshrnd_n_s64 (int64_t a, const int n)
    A64: SQSHRN Sd, Dn, #n
    
    
    Instruction Documentation: [vqshrnd_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrnd_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vqshrnd_n_u64 (uint64_t a, const int n)
    A64: UQSHRN Sd, Dn, #n
    
    
    Instruction Documentation: [vqshrnd_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnd_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrnh_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vqshrnh_n_s16 (int16_t a, const int n)
    A64: SQSHRN Bd, Hn, #n
    
    
    Instruction Documentation: [vqshrnh_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrnh_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vqshrnh_n_u16 (uint16_t a, const int n)
    A64: UQSHRN Bd, Hn, #n
    
    
    Instruction Documentation: [vqshrnh_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrnh_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrns_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vqshrns_n_s32 (int32_t a, const int n)
    A64: SQSHRN Hd, Sn, #n
    
    
    Instruction Documentation: [vqshrns_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrns_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vqshrns_n_u32 (uint32_t a, const int n)
    A64: UQSHRN Hd, Sn, #n
    
    
    Instruction Documentation: [vqshrns_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrns_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrund_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vqshrund_n_s64 (int64_t a, const int n)
    A64: SQSHRUN Sd, Dn, #n
    
    
    Instruction Documentation: [vqshrund_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrund_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrunh_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vqshrunh_n_s16 (int16_t a, const int n)
    A64: SQSHRUN Bd, Hn, #n
    
    
    Instruction Documentation: [vqshrunh_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrunh_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshruns_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vqshruns_n_s32 (int32_t a, const int n)
    A64: SQSHRUN Hd, Sn, #n
    
    
    Instruction Documentation: [vqshruns_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshruns_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubb_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vqsubb_s8 (int8_t a, int8_t b)
    A64: SQSUB Bd, Bn, Bm
    
    
    Instruction Documentation: [vqsubb_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubb_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vqsubb_u8 (uint8_t a, uint8_t b)
    A64: UQSUB Bd, Bn, Bm
    
    
    Instruction Documentation: [vqsubb_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubb_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubh_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vqsubh_s16 (int16_t a, int16_t b)
    A64: SQSUB Hd, Hn, Hm
    
    
    Instruction Documentation: [vqsubh_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubh_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vqsubh_u16 (uint16_t a, uint16_t b)
    A64: UQSUB Hd, Hn, Hm
    
    
    Instruction Documentation: [vqsubh_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubh_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubs_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vqsubs_s32 (int32_t a, int32_t b)
    A64: SQSUB Sd, Sn, Sm
    
    
    Instruction Documentation: [vqsubs_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubs_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vqsubs_u32 (uint32_t a, uint32_t b)
    A64: UQSUB Sd, Sn, Sm
    
    
    Instruction Documentation: [vqsubs_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubs_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqvtbl1q_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vqvtbl1q_s8(int8x16_t t, uint8x16_t idx)
    A64: TBL Vd.16B, {Vn.16B}, Vm.16B
    
    
    Instruction Documentation: [vqvtbl1q_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqvtbl1q_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqvtbl1q_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqvtbl1q_u8(uint8x16_t t, uint8x16_t idx)
    A64: TBL Vd.16B, {Vn.16B}, Vm.16B
    
    
    Instruction Documentation: [vqvtbl1q_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqvtbl1q_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqvtbx1q_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vqvtbx1q_s8(int8x16_t r, int8x16_t t, uint8x16_t idx)
    A64: TBX Vd.16B, {Vn.16B}, Vm.16B
    
    
    Instruction Documentation: [vqvtbx1q_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqvtbx1q_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqvtbx1q_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqvtbx1q_u8(uint8x16_t r, int8x16_t t, uint8x16_t idx)
    A64: TBX Vd.16B, {Vn.16B}, Vm.16B
    
    
    Instruction Documentation: [vqvtbx1q_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqvtbx1q_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrbit_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vrbit_s8 (int8x8_t a)
    A64: RBIT Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vrbit_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrbit_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vrbit_u8 (uint8x8_t a)
    A64: RBIT Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vrbit_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbit_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrbitq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vrbitq_s8 (int8x16_t a)
    A64: RBIT Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vrbitq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrbitq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vrbitq_u8 (uint8x16_t a)
    A64: RBIT Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vrbitq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrbitq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpe_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vrecpe_f64 (float64x1_t a)
    A64: FRECPE Dd, Dn
    
    
    Instruction Documentation: [vrecpe_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpeq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vrecpeq_f64 (float64x2_t a)
    A64: FRECPE Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vrecpeq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpes_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vrecpes_f32 (float32_t a)
    A64: FRECPE Sd, Sn
    
    
    Instruction Documentation: [vrecpes_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpes_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecps_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vrecps_f64 (float64x1_t a, float64x1_t b)
    A64: FRECPS Dd, Dn, Dm
    
    
    Instruction Documentation: [vrecps_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpsq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vrecpsq_f64 (float64x2_t a, float64x2_t b)
    A64: FRECPS Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vrecpsq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpss_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vrecpss_f32 (float32_t a, float32_t b)
    A64: FRECPS Sd, Sn, Sm
    
    
    Instruction Documentation: [vrecpss_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpss_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpxd_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64_t vrecpxd_f64 (float64_t a)
    A64: FRECPX Dd, Dn
    
    
    Instruction Documentation: [vrecpxd_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxd_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpxs_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vrecpxs_f32 (float32_t a)
    A64: FRECPX Sd, Sn
    
    
    Instruction Documentation: [vrecpxs_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpxs_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndaq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vrndaq_f64 (float64x2_t a)
    A64: FRINTA Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vrndaq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndmq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vrndmq_f64 (float64x2_t a)
    A64: FRINTM Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vrndmq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndnq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vrndnq_f64 (float64x2_t a)
    A64: FRINTN Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vrndnq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndpq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vrndpq_f64 (float64x2_t a)
    A64: FRINTP Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vrndpq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vrndq_f64 (float64x2_t a)
    A64: FRINTZ Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vrndq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrte_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vrsqrte_f64 (float64x1_t a)
    A64: FRSQRTE Dd, Dn
    
    
    Instruction Documentation: [vrsqrte_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrteq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vrsqrteq_f64 (float64x2_t a)
    A64: FRSQRTE Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vrsqrteq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrtes_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vrsqrtes_f32 (float32_t a)
    A64: FRSQRTE Sd, Sn
    
    
    Instruction Documentation: [vrsqrtes_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtes_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrts_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vrsqrts_f64 (float64x1_t a, float64x1_t b)
    A64: FRSQRTS Dd, Dn, Dm
    
    
    Instruction Documentation: [vrsqrts_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrtsq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vrsqrtsq_f64 (float64x2_t a, float64x2_t b)
    A64: FRSQRTS Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vrsqrtsq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrtss_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vrsqrtss_f32 (float32_t a, float32_t b)
    A64: FRSQRTS Sd, Sn, Sm
    
    
    Instruction Documentation: [vrsqrtss_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtss_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqadd_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vsqadd_u16 (uint16x4_t a, int16x4_t b)
    A64: USQADD Vd.4H, Vn.4H
    
    
    Instruction Documentation: [vsqadd_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqadd_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vsqadd_u32 (uint32x2_t a, int32x2_t b)
    A64: USQADD Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vsqadd_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqadd_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vsqadd_u64 (uint64x1_t a, int64x1_t b)
    A64: USQADD Dd, Dn
    
    
    Instruction Documentation: [vsqadd_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqadd_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vsqadd_u8 (uint8x8_t a, int8x8_t b)
    A64: USQADD Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vsqadd_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadd_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqaddb_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vsqaddb_u8 (uint8_t a, int8_t b)
    A64: USQADD Bd, Bn
    
    
    Instruction Documentation: [vsqaddb_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddb_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqaddh_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vsqaddh_u16 (uint16_t a, int16_t b)
    A64: USQADD Hd, Hn
    
    
    Instruction Documentation: [vsqaddh_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddh_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqaddq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vsqaddq_u16 (uint16x8_t a, int16x8_t b)
    A64: USQADD Vd.8H, Vn.8H
    
    
    Instruction Documentation: [vsqaddq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqaddq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vsqaddq_u32 (uint32x4_t a, int32x4_t b)
    A64: USQADD Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vsqaddq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqaddq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vsqaddq_u64 (uint64x2_t a, int64x2_t b)
    A64: USQADD Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vsqaddq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqaddq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vsqaddq_u8 (uint8x16_t a, int8x16_t b)
    A64: USQADD Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vsqaddq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqaddq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqadds_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vsqadds_u32 (uint32_t a, int32_t b)
    A64: USQADD Sd, Sn
    
    
    Instruction Documentation: [vsqadds_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqadds_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqrt_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vsqrt_f32 (float32x2_t a)
    A64: FSQRT Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vsqrt_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqrtq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vsqrtq_f32 (float32x4_t a)
    A64: FSQRT Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vsqrtq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqrtq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vsqrtq_f64 (float64x2_t a)
    A64: FSQRT Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vsqrtq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrtq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vsubq_f64 (float64x2_t a, float64x2_t b)
    A64: FSUB Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vsubq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vtrn1_f32(float32x2_t a, float32x2_t b)
    A64: TRN1 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vtrn1_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vtrn1_s16(int16x4_t a, int16x4_t b)
    A64: TRN1 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vtrn1_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vtrn1_s32(int32x2_t a, int32x2_t b)
    A64: TRN1 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vtrn1_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vtrn1_s8(int8x8_t a, int8x8_t b)
    A64: TRN1 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vtrn1_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vtrn1_u16(uint16x4_t a, uint16x4_t b)
    A64: TRN1 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vtrn1_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vtrn1_u32(uint32x2_t a, uint32x2_t b)
    A64: TRN1 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vtrn1_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vtrn1_u8(uint8x8_t a, uint8x8_t b)
    A64: TRN1 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vtrn1_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1q_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vtrn1q_f32(float32x4_t a, float32x4_t b)
    A64: TRN1 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vtrn1q_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1q_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vtrn1q_f64(float64x2_t a, float64x2_t b)
    A64: TRN1 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vtrn1q_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1q_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vtrn1q_s16(int16x8_t a, int16x8_t b)
    A64: TRN1 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vtrn1q_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1q_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vtrn1q_s32(int32x4_t a, int32x4_t b)
    A64: TRN1 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vtrn1q_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1q_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vtrn1q_s64(int64x2_t a, int64x2_t b)
    A64: TRN1 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vtrn1q_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1q_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vtrn1q_u16(uint16x8_t a, uint16x8_t b)
    A64: TRN1 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vtrn1q_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1q_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vtrn1q_u32(uint32x4_t a, uint32x4_t b)
    A64: TRN1 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vtrn1q_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1q_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vtrn1q_u64(uint64x2_t a, uint64x2_t b)
    A64: TRN1 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vtrn1q_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn1q_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vtrn1q_u8(uint8x16_t a, uint8x16_t b)
    A64: TRN1 Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vtrn1q_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn1q_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vtrn2_f32(float32x2_t a, float32x2_t b)
    A64: TRN2 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vtrn2_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vtrn2_s16(int16x4_t a, int16x4_t b)
    A64: TRN2 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vtrn2_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vtrn2_s32(int32x2_t a, int32x2_t b)
    A64: TRN2 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vtrn2_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vtrn2_s8(int8x8_t a, int8x8_t b)
    A64: TRN2 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vtrn2_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vtrn2_u16(uint16x4_t a, uint16x4_t b)
    A64: TRN2 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vtrn2_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vtrn2_u32(uint32x2_t a, uint32x2_t b)
    A64: TRN2 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vtrn2_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vtrn2_u8(uint8x8_t a, uint8x8_t b)
    A64: TRN2 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vtrn2_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2q_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vtrn2q_f32(float32x4_t a, float32x4_t b)
    A64: TRN2 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vtrn2q_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2q_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vtrn2q_f64(float64x2_t a, float64x2_t b)
    A64: TRN2 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vtrn2q_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2q_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vtrn2q_s16(int16x8_t a, int16x8_t b)
    A64: TRN2 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vtrn2q_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2q_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vtrn2q_s32(int32x4_t a, int32x4_t b)
    A64: TRN2 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vtrn2q_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2q_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vtrn2q_s64(int64x2_t a, int64x2_t b)
    A64: TRN2 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vtrn2q_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2q_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vtrn2q_u16(uint16x8_t a, uint16x8_t b)
    A64: TRN2 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vtrn2q_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtrn2q_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vtrn2q_u8(uint8x16_t a, uint8x16_t b)
    A64: TRN2 Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vtrn2q_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtrn2q_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtst_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vtst_f64 (float64x1_t a, float64x1_t b)
    A64: CMTST Dd, Dn, Dm The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vtst_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtst_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vtst_s64 (int64x1_t a, int64x1_t b)
    A64: CMTST Dd, Dn, Dm
    
    
    Instruction Documentation: [vtst_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtst_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vtst_u64 (uint64x1_t a, uint64x1_t b)
    A64: CMTST Dd, Dn, Dm
    
    
    Instruction Documentation: [vtst_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtstq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vtstq_f64 (float64x2_t a, float64x2_t b)
    A64: CMTST Vd.2D, Vn.2D, Vm.2D The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vtstq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtstq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vtstq_s64 (int64x2_t a, int64x2_t b)
    A64: CMTST Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vtstq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtstq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vtstq_u64 (uint64x2_t a, uint64x2_t b)
    A64: CMTST Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vtstq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuqadd_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vuqadd_s16 (int16x4_t a, uint16x4_t b)
    A64: SUQADD Vd.4H, Vn.4H
    
    
    Instruction Documentation: [vuqadd_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuqadd_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vuqadd_s32 (int32x2_t a, uint32x2_t b)
    A64: SUQADD Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vuqadd_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuqadd_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vuqadd_s64 (int64x1_t a, uint64x1_t b)
    A64: SUQADD Dd, Dn
    
    
    Instruction Documentation: [vuqadd_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuqadd_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vuqadd_s8 (int8x8_t a, uint8x8_t b)
    A64: SUQADD Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vuqadd_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadd_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuqaddb_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vuqaddb_s8 (int8_t a, uint8_t b)
    A64: SUQADD Bd, Bn
    
    
    Instruction Documentation: [vuqaddb_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddb_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuqaddh_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vuqaddh_s16 (int16_t a, uint16_t b)
    A64: SUQADD Hd, Hn
    
    
    Instruction Documentation: [vuqaddh_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddh_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuqaddq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vuqaddq_s16 (int16x8_t a, uint16x8_t b)
    A64: SUQADD Vd.8H, Vn.8H
    
    
    Instruction Documentation: [vuqaddq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuqaddq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vuqaddq_s32 (int32x4_t a, uint32x4_t b)
    A64: SUQADD Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vuqaddq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuqaddq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vuqaddq_s64 (int64x2_t a, uint64x2_t b)
    A64: SUQADD Vd.2D, Vn.2D
    
    
    Instruction Documentation: [vuqaddq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuqaddq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vuqaddq_s8 (int8x16_t a, uint8x16_t b)
    A64: SUQADD Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vuqaddq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqaddq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuqadds_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vuqadds_s32 (int32_t a, uint32_t b)
    A64: SUQADD Sd, Sn
    
    
    Instruction Documentation: [vuqadds_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuqadds_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vuzp1_f32(float32x2_t a, float32x2_t b)
    A64: UZP1 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vuzp1_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vuzp1_s16(int16x4_t a, int16x4_t b)
    A64: UZP1 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vuzp1_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vuzp1_s32(int32x2_t a, int32x2_t b)
    A64: UZP1 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vuzp1_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vuzp1_s8(int8x8_t a, int8x8_t b)
    A64: UZP1 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vuzp1_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vuzp1_u16(uint16x4_t a, uint16x4_t b)
    A64: UZP1 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vuzp1_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vuzp1_u32(uint32x2_t a, uint32x2_t b)
    A64: UZP1 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vuzp1_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vuzp1_u8(uint8x8_t a, uint8x8_t b)
    A64: UZP1 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vuzp1_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1q_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vuzp1q_f32(float32x4_t a, float32x4_t b)
    A64: UZP1 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vuzp1q_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1q_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vuzp1q_f64(float64x2_t a, float64x2_t b)
    A64: UZP1 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vuzp1q_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1q_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vuzp1q_s16(int16x8_t a, int16x8_t b)
    A64: UZP1 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vuzp1q_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1q_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vuzp1q_s32(int32x4_t a, int32x4_t b)
    A64: UZP1 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vuzp1q_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1q_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vuzp1q_s64(int64x2_t a, int64x2_t b)
    A64: UZP1 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vuzp1q_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1q_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vuzp1q_u16(uint16x8_t a, uint16x8_t b)
    A64: UZP1 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vuzp1q_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1q_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vuzp1q_u32(uint32x4_t a, uint32x4_t b)
    A64: UZP1 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vuzp1q_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1q_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vuzp1q_u64(uint64x2_t a, uint64x2_t b)
    A64: UZP1 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vuzp1q_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp1q_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vuzp1q_u8(uint8x16_t a, uint8x16_t b)
    A64: UZP1 Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vuzp1q_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp1q_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vuzp2_f32(float32x2_t a, float32x2_t b)
    A64: UZP2 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vuzp2_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vuzp2_s16(int16x4_t a, int16x4_t b)
    A64: UZP2 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vuzp2_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vuzp2_s32(int32x2_t a, int32x2_t b)
    A64: UZP2 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vuzp2_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vuzp2_s8(int8x8_t a, int8x8_t b)
    A64: UZP2 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vuzp2_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vuzp2_u16(uint16x4_t a, uint16x4_t b)
    A64: UZP2 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vuzp2_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vuzp2_u32(uint32x2_t a, uint32x2_t b)
    A64: UZP2 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vuzp2_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vuzp2_u8(uint8x8_t a, uint8x8_t b)
    A64: UZP2 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vuzp2_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2q_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vuzp2q_f64(float64x2_t a, float64x2_t b)
    A64: UZP2 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vuzp2q_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2q_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vuzp2q_s16(int16x8_t a, int16x8_t b)
    A64: UZP2 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vuzp2q_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2q_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vuzp2q_s32(int32x4_t a, int32x4_t b)
    A64: UZP2 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vuzp2q_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2q_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vuzp2q_s64(int64x2_t a, int64x2_t b)
    A64: UZP2 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vuzp2q_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2q_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vuzp2q_u16(uint16x8_t a, uint16x8_t b)
    A64: UZP2 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vuzp2q_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2q_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vuzp2q_u32(uint32x4_t a, uint32x4_t b)
    A64: UZP2 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vuzp2q_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2q_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vuzp2q_u64(uint64x2_t a, uint64x2_t b)
    A64: UZP2 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vuzp2q_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vuzp2q_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vuzp2q_u8(uint8x16_t a, uint8x16_t b)
    A64: UZP2 Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vuzp2q_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vuzp2q_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vzip1_f32(float32x2_t a, float32x2_t b)
    A64: ZIP1 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vzip1_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vzip1_s16(int16x4_t a, int16x4_t b)
    A64: ZIP1 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vzip1_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vzip1_s32(int32x2_t a, int32x2_t b)
    A64: ZIP1 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vzip1_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vzip1_s8(int8x8_t a, int8x8_t b)
    A64: ZIP1 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vzip1_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vzip1_u16(uint16x4_t a, uint16x4_t b)
    A64: ZIP1 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vzip1_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vzip1_u32(uint32x2_t a, uint32x2_t b)
    A64: ZIP1 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vzip1_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vzip1_u8(uint8x8_t a, uint8x8_t b)
    A64: ZIP1 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vzip1_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1q_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vzip1q_f32(float32x4_t a, float32x4_t b)
    A64: ZIP1 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vzip1q_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1q_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vzip1q_f64(float64x2_t a, float64x2_t b)
    A64: ZIP1 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vzip1q_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1q_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vzip1q_s16(int16x8_t a, int16x8_t b)
    A64: ZIP1 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vzip1q_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1q_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vzip1q_s32(int32x4_t a, int32x4_t b)
    A64: ZIP1 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vzip1q_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1q_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vzip1q_s64(int64x2_t a, int64x2_t b)
    A64: ZIP1 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vzip1q_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1q_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vzip1q_u16(uint16x8_t a, uint16x8_t b)
    A64: ZIP1 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vzip1q_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1q_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vzip1q_u32(uint32x4_t a, uint32x4_t b)
    A64: ZIP1 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vzip1q_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1q_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vzip1q_u64(uint64x2_t a, uint64x2_t b)
    A64: ZIP1 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vzip1q_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip1q_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vzip1q_u8(uint8x16_t a, uint8x16_t b)
    A64: ZIP1 Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vzip1q_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip1q_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vzip2_f32(float32x2_t a, float32x2_t b)
    A64: ZIP2 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vzip2_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vzip2_s16(int16x4_t a, int16x4_t b)
    A64: ZIP2 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vzip2_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vzip2_s32(int32x2_t a, int32x2_t b)
    A64: ZIP2 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vzip2_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vzip2_s8(int8x8_t a, int8x8_t b)
    A64: ZIP2 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vzip2_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vzip2_u16(uint16x4_t a, uint16x4_t b)
    A64: ZIP2 Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vzip2_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vzip2_u32(uint32x2_t a, uint32x2_t b)
    A64: ZIP2 Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vzip2_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vzip2_u8(uint8x8_t a, uint8x8_t b)
    A64: ZIP2 Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vzip2_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2q_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vzip2q_f32(float32x4_t a, float32x4_t b)
    A64: ZIP2 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vzip2q_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2q_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vzip2q_f64(float64x2_t a, float64x2_t b)
    A64: ZIP2 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vzip2q_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2q_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vzip2q_s16(int16x8_t a, int16x8_t b)
    A64: ZIP2 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vzip2q_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2q_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vzip2q_s32(int32x4_t a, int32x4_t b)
    A64: ZIP2 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vzip2q_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2q_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vzip2q_s64(int64x2_t a, int64x2_t b)
    A64: ZIP2 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vzip2q_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2q_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vzip2q_u16(uint16x8_t a, uint16x8_t b)
    A64: ZIP2 Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vzip2q_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2q_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vzip2q_u32(uint32x4_t a, uint32x4_t b)
    A64: ZIP2 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vzip2q_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2q_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vzip2q_u64(uint64x2_t a, uint64x2_t b)
    A64: ZIP2 Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vzip2q_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vzip2q_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vzip2q_u8(uint8x16_t a, uint8x16_t b)
    A64: ZIP2 Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vzip2q_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vzip2q_u8)";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.Arm
{
    public partial class AdvSimdIntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("vaba_s16", (Func<object, object, object, object>)vaba_s16);
            RegisterFunction("vaba_s32", (Func<object, object, object, object>)vaba_s32);
            RegisterFunction("vaba_s8", (Func<object, object, object, object>)vaba_s8);
            RegisterFunction("vaba_u16", (Func<object, object, object, object>)vaba_u16);
            RegisterFunction("vaba_u32", (Func<object, object, object, object>)vaba_u32);
            RegisterFunction("vaba_u8", (Func<object, object, object, object>)vaba_u8);
            RegisterFunction("vabal_high_s16", (Func<object, object, object, object>)vabal_high_s16);
            RegisterFunction("vabal_high_s32", (Func<object, object, object, object>)vabal_high_s32);
            RegisterFunction("vabal_high_s8", (Func<object, object, object, object>)vabal_high_s8);
            RegisterFunction("vabal_high_u16", (Func<object, object, object, object>)vabal_high_u16);
            RegisterFunction("vabal_high_u32", (Func<object, object, object, object>)vabal_high_u32);
            RegisterFunction("vabal_high_u8", (Func<object, object, object, object>)vabal_high_u8);
            RegisterFunction("vabal_s16", (Func<object, object, object, object>)vabal_s16);
            RegisterFunction("vabal_s32", (Func<object, object, object, object>)vabal_s32);
            RegisterFunction("vabal_s8", (Func<object, object, object, object>)vabal_s8);
            RegisterFunction("vabal_u16", (Func<object, object, object, object>)vabal_u16);
            RegisterFunction("vabal_u32", (Func<object, object, object, object>)vabal_u32);
            RegisterFunction("vabal_u8", (Func<object, object, object, object>)vabal_u8);
            RegisterFunction("vabaq_s16", (Func<object, object, object, object>)vabaq_s16);
            RegisterFunction("vabaq_s32", (Func<object, object, object, object>)vabaq_s32);
            RegisterFunction("vabaq_s8", (Func<object, object, object, object>)vabaq_s8);
            RegisterFunction("vabaq_u16", (Func<object, object, object, object>)vabaq_u16);
            RegisterFunction("vabaq_u32", (Func<object, object, object, object>)vabaq_u32);
            RegisterFunction("vabaq_u8", (Func<object, object, object, object>)vabaq_u8);
            RegisterFunction("vabd_f32", (Func<object, object, object>)vabd_f32);
            RegisterFunction("vabd_s16", (Func<object, object, object>)vabd_s16);
            RegisterFunction("vabd_s32", (Func<object, object, object>)vabd_s32);
            RegisterFunction("vabd_s8", (Func<object, object, object>)vabd_s8);
            RegisterFunction("vabd_u16", (Func<object, object, object>)vabd_u16);
            RegisterFunction("vabd_u32", (Func<object, object, object>)vabd_u32);
            RegisterFunction("vabd_u8", (Func<object, object, object>)vabd_u8);
            RegisterFunction("vabdl_high_s16", (Func<object, object, object>)vabdl_high_s16);
            RegisterFunction("vabdl_high_s32", (Func<object, object, object>)vabdl_high_s32);
            RegisterFunction("vabdl_high_s8", (Func<object, object, object>)vabdl_high_s8);
            RegisterFunction("vabdl_high_u16", (Func<object, object, object>)vabdl_high_u16);
            RegisterFunction("vabdl_high_u32", (Func<object, object, object>)vabdl_high_u32);
            RegisterFunction("vabdl_high_u8", (Func<object, object, object>)vabdl_high_u8);
            RegisterFunction("vabdl_s16", (Func<object, object, object>)vabdl_s16);
            RegisterFunction("vabdl_s32", (Func<object, object, object>)vabdl_s32);
            RegisterFunction("vabdl_s8", (Func<object, object, object>)vabdl_s8);
            RegisterFunction("vabdl_u16", (Func<object, object, object>)vabdl_u16);
            RegisterFunction("vabdl_u32", (Func<object, object, object>)vabdl_u32);
            RegisterFunction("vabdl_u8", (Func<object, object, object>)vabdl_u8);
            RegisterFunction("vabdq_f32", (Func<object, object, object>)vabdq_f32);
            RegisterFunction("vabdq_s16", (Func<object, object, object>)vabdq_s16);
            RegisterFunction("vabdq_s32", (Func<object, object, object>)vabdq_s32);
            RegisterFunction("vabdq_s8", (Func<object, object, object>)vabdq_s8);
            RegisterFunction("vabdq_u16", (Func<object, object, object>)vabdq_u16);
            RegisterFunction("vabdq_u32", (Func<object, object, object>)vabdq_u32);
            RegisterFunction("vabdq_u8", (Func<object, object, object>)vabdq_u8);
            RegisterFunction("vabs_f32", (Func<object, object>)vabs_f32);
            RegisterFunction("vabs_f64", (Func<object, object>)vabs_f64);
            RegisterFunction("vabs_s16", (Func<object, object>)vabs_s16);
            RegisterFunction("vabs_s32", (Func<object, object>)vabs_s32);
            RegisterFunction("vabs_s8", (Func<object, object>)vabs_s8);
            RegisterFunction("vabsq_f32", (Func<object, object>)vabsq_f32);
            RegisterFunction("vabsq_s16", (Func<object, object>)vabsq_s16);
            RegisterFunction("vabsq_s32", (Func<object, object>)vabsq_s32);
            RegisterFunction("vabsq_s8", (Func<object, object>)vabsq_s8);
            RegisterFunction("vabss_f32", (Func<object, object>)vabss_f32);
            RegisterFunction("vadd_f32", (Func<object, object, object>)vadd_f32);
            RegisterFunction("vadd_f64", (Func<object, object, object>)vadd_f64);
            RegisterFunction("vadd_s16", (Func<object, object, object>)vadd_s16);
            RegisterFunction("vadd_s32", (Func<object, object, object>)vadd_s32);
            RegisterFunction("vadd_s64", (Func<object, object, object>)vadd_s64);
            RegisterFunction("vadd_s8", (Func<object, object, object>)vadd_s8);
            RegisterFunction("vadd_u16", (Func<object, object, object>)vadd_u16);
            RegisterFunction("vadd_u32", (Func<object, object, object>)vadd_u32);
            RegisterFunction("vadd_u64", (Func<object, object, object>)vadd_u64);
            RegisterFunction("vadd_u8", (Func<object, object, object>)vadd_u8);
            RegisterFunction("vaddhn_high_s16", (Func<object, object, object, object>)vaddhn_high_s16);
            RegisterFunction("vaddhn_high_s32", (Func<object, object, object, object>)vaddhn_high_s32);
            RegisterFunction("vaddhn_high_s64", (Func<object, object, object, object>)vaddhn_high_s64);
            RegisterFunction("vaddhn_high_u16", (Func<object, object, object, object>)vaddhn_high_u16);
            RegisterFunction("vaddhn_high_u32", (Func<object, object, object, object>)vaddhn_high_u32);
            RegisterFunction("vaddhn_high_u64", (Func<object, object, object, object>)vaddhn_high_u64);
            RegisterFunction("vaddhn_s16", (Func<object, object, object>)vaddhn_s16);
            RegisterFunction("vaddhn_s32", (Func<object, object, object>)vaddhn_s32);
            RegisterFunction("vaddhn_s64", (Func<object, object, object>)vaddhn_s64);
            RegisterFunction("vaddhn_u16", (Func<object, object, object>)vaddhn_u16);
            RegisterFunction("vaddhn_u32", (Func<object, object, object>)vaddhn_u32);
            RegisterFunction("vaddhn_u64", (Func<object, object, object>)vaddhn_u64);
            RegisterFunction("vaddl_high_s16", (Func<object, object, object>)vaddl_high_s16);
            RegisterFunction("vaddl_high_s32", (Func<object, object, object>)vaddl_high_s32);
            RegisterFunction("vaddl_high_s8", (Func<object, object, object>)vaddl_high_s8);
            RegisterFunction("vaddl_high_u16", (Func<object, object, object>)vaddl_high_u16);
            RegisterFunction("vaddl_high_u32", (Func<object, object, object>)vaddl_high_u32);
            RegisterFunction("vaddl_high_u8", (Func<object, object, object>)vaddl_high_u8);
            RegisterFunction("vaddl_s16", (Func<object, object, object>)vaddl_s16);
            RegisterFunction("vaddl_s32", (Func<object, object, object>)vaddl_s32);
            RegisterFunction("vaddl_s8", (Func<object, object, object>)vaddl_s8);
            RegisterFunction("vaddl_u16", (Func<object, object, object>)vaddl_u16);
            RegisterFunction("vaddl_u32", (Func<object, object, object>)vaddl_u32);
            RegisterFunction("vaddl_u8", (Func<object, object, object>)vaddl_u8);
            RegisterFunction("vaddq_f32", (Func<object, object, object>)vaddq_f32);
            RegisterFunction("vaddq_s16", (Func<object, object, object>)vaddq_s16);
            RegisterFunction("vaddq_s32", (Func<object, object, object>)vaddq_s32);
            RegisterFunction("vaddq_s64", (Func<object, object, object>)vaddq_s64);
            RegisterFunction("vaddq_s8", (Func<object, object, object>)vaddq_s8);
            RegisterFunction("vaddq_u16", (Func<object, object, object>)vaddq_u16);
            RegisterFunction("vaddq_u32", (Func<object, object, object>)vaddq_u32);
            RegisterFunction("vaddq_u64", (Func<object, object, object>)vaddq_u64);
            RegisterFunction("vaddq_u8", (Func<object, object, object>)vaddq_u8);
            RegisterFunction("vadds_f32", (Func<object, object, object>)vadds_f32);
            RegisterFunction("vaddw_high_s16", (Func<object, object, object>)vaddw_high_s16);
            RegisterFunction("vaddw_high_s32", (Func<object, object, object>)vaddw_high_s32);
            RegisterFunction("vaddw_high_s8", (Func<object, object, object>)vaddw_high_s8);
            RegisterFunction("vaddw_high_u16", (Func<object, object, object>)vaddw_high_u16);
            RegisterFunction("vaddw_high_u32", (Func<object, object, object>)vaddw_high_u32);
            RegisterFunction("vaddw_high_u8", (Func<object, object, object>)vaddw_high_u8);
            RegisterFunction("vaddw_s16", (Func<object, object, object>)vaddw_s16);
            RegisterFunction("vaddw_s32", (Func<object, object, object>)vaddw_s32);
            RegisterFunction("vaddw_s8", (Func<object, object, object>)vaddw_s8);
            RegisterFunction("vaddw_u16", (Func<object, object, object>)vaddw_u16);
            RegisterFunction("vaddw_u32", (Func<object, object, object>)vaddw_u32);
            RegisterFunction("vaddw_u8", (Func<object, object, object>)vaddw_u8);
            RegisterFunction("vand_f32", (Func<object, object, object>)vand_f32);
            RegisterFunction("vand_f64", (Func<object, object, object>)vand_f64);
            RegisterFunction("vand_s16", (Func<object, object, object>)vand_s16);
            RegisterFunction("vand_s32", (Func<object, object, object>)vand_s32);
            RegisterFunction("vand_s64", (Func<object, object, object>)vand_s64);
            RegisterFunction("vand_s8", (Func<object, object, object>)vand_s8);
            RegisterFunction("vand_u16", (Func<object, object, object>)vand_u16);
            RegisterFunction("vand_u32", (Func<object, object, object>)vand_u32);
            RegisterFunction("vand_u64", (Func<object, object, object>)vand_u64);
            RegisterFunction("vand_u8", (Func<object, object, object>)vand_u8);
            RegisterFunction("vandq_f32", (Func<object, object, object>)vandq_f32);
            RegisterFunction("vandq_f64", (Func<object, object, object>)vandq_f64);
            RegisterFunction("vandq_s16", (Func<object, object, object>)vandq_s16);
            RegisterFunction("vandq_s32", (Func<object, object, object>)vandq_s32);
            RegisterFunction("vandq_s64", (Func<object, object, object>)vandq_s64);
            RegisterFunction("vandq_s8", (Func<object, object, object>)vandq_s8);
            RegisterFunction("vandq_u16", (Func<object, object, object>)vandq_u16);
            RegisterFunction("vandq_u32", (Func<object, object, object>)vandq_u32);
            RegisterFunction("vandq_u64", (Func<object, object, object>)vandq_u64);
            RegisterFunction("vandq_u8", (Func<object, object, object>)vandq_u8);
            RegisterFunction("vbic_f32", (Func<object, object, object>)vbic_f32);
            RegisterFunction("vbic_f64", (Func<object, object, object>)vbic_f64);
            RegisterFunction("vbic_s16", (Func<object, object, object>)vbic_s16);
            RegisterFunction("vbic_s32", (Func<object, object, object>)vbic_s32);
            RegisterFunction("vbic_s64", (Func<object, object, object>)vbic_s64);
            RegisterFunction("vbic_s8", (Func<object, object, object>)vbic_s8);
            RegisterFunction("vbic_u16", (Func<object, object, object>)vbic_u16);
            RegisterFunction("vbic_u32", (Func<object, object, object>)vbic_u32);
            RegisterFunction("vbic_u64", (Func<object, object, object>)vbic_u64);
            RegisterFunction("vbic_u8", (Func<object, object, object>)vbic_u8);
            RegisterFunction("vbicq_f32", (Func<object, object, object>)vbicq_f32);
            RegisterFunction("vbicq_f64", (Func<object, object, object>)vbicq_f64);
            RegisterFunction("vbicq_s16", (Func<object, object, object>)vbicq_s16);
            RegisterFunction("vbicq_s32", (Func<object, object, object>)vbicq_s32);
            RegisterFunction("vbicq_s64", (Func<object, object, object>)vbicq_s64);
            RegisterFunction("vbicq_s8", (Func<object, object, object>)vbicq_s8);
            RegisterFunction("vbicq_u16", (Func<object, object, object>)vbicq_u16);
            RegisterFunction("vbicq_u32", (Func<object, object, object>)vbicq_u32);
            RegisterFunction("vbicq_u64", (Func<object, object, object>)vbicq_u64);
            RegisterFunction("vbicq_u8", (Func<object, object, object>)vbicq_u8);
            RegisterFunction("vbsl_f32", (Func<object, object, object, object>)vbsl_f32);
            RegisterFunction("vbsl_f64", (Func<object, object, object, object>)vbsl_f64);
            RegisterFunction("vbsl_s16", (Func<object, object, object, object>)vbsl_s16);
            RegisterFunction("vbsl_s32", (Func<object, object, object, object>)vbsl_s32);
            RegisterFunction("vbsl_s64", (Func<object, object, object, object>)vbsl_s64);
            RegisterFunction("vbsl_s8", (Func<object, object, object, object>)vbsl_s8);
            RegisterFunction("vbsl_u16", (Func<object, object, object, object>)vbsl_u16);
            RegisterFunction("vbsl_u32", (Func<object, object, object, object>)vbsl_u32);
            RegisterFunction("vbsl_u64", (Func<object, object, object, object>)vbsl_u64);
            RegisterFunction("vbsl_u8", (Func<object, object, object, object>)vbsl_u8);
            RegisterFunction("vbslq_f32", (Func<object, object, object, object>)vbslq_f32);
            RegisterFunction("vbslq_f64", (Func<object, object, object, object>)vbslq_f64);
            RegisterFunction("vbslq_s16", (Func<object, object, object, object>)vbslq_s16);
            RegisterFunction("vbslq_s32", (Func<object, object, object, object>)vbslq_s32);
            RegisterFunction("vbslq_s64", (Func<object, object, object, object>)vbslq_s64);
            RegisterFunction("vbslq_s8", (Func<object, object, object, object>)vbslq_s8);
            RegisterFunction("vbslq_u16", (Func<object, object, object, object>)vbslq_u16);
            RegisterFunction("vbslq_u32", (Func<object, object, object, object>)vbslq_u32);
            RegisterFunction("vbslq_u64", (Func<object, object, object, object>)vbslq_u64);
            RegisterFunction("vbslq_u8", (Func<object, object, object, object>)vbslq_u8);
            RegisterFunction("vcage_f32", (Func<object, object, object>)vcage_f32);
            RegisterFunction("vcageq_f32", (Func<object, object, object>)vcageq_f32);
            RegisterFunction("vcagt_f32", (Func<object, object, object>)vcagt_f32);
            RegisterFunction("vcagtq_f32", (Func<object, object, object>)vcagtq_f32);
            RegisterFunction("vcale_f32", (Func<object, object, object>)vcale_f32);
            RegisterFunction("vcaleq_f32", (Func<object, object, object>)vcaleq_f32);
            RegisterFunction("vcalt_f32", (Func<object, object, object>)vcalt_f32);
            RegisterFunction("vcaltq_f32", (Func<object, object, object>)vcaltq_f32);
            RegisterFunction("vceq_f32", (Func<object, object, object>)vceq_f32);
            RegisterFunction("vceq_s16", (Func<object, object, object>)vceq_s16);
            RegisterFunction("vceq_s32", (Func<object, object, object>)vceq_s32);
            RegisterFunction("vceq_s8", (Func<object, object, object>)vceq_s8);
            RegisterFunction("vceq_u16", (Func<object, object, object>)vceq_u16);
            RegisterFunction("vceq_u32", (Func<object, object, object>)vceq_u32);
            RegisterFunction("vceq_u8", (Func<object, object, object>)vceq_u8);
            RegisterFunction("vceqq_f32", (Func<object, object, object>)vceqq_f32);
            RegisterFunction("vceqq_s16", (Func<object, object, object>)vceqq_s16);
            RegisterFunction("vceqq_s32", (Func<object, object, object>)vceqq_s32);
            RegisterFunction("vceqq_s8", (Func<object, object, object>)vceqq_s8);
            RegisterFunction("vceqq_u16", (Func<object, object, object>)vceqq_u16);
            RegisterFunction("vceqq_u32", (Func<object, object, object>)vceqq_u32);
            RegisterFunction("vceqq_u8", (Func<object, object, object>)vceqq_u8);
            RegisterFunction("vcge_f32", (Func<object, object, object>)vcge_f32);
            RegisterFunction("vcge_s16", (Func<object, object, object>)vcge_s16);
            RegisterFunction("vcge_s32", (Func<object, object, object>)vcge_s32);
            RegisterFunction("vcge_s8", (Func<object, object, object>)vcge_s8);
            RegisterFunction("vcge_u16", (Func<object, object, object>)vcge_u16);
            RegisterFunction("vcge_u32", (Func<object, object, object>)vcge_u32);
            RegisterFunction("vcge_u8", (Func<object, object, object>)vcge_u8);
            RegisterFunction("vcgeq_f32", (Func<object, object, object>)vcgeq_f32);
            RegisterFunction("vcgeq_s16", (Func<object, object, object>)vcgeq_s16);
            RegisterFunction("vcgeq_s32", (Func<object, object, object>)vcgeq_s32);
            RegisterFunction("vcgeq_s8", (Func<object, object, object>)vcgeq_s8);
            RegisterFunction("vcgeq_u16", (Func<object, object, object>)vcgeq_u16);
            RegisterFunction("vcgeq_u32", (Func<object, object, object>)vcgeq_u32);
            RegisterFunction("vcgeq_u8", (Func<object, object, object>)vcgeq_u8);
            RegisterFunction("vcgt_f32", (Func<object, object, object>)vcgt_f32);
            RegisterFunction("vcgt_s16", (Func<object, object, object>)vcgt_s16);
            RegisterFunction("vcgt_s32", (Func<object, object, object>)vcgt_s32);
            RegisterFunction("vcgt_s8", (Func<object, object, object>)vcgt_s8);
            RegisterFunction("vcgt_u16", (Func<object, object, object>)vcgt_u16);
            RegisterFunction("vcgt_u32", (Func<object, object, object>)vcgt_u32);
            RegisterFunction("vcgt_u8", (Func<object, object, object>)vcgt_u8);
            RegisterFunction("vcgtq_f32", (Func<object, object, object>)vcgtq_f32);
            RegisterFunction("vcgtq_s16", (Func<object, object, object>)vcgtq_s16);
            RegisterFunction("vcgtq_s32", (Func<object, object, object>)vcgtq_s32);
            RegisterFunction("vcgtq_s8", (Func<object, object, object>)vcgtq_s8);
            RegisterFunction("vcgtq_u16", (Func<object, object, object>)vcgtq_u16);
            RegisterFunction("vcgtq_u32", (Func<object, object, object>)vcgtq_u32);
            RegisterFunction("vcgtq_u8", (Func<object, object, object>)vcgtq_u8);
            RegisterFunction("vcle_f32", (Func<object, object, object>)vcle_f32);
            RegisterFunction("vcle_s16", (Func<object, object, object>)vcle_s16);
            RegisterFunction("vcle_s32", (Func<object, object, object>)vcle_s32);
            RegisterFunction("vcle_s8", (Func<object, object, object>)vcle_s8);
            RegisterFunction("vcle_u16", (Func<object, object, object>)vcle_u16);
            RegisterFunction("vcle_u32", (Func<object, object, object>)vcle_u32);
            RegisterFunction("vcle_u8", (Func<object, object, object>)vcle_u8);
            RegisterFunction("vcleq_f32", (Func<object, object, object>)vcleq_f32);
            RegisterFunction("vcleq_s16", (Func<object, object, object>)vcleq_s16);
            RegisterFunction("vcleq_s32", (Func<object, object, object>)vcleq_s32);
            RegisterFunction("vcleq_s8", (Func<object, object, object>)vcleq_s8);
            RegisterFunction("vcleq_u16", (Func<object, object, object>)vcleq_u16);
            RegisterFunction("vcleq_u32", (Func<object, object, object>)vcleq_u32);
            RegisterFunction("vcleq_u8", (Func<object, object, object>)vcleq_u8);
            RegisterFunction("vcls_s16", (Func<object, object>)vcls_s16);
            RegisterFunction("vcls_s32", (Func<object, object>)vcls_s32);
            RegisterFunction("vcls_s8", (Func<object, object>)vcls_s8);
            RegisterFunction("vclsq_s16", (Func<object, object>)vclsq_s16);
            RegisterFunction("vclsq_s32", (Func<object, object>)vclsq_s32);
            RegisterFunction("vclsq_s8", (Func<object, object>)vclsq_s8);
            RegisterFunction("vclt_f32", (Func<object, object, object>)vclt_f32);
            RegisterFunction("vclt_s16", (Func<object, object, object>)vclt_s16);
            RegisterFunction("vclt_s32", (Func<object, object, object>)vclt_s32);
            RegisterFunction("vclt_s8", (Func<object, object, object>)vclt_s8);
            RegisterFunction("vclt_u16", (Func<object, object, object>)vclt_u16);
            RegisterFunction("vclt_u32", (Func<object, object, object>)vclt_u32);
            RegisterFunction("vclt_u8", (Func<object, object, object>)vclt_u8);
            RegisterFunction("vcltq_f32", (Func<object, object, object>)vcltq_f32);
            RegisterFunction("vcltq_s16", (Func<object, object, object>)vcltq_s16);
            RegisterFunction("vcltq_s32", (Func<object, object, object>)vcltq_s32);
            RegisterFunction("vcltq_s8", (Func<object, object, object>)vcltq_s8);
            RegisterFunction("vcltq_u16", (Func<object, object, object>)vcltq_u16);
            RegisterFunction("vcltq_u32", (Func<object, object, object>)vcltq_u32);
            RegisterFunction("vcltq_u8", (Func<object, object, object>)vcltq_u8);
            RegisterFunction("vclz_s16", (Func<object, object>)vclz_s16);
            RegisterFunction("vclz_s32", (Func<object, object>)vclz_s32);
            RegisterFunction("vclz_s8", (Func<object, object>)vclz_s8);
            RegisterFunction("vclz_u16", (Func<object, object>)vclz_u16);
            RegisterFunction("vclz_u32", (Func<object, object>)vclz_u32);
            RegisterFunction("vclz_u8", (Func<object, object>)vclz_u8);
            RegisterFunction("vclzq_s16", (Func<object, object>)vclzq_s16);
            RegisterFunction("vclzq_s32", (Func<object, object>)vclzq_s32);
            RegisterFunction("vclzq_s8", (Func<object, object>)vclzq_s8);
            RegisterFunction("vclzq_u16", (Func<object, object>)vclzq_u16);
            RegisterFunction("vclzq_u32", (Func<object, object>)vclzq_u32);
            RegisterFunction("vclzq_u8", (Func<object, object>)vclzq_u8);
            RegisterFunction("vcnt_s8", (Func<object, object>)vcnt_s8);
            RegisterFunction("vcnt_u8", (Func<object, object>)vcnt_u8);
            RegisterFunction("vcntq_s8", (Func<object, object>)vcntq_s8);
            RegisterFunction("vcntq_u8", (Func<object, object>)vcntq_u8);
            RegisterFunction("vcvt_f32_s32", (Func<object, object>)vcvt_f32_s32);
            RegisterFunction("vcvt_f32_u32", (Func<object, object>)vcvt_f32_u32);
            RegisterFunction("vcvt_s32_f32", (Func<object, object>)vcvt_s32_f32);
            RegisterFunction("vcvt_u32_f32", (Func<object, object>)vcvt_u32_f32);
            RegisterFunction("vcvta_s32_f32", (Func<object, object>)vcvta_s32_f32);
            RegisterFunction("vcvta_u32_f32", (Func<object, object>)vcvta_u32_f32);
            RegisterFunction("vcvtaq_s32_f32", (Func<object, object>)vcvtaq_s32_f32);
            RegisterFunction("vcvtaq_u32_f32", (Func<object, object>)vcvtaq_u32_f32);
            RegisterFunction("vcvtas_s32_f32", (Func<object, object>)vcvtas_s32_f32);
            RegisterFunction("vcvtas_u32_f32", (Func<object, object>)vcvtas_u32_f32);
            RegisterFunction("vcvtm_s32_f32", (Func<object, object>)vcvtm_s32_f32);
            RegisterFunction("vcvtm_u32_f32", (Func<object, object>)vcvtm_u32_f32);
            RegisterFunction("vcvtmq_s32_f32", (Func<object, object>)vcvtmq_s32_f32);
            RegisterFunction("vcvtmq_u32_f32", (Func<object, object>)vcvtmq_u32_f32);
            RegisterFunction("vcvtms_s32_f32", (Func<object, object>)vcvtms_s32_f32);
            RegisterFunction("vcvtms_u32_f32", (Func<object, object>)vcvtms_u32_f32);
            RegisterFunction("vcvtn_s32_f32", (Func<object, object>)vcvtn_s32_f32);
            RegisterFunction("vcvtn_u32_f32", (Func<object, object>)vcvtn_u32_f32);
            RegisterFunction("vcvtnq_s32_f32", (Func<object, object>)vcvtnq_s32_f32);
            RegisterFunction("vcvtnq_u32_f32", (Func<object, object>)vcvtnq_u32_f32);
            RegisterFunction("vcvtns_s32_f32", (Func<object, object>)vcvtns_s32_f32);
            RegisterFunction("vcvtns_u32_f32", (Func<object, object>)vcvtns_u32_f32);
            RegisterFunction("vcvtp_s32_f32", (Func<object, object>)vcvtp_s32_f32);
            RegisterFunction("vcvtp_u32_f32", (Func<object, object>)vcvtp_u32_f32);
            RegisterFunction("vcvtpq_s32_f32", (Func<object, object>)vcvtpq_s32_f32);
            RegisterFunction("vcvtpq_u32_f32", (Func<object, object>)vcvtpq_u32_f32);
            RegisterFunction("vcvtps_s32_f32", (Func<object, object>)vcvtps_s32_f32);
            RegisterFunction("vcvtps_u32_f32", (Func<object, object>)vcvtps_u32_f32);
            RegisterFunction("vcvtq_f32_s32", (Func<object, object>)vcvtq_f32_s32);
            RegisterFunction("vcvtq_f32_u32", (Func<object, object>)vcvtq_f32_u32);
            RegisterFunction("vcvtq_s32_f32", (Func<object, object>)vcvtq_s32_f32);
            RegisterFunction("vcvtq_u32_f32", (Func<object, object>)vcvtq_u32_f32);
            RegisterFunction("vcvts_f32_s32", (Func<object, object>)vcvts_f32_s32);
            RegisterFunction("vcvts_f32_u32", (Func<object, object>)vcvts_f32_u32);
            RegisterFunction("vcvts_s32_f32", (Func<object, object>)vcvts_s32_f32);
            RegisterFunction("vcvts_u32_f32", (Func<object, object>)vcvts_u32_f32);
            RegisterFunction("vdiv_f64", (Func<object, object, object>)vdiv_f64);
            RegisterFunction("vdivs_f32", (Func<object, object, object>)vdivs_f32);
            RegisterFunction("vdup_lane_f32", (Func<object, byte, object>)vdup_lane_f32);
            RegisterFunction("vdup_lane_s16", (Func<object, byte, object>)vdup_lane_s16);
            RegisterFunction("vdup_lane_s32", (Func<object, byte, object>)vdup_lane_s32);
            RegisterFunction("vdup_lane_s8", (Func<object, byte, object>)vdup_lane_s8);
            RegisterFunction("vdup_lane_u16", (Func<object, byte, object>)vdup_lane_u16);
            RegisterFunction("vdup_lane_u32", (Func<object, byte, object>)vdup_lane_u32);
            RegisterFunction("vdup_lane_u8", (Func<object, byte, object>)vdup_lane_u8);
            RegisterFunction("vdup_laneq_f32", (Func<object, byte, object>)vdup_laneq_f32);
            RegisterFunction("vdup_laneq_s16", (Func<object, byte, object>)vdup_laneq_s16);
            RegisterFunction("vdup_laneq_s32", (Func<object, byte, object>)vdup_laneq_s32);
            RegisterFunction("vdup_laneq_s8", (Func<object, byte, object>)vdup_laneq_s8);
            RegisterFunction("vdup_laneq_u16", (Func<object, byte, object>)vdup_laneq_u16);
            RegisterFunction("vdup_laneq_u32", (Func<object, byte, object>)vdup_laneq_u32);
            RegisterFunction("vdup_laneq_u8", (Func<object, byte, object>)vdup_laneq_u8);
            RegisterFunction("vdup_n_f32", (Func<float, object>)vdup_n_f32);
            RegisterFunction("vdup_n_s16", (Func<short, object>)vdup_n_s16);
            RegisterFunction("vdup_n_s32", (Func<int, object>)vdup_n_s32);
            RegisterFunction("vdup_n_s8", (Func<sbyte, object>)vdup_n_s8);
            RegisterFunction("vdup_n_u16", (Func<ushort, object>)vdup_n_u16);
            RegisterFunction("vdup_n_u32", (Func<uint, object>)vdup_n_u32);
            RegisterFunction("vdup_n_u8", (Func<byte, object>)vdup_n_u8);
            RegisterFunction("vdupq_lane_f32", (Func<object, byte, object>)vdupq_lane_f32);
            RegisterFunction("vdupq_lane_s16", (Func<object, byte, object>)vdupq_lane_s16);
            RegisterFunction("vdupq_lane_s32", (Func<object, byte, object>)vdupq_lane_s32);
            RegisterFunction("vdupq_lane_s8", (Func<object, byte, object>)vdupq_lane_s8);
            RegisterFunction("vdupq_lane_u16", (Func<object, byte, object>)vdupq_lane_u16);
            RegisterFunction("vdupq_lane_u32", (Func<object, byte, object>)vdupq_lane_u32);
            RegisterFunction("vdupq_lane_u8", (Func<object, byte, object>)vdupq_lane_u8);
            RegisterFunction("vdupq_n_f32", (Func<float, object>)vdupq_n_f32);
            RegisterFunction("vdupq_n_s16", (Func<short, object>)vdupq_n_s16);
            RegisterFunction("vdupq_n_s32", (Func<int, object>)vdupq_n_s32);
            RegisterFunction("vdupq_n_s8", (Func<sbyte, object>)vdupq_n_s8);
            RegisterFunction("vdupq_n_u16", (Func<ushort, object>)vdupq_n_u16);
            RegisterFunction("vdupq_n_u32", (Func<uint, object>)vdupq_n_u32);
            RegisterFunction("vdupq_n_u8", (Func<byte, object>)vdupq_n_u8);
            RegisterFunction("veor_f32", (Func<object, object, object>)veor_f32);
            RegisterFunction("veor_f64", (Func<object, object, object>)veor_f64);
            RegisterFunction("veor_s16", (Func<object, object, object>)veor_s16);
            RegisterFunction("veor_s32", (Func<object, object, object>)veor_s32);
            RegisterFunction("veor_s64", (Func<object, object, object>)veor_s64);
            RegisterFunction("veor_s8", (Func<object, object, object>)veor_s8);
            RegisterFunction("veor_u16", (Func<object, object, object>)veor_u16);
            RegisterFunction("veor_u32", (Func<object, object, object>)veor_u32);
            RegisterFunction("veor_u64", (Func<object, object, object>)veor_u64);
            RegisterFunction("veor_u8", (Func<object, object, object>)veor_u8);
            RegisterFunction("veorq_f32", (Func<object, object, object>)veorq_f32);
            RegisterFunction("veorq_f64", (Func<object, object, object>)veorq_f64);
            RegisterFunction("veorq_s16", (Func<object, object, object>)veorq_s16);
            RegisterFunction("veorq_s32", (Func<object, object, object>)veorq_s32);
            RegisterFunction("veorq_s64", (Func<object, object, object>)veorq_s64);
            RegisterFunction("veorq_s8", (Func<object, object, object>)veorq_s8);
            RegisterFunction("veorq_u16", (Func<object, object, object>)veorq_u16);
            RegisterFunction("veorq_u32", (Func<object, object, object>)veorq_u32);
            RegisterFunction("veorq_u64", (Func<object, object, object>)veorq_u64);
            RegisterFunction("veorq_u8", (Func<object, object, object>)veorq_u8);
            RegisterFunction("vext_f32", (Func<object, object, byte, object>)vext_f32);
            RegisterFunction("vext_s16", (Func<object, object, byte, object>)vext_s16);
            RegisterFunction("vext_s32", (Func<object, object, byte, object>)vext_s32);
            RegisterFunction("vext_s8", (Func<object, object, byte, object>)vext_s8);
            RegisterFunction("vextq_f32", (Func<object, object, byte, object>)vextq_f32);
            RegisterFunction("vextq_f64", (Func<object, object, byte, object>)vextq_f64);
            RegisterFunction("vextq_s16", (Func<object, object, byte, object>)vextq_s16);
            RegisterFunction("vextq_s32", (Func<object, object, byte, object>)vextq_s32);
            RegisterFunction("vextq_s64", (Func<object, object, byte, object>)vextq_s64);
            RegisterFunction("vextq_s8", (Func<object, object, byte, object>)vextq_s8);
            RegisterFunction("vfma_f32", (Func<object, object, object, object>)vfma_f32);
            RegisterFunction("vfma_f64", (Func<object, object, object, object>)vfma_f64);
            RegisterFunction("vfmaq_f32", (Func<object, object, object, object>)vfmaq_f32);
            RegisterFunction("vfmas_f32", (Func<object, object, object, object>)vfmas_f32);
            RegisterFunction("vfms_f32", (Func<object, object, object, object>)vfms_f32);
            RegisterFunction("vfms_f64", (Func<object, object, object, object>)vfms_f64);
            RegisterFunction("vfmsq_f32", (Func<object, object, object, object>)vfmsq_f32);
            RegisterFunction("vfmss_f32", (Func<object, object, object, object>)vfmss_f32);
            RegisterFunction("vfnma_f64", (Func<object, object, object, object>)vfnma_f64);
            RegisterFunction("vfnmas_f32", (Func<object, object, object, object>)vfnmas_f32);
            RegisterFunction("vfnms_f64", (Func<object, object, object, object>)vfnms_f64);
            RegisterFunction("vfnmss_f32", (Func<object, object, object, object>)vfnmss_f32);
            RegisterFunction("vget_lane_f32", (Func<object, byte, float>)vget_lane_f32);
            RegisterFunction("vget_lane_s16", (Func<object, byte, short>)vget_lane_s16);
            RegisterFunction("vget_lane_s32", (Func<object, byte, int>)vget_lane_s32);
            RegisterFunction("vget_lane_s8", (Func<object, byte, sbyte>)vget_lane_s8);
            RegisterFunction("vget_lane_u16", (Func<object, byte, ushort>)vget_lane_u16);
            RegisterFunction("vget_lane_u32", (Func<object, byte, uint>)vget_lane_u32);
            RegisterFunction("vget_lane_u8", (Func<object, byte, byte>)vget_lane_u8);
            RegisterFunction("vgetq_lane_f32", (Func<object, byte, float>)vgetq_lane_f32);
            RegisterFunction("vgetq_lane_f64", (Func<object, byte, double>)vgetq_lane_f64);
            RegisterFunction("vgetq_lane_s16", (Func<object, byte, short>)vgetq_lane_s16);
            RegisterFunction("vgetq_lane_s32", (Func<object, byte, int>)vgetq_lane_s32);
            RegisterFunction("vgetq_lane_s64", (Func<object, byte, long>)vgetq_lane_s64);
            RegisterFunction("vgetq_lane_s8", (Func<object, byte, sbyte>)vgetq_lane_s8);
            RegisterFunction("vgetq_lane_u16", (Func<object, byte, ushort>)vgetq_lane_u16);
            RegisterFunction("vgetq_lane_u32", (Func<object, byte, uint>)vgetq_lane_u32);
            RegisterFunction("vgetq_lane_u64", (Func<object, byte, ulong>)vgetq_lane_u64);
            RegisterFunction("vgetq_lane_u8", (Func<object, byte, byte>)vgetq_lane_u8);
            RegisterFunction("vhadd_s16", (Func<object, object, object>)vhadd_s16);
            RegisterFunction("vhadd_s32", (Func<object, object, object>)vhadd_s32);
            RegisterFunction("vhadd_s8", (Func<object, object, object>)vhadd_s8);
            RegisterFunction("vhadd_u16", (Func<object, object, object>)vhadd_u16);
            RegisterFunction("vhadd_u32", (Func<object, object, object>)vhadd_u32);
            RegisterFunction("vhadd_u8", (Func<object, object, object>)vhadd_u8);
            RegisterFunction("vhaddq_s16", (Func<object, object, object>)vhaddq_s16);
            RegisterFunction("vhaddq_s32", (Func<object, object, object>)vhaddq_s32);
            RegisterFunction("vhaddq_s8", (Func<object, object, object>)vhaddq_s8);
            RegisterFunction("vhaddq_u16", (Func<object, object, object>)vhaddq_u16);
            RegisterFunction("vhaddq_u32", (Func<object, object, object>)vhaddq_u32);
            RegisterFunction("vhaddq_u8", (Func<object, object, object>)vhaddq_u8);
            RegisterFunction("vhsub_s16", (Func<object, object, object>)vhsub_s16);
            RegisterFunction("vhsub_s32", (Func<object, object, object>)vhsub_s32);
            RegisterFunction("vhsub_s8", (Func<object, object, object>)vhsub_s8);
            RegisterFunction("vhsub_u16", (Func<object, object, object>)vhsub_u16);
            RegisterFunction("vhsub_u32", (Func<object, object, object>)vhsub_u32);
            RegisterFunction("vhsub_u8", (Func<object, object, object>)vhsub_u8);
            RegisterFunction("vhsubq_s16", (Func<object, object, object>)vhsubq_s16);
            RegisterFunction("vhsubq_s32", (Func<object, object, object>)vhsubq_s32);
            RegisterFunction("vhsubq_s8", (Func<object, object, object>)vhsubq_s8);
            RegisterFunction("vhsubq_u16", (Func<object, object, object>)vhsubq_u16);
            RegisterFunction("vhsubq_u32", (Func<object, object, object>)vhsubq_u32);
            RegisterFunction("vhsubq_u8", (Func<object, object, object>)vhsubq_u8);
            RegisterFunction("vld1_dup_f32", (Func<object, object>)vld1_dup_f32);
            RegisterFunction("vld1_dup_s16", (Func<object, object>)vld1_dup_s16);
            RegisterFunction("vld1_dup_s32", (Func<object, object>)vld1_dup_s32);
            RegisterFunction("vld1_dup_s8", (Func<object, object>)vld1_dup_s8);
            RegisterFunction("vld1_dup_u16", (Func<object, object>)vld1_dup_u16);
            RegisterFunction("vld1_dup_u32", (Func<object, object>)vld1_dup_u32);
            RegisterFunction("vld1_dup_u8", (Func<object, object>)vld1_dup_u8);
            RegisterFunction("vld1_f32", (Func<object, object>)vld1_f32);
            RegisterFunction("vld1_f64", (Func<object, object>)vld1_f64);
            RegisterFunction("vld1_lane_f32", (Func<object, byte, object, object>)vld1_lane_f32);
            RegisterFunction("vld1_lane_s16", (Func<object, byte, object, object>)vld1_lane_s16);
            RegisterFunction("vld1_lane_s32", (Func<object, byte, object, object>)vld1_lane_s32);
            RegisterFunction("vld1_lane_s8", (Func<object, byte, object, object>)vld1_lane_s8);
            RegisterFunction("vld1_lane_u16", (Func<object, byte, object, object>)vld1_lane_u16);
            RegisterFunction("vld1_lane_u32", (Func<object, byte, object, object>)vld1_lane_u32);
            RegisterFunction("vld1_lane_u8", (Func<object, byte, object, object>)vld1_lane_u8);
            RegisterFunction("vld1_s16", (Func<object, object>)vld1_s16);
            RegisterFunction("vld1_s32", (Func<object, object>)vld1_s32);
            RegisterFunction("vld1_s64", (Func<object, object>)vld1_s64);
            RegisterFunction("vld1_s8", (Func<object, object>)vld1_s8);
            RegisterFunction("vld1_u16", (Func<object, object>)vld1_u16);
            RegisterFunction("vld1_u32", (Func<object, object>)vld1_u32);
            RegisterFunction("vld1_u64", (Func<object, object>)vld1_u64);
            RegisterFunction("vld1_u8", (Func<object, object>)vld1_u8);
            RegisterFunction("vld1q_dup_f32", (Func<object, object>)vld1q_dup_f32);
            RegisterFunction("vld1q_dup_s16", (Func<object, object>)vld1q_dup_s16);
            RegisterFunction("vld1q_dup_s32", (Func<object, object>)vld1q_dup_s32);
            RegisterFunction("vld1q_dup_s8", (Func<object, object>)vld1q_dup_s8);
            RegisterFunction("vld1q_dup_u16", (Func<object, object>)vld1q_dup_u16);
            RegisterFunction("vld1q_dup_u32", (Func<object, object>)vld1q_dup_u32);
            RegisterFunction("vld1q_dup_u8", (Func<object, object>)vld1q_dup_u8);
            RegisterFunction("vld1q_f32", (Func<object, object>)vld1q_f32);
            RegisterFunction("vld1q_f64", (Func<object, object>)vld1q_f64);
            RegisterFunction("vld1q_lane_f32", (Func<object, byte, object, object>)vld1q_lane_f32);
            RegisterFunction("vld1q_lane_f64", (Func<object, byte, object, object>)vld1q_lane_f64);
            RegisterFunction("vld1q_lane_s16", (Func<object, byte, object, object>)vld1q_lane_s16);
            RegisterFunction("vld1q_lane_s32", (Func<object, byte, object, object>)vld1q_lane_s32);
            RegisterFunction("vld1q_lane_s64", (Func<object, byte, object, object>)vld1q_lane_s64);
            RegisterFunction("vld1q_lane_s8", (Func<object, byte, object, object>)vld1q_lane_s8);
            RegisterFunction("vld1q_lane_u16", (Func<object, byte, object, object>)vld1q_lane_u16);
            RegisterFunction("vld1q_lane_u32", (Func<object, byte, object, object>)vld1q_lane_u32);
            RegisterFunction("vld1q_lane_u64", (Func<object, byte, object, object>)vld1q_lane_u64);
            RegisterFunction("vld1q_lane_u8", (Func<object, byte, object, object>)vld1q_lane_u8);
            RegisterFunction("vld1q_s16", (Func<object, object>)vld1q_s16);
            RegisterFunction("vld1q_s32", (Func<object, object>)vld1q_s32);
            RegisterFunction("vld1q_s64", (Func<object, object>)vld1q_s64);
            RegisterFunction("vld1q_s8", (Func<object, object>)vld1q_s8);
            RegisterFunction("vld1q_u64", (Func<object, object>)vld1q_u64);
            RegisterFunction("vld1q_u8", (Func<object, object>)vld1q_u8);
            RegisterFunction("vmax_f32", (Func<object, object, object>)vmax_f32);
            RegisterFunction("vmax_s16", (Func<object, object, object>)vmax_s16);
            RegisterFunction("vmax_s32", (Func<object, object, object>)vmax_s32);
            RegisterFunction("vmax_s8", (Func<object, object, object>)vmax_s8);
            RegisterFunction("vmax_u16", (Func<object, object, object>)vmax_u16);
            RegisterFunction("vmax_u32", (Func<object, object, object>)vmax_u32);
            RegisterFunction("vmax_u8", (Func<object, object, object>)vmax_u8);
            RegisterFunction("vmaxnm_f32", (Func<object, object, object>)vmaxnm_f32);
            RegisterFunction("vmaxnm_f64", (Func<object, object, object>)vmaxnm_f64);
            RegisterFunction("vmaxnmq_f32", (Func<object, object, object>)vmaxnmq_f32);
            RegisterFunction("vmaxnms_f32", (Func<object, object, object>)vmaxnms_f32);
            RegisterFunction("vmaxq_f32", (Func<object, object, object>)vmaxq_f32);
            RegisterFunction("vmaxq_s16", (Func<object, object, object>)vmaxq_s16);
            RegisterFunction("vmaxq_s32", (Func<object, object, object>)vmaxq_s32);
            RegisterFunction("vmaxq_s8", (Func<object, object, object>)vmaxq_s8);
            RegisterFunction("vmaxq_u16", (Func<object, object, object>)vmaxq_u16);
            RegisterFunction("vmaxq_u32", (Func<object, object, object>)vmaxq_u32);
            RegisterFunction("vmaxq_u8", (Func<object, object, object>)vmaxq_u8);
            RegisterFunction("vmin_f32", (Func<object, object, object>)vmin_f32);
            RegisterFunction("vmin_s16", (Func<object, object, object>)vmin_s16);
            RegisterFunction("vmin_s32", (Func<object, object, object>)vmin_s32);
            RegisterFunction("vmin_s8", (Func<object, object, object>)vmin_s8);
            RegisterFunction("vmin_u16", (Func<object, object, object>)vmin_u16);
            RegisterFunction("vmin_u32", (Func<object, object, object>)vmin_u32);
            RegisterFunction("vmin_u8", (Func<object, object, object>)vmin_u8);
            RegisterFunction("vminnm_f32", (Func<object, object, object>)vminnm_f32);
            RegisterFunction("vminnm_f64", (Func<object, object, object>)vminnm_f64);
            RegisterFunction("vminnmq_f32", (Func<object, object, object>)vminnmq_f32);
            RegisterFunction("vminnms_f32", (Func<object, object, object>)vminnms_f32);
            RegisterFunction("vminq_f32", (Func<object, object, object>)vminq_f32);
            RegisterFunction("vminq_s16", (Func<object, object, object>)vminq_s16);
            RegisterFunction("vminq_s32", (Func<object, object, object>)vminq_s32);
            RegisterFunction("vminq_s8", (Func<object, object, object>)vminq_s8);
            RegisterFunction("vminq_u16", (Func<object, object, object>)vminq_u16);
            RegisterFunction("vminq_u32", (Func<object, object, object>)vminq_u32);
            RegisterFunction("vminq_u8", (Func<object, object, object>)vminq_u8);
            RegisterFunction("vmla_lane_s16", (Func<object, object, object, byte, object>)vmla_lane_s16);
            RegisterFunction("vmla_lane_s32", (Func<object, object, object, byte, object>)vmla_lane_s32);
            RegisterFunction("vmla_lane_u16", (Func<object, object, object, byte, object>)vmla_lane_u16);
            RegisterFunction("vmla_lane_u32", (Func<object, object, object, byte, object>)vmla_lane_u32);
            RegisterFunction("vmla_laneq_s16", (Func<object, object, object, byte, object>)vmla_laneq_s16);
            RegisterFunction("vmla_laneq_s32", (Func<object, object, object, byte, object>)vmla_laneq_s32);
            RegisterFunction("vmla_laneq_u16", (Func<object, object, object, byte, object>)vmla_laneq_u16);
            RegisterFunction("vmla_laneq_u32", (Func<object, object, object, byte, object>)vmla_laneq_u32);
            RegisterFunction("vmla_n_s16", (Func<object, object, object, object>)vmla_n_s16);
            RegisterFunction("vmla_n_s32", (Func<object, object, object, object>)vmla_n_s32);
            RegisterFunction("vmla_n_u16", (Func<object, object, object, object>)vmla_n_u16);
            RegisterFunction("vmla_n_u32", (Func<object, object, object, object>)vmla_n_u32);
            RegisterFunction("vmla_s16", (Func<object, object, object, object>)vmla_s16);
            RegisterFunction("vmla_s32", (Func<object, object, object, object>)vmla_s32);
            RegisterFunction("vmla_s8", (Func<object, object, object, object>)vmla_s8);
            RegisterFunction("vmla_u16", (Func<object, object, object, object>)vmla_u16);
            RegisterFunction("vmla_u32", (Func<object, object, object, object>)vmla_u32);
            RegisterFunction("vmla_u8", (Func<object, object, object, object>)vmla_u8);
            RegisterFunction("vmlal_high_lane_s16", (Func<object, object, object, byte, object>)vmlal_high_lane_s16);
            RegisterFunction("vmlal_high_lane_s32", (Func<object, object, object, byte, object>)vmlal_high_lane_s32);
            RegisterFunction("vmlal_high_lane_u16", (Func<object, object, object, byte, object>)vmlal_high_lane_u16);
            RegisterFunction("vmlal_high_lane_u32", (Func<object, object, object, byte, object>)vmlal_high_lane_u32);
            RegisterFunction("vmlal_high_laneq_s16", (Func<object, object, object, byte, object>)vmlal_high_laneq_s16);
            RegisterFunction("vmlal_high_laneq_s32", (Func<object, object, object, byte, object>)vmlal_high_laneq_s32);
            RegisterFunction("vmlal_high_laneq_u16", (Func<object, object, object, byte, object>)vmlal_high_laneq_u16);
            RegisterFunction("vmlal_high_laneq_u32", (Func<object, object, object, byte, object>)vmlal_high_laneq_u32);
            RegisterFunction("vmlal_high_s16", (Func<object, object, object, object>)vmlal_high_s16);
            RegisterFunction("vmlal_high_s32", (Func<object, object, object, object>)vmlal_high_s32);
            RegisterFunction("vmlal_high_s8", (Func<object, object, object, object>)vmlal_high_s8);
            RegisterFunction("vmlal_high_u16", (Func<object, object, object, object>)vmlal_high_u16);
            RegisterFunction("vmlal_high_u32", (Func<object, object, object, object>)vmlal_high_u32);
            RegisterFunction("vmlal_high_u8", (Func<object, object, object, object>)vmlal_high_u8);
            RegisterFunction("vmlal_lane_s16", (Func<object, object, object, byte, object>)vmlal_lane_s16);
            RegisterFunction("vmlal_lane_s32", (Func<object, object, object, byte, object>)vmlal_lane_s32);
            RegisterFunction("vmlal_lane_u16", (Func<object, object, object, byte, object>)vmlal_lane_u16);
            RegisterFunction("vmlal_lane_u32", (Func<object, object, object, byte, object>)vmlal_lane_u32);
            RegisterFunction("vmlal_laneq_s16", (Func<object, object, object, byte, object>)vmlal_laneq_s16);
            RegisterFunction("vmlal_laneq_s32", (Func<object, object, object, byte, object>)vmlal_laneq_s32);
            RegisterFunction("vmlal_laneq_u16", (Func<object, object, object, byte, object>)vmlal_laneq_u16);
            RegisterFunction("vmlal_laneq_u32", (Func<object, object, object, byte, object>)vmlal_laneq_u32);
            RegisterFunction("vmlal_s16", (Func<object, object, object, object>)vmlal_s16);
            RegisterFunction("vmlal_s32", (Func<object, object, object, object>)vmlal_s32);
            RegisterFunction("vmlal_s8", (Func<object, object, object, object>)vmlal_s8);
            RegisterFunction("vmlal_u16", (Func<object, object, object, object>)vmlal_u16);
            RegisterFunction("vmlal_u32", (Func<object, object, object, object>)vmlal_u32);
            RegisterFunction("vmlal_u8", (Func<object, object, object, object>)vmlal_u8);
            RegisterFunction("vmlaq_lane_s16", (Func<object, object, object, byte, object>)vmlaq_lane_s16);
            RegisterFunction("vmlaq_lane_s32", (Func<object, object, object, byte, object>)vmlaq_lane_s32);
            RegisterFunction("vmlaq_lane_u16", (Func<object, object, object, byte, object>)vmlaq_lane_u16);
            RegisterFunction("vmlaq_lane_u32", (Func<object, object, object, byte, object>)vmlaq_lane_u32);
            RegisterFunction("vmlaq_laneq_s16", (Func<object, object, object, byte, object>)vmlaq_laneq_s16);
            RegisterFunction("vmlaq_laneq_s32", (Func<object, object, object, byte, object>)vmlaq_laneq_s32);
            RegisterFunction("vmlaq_laneq_u16", (Func<object, object, object, byte, object>)vmlaq_laneq_u16);
            RegisterFunction("vmlaq_laneq_u32", (Func<object, object, object, byte, object>)vmlaq_laneq_u32);
            RegisterFunction("vmlaq_n_s16", (Func<object, object, object, object>)vmlaq_n_s16);
            RegisterFunction("vmlaq_n_s32", (Func<object, object, object, object>)vmlaq_n_s32);
            RegisterFunction("vmlaq_n_u16", (Func<object, object, object, object>)vmlaq_n_u16);
            RegisterFunction("vmlaq_n_u32", (Func<object, object, object, object>)vmlaq_n_u32);
            RegisterFunction("vmlaq_s16", (Func<object, object, object, object>)vmlaq_s16);
            RegisterFunction("vmlaq_s32", (Func<object, object, object, object>)vmlaq_s32);
            RegisterFunction("vmlaq_s8", (Func<object, object, object, object>)vmlaq_s8);
            RegisterFunction("vmlaq_u16", (Func<object, object, object, object>)vmlaq_u16);
            RegisterFunction("vmlaq_u32", (Func<object, object, object, object>)vmlaq_u32);
            RegisterFunction("vmlaq_u8", (Func<object, object, object, object>)vmlaq_u8);
            RegisterFunction("vmls_lane_s16", (Func<object, object, object, byte, object>)vmls_lane_s16);
            RegisterFunction("vmls_lane_s32", (Func<object, object, object, byte, object>)vmls_lane_s32);
            RegisterFunction("vmls_lane_u16", (Func<object, object, object, byte, object>)vmls_lane_u16);
            RegisterFunction("vmls_lane_u32", (Func<object, object, object, byte, object>)vmls_lane_u32);
            RegisterFunction("vmls_laneq_s16", (Func<object, object, object, byte, object>)vmls_laneq_s16);
            RegisterFunction("vmls_laneq_s32", (Func<object, object, object, byte, object>)vmls_laneq_s32);
            RegisterFunction("vmls_laneq_u16", (Func<object, object, object, byte, object>)vmls_laneq_u16);
            RegisterFunction("vmls_laneq_u32", (Func<object, object, object, byte, object>)vmls_laneq_u32);
            RegisterFunction("vmls_n_s16", (Func<object, object, object, object>)vmls_n_s16);
            RegisterFunction("vmls_n_s32", (Func<object, object, object, object>)vmls_n_s32);
            RegisterFunction("vmls_n_u16", (Func<object, object, object, object>)vmls_n_u16);
            RegisterFunction("vmls_n_u32", (Func<object, object, object, object>)vmls_n_u32);
            RegisterFunction("vmls_s16", (Func<object, object, object, object>)vmls_s16);
            RegisterFunction("vmls_s32", (Func<object, object, object, object>)vmls_s32);
            RegisterFunction("vmls_s8", (Func<object, object, object, object>)vmls_s8);
            RegisterFunction("vmls_u16", (Func<object, object, object, object>)vmls_u16);
            RegisterFunction("vmls_u32", (Func<object, object, object, object>)vmls_u32);
            RegisterFunction("vmls_u8", (Func<object, object, object, object>)vmls_u8);
            RegisterFunction("vmlsl_high_lane_s16", (Func<object, object, object, byte, object>)vmlsl_high_lane_s16);
            RegisterFunction("vmlsl_high_lane_s32", (Func<object, object, object, byte, object>)vmlsl_high_lane_s32);
            RegisterFunction("vmlsl_high_lane_u16", (Func<object, object, object, byte, object>)vmlsl_high_lane_u16);
            RegisterFunction("vmlsl_high_lane_u32", (Func<object, object, object, byte, object>)vmlsl_high_lane_u32);
            RegisterFunction("vmlsl_high_laneq_s16", (Func<object, object, object, byte, object>)vmlsl_high_laneq_s16);
            RegisterFunction("vmlsl_high_laneq_s32", (Func<object, object, object, byte, object>)vmlsl_high_laneq_s32);
            RegisterFunction("vmlsl_high_laneq_u16", (Func<object, object, object, byte, object>)vmlsl_high_laneq_u16);
            RegisterFunction("vmlsl_high_laneq_u32", (Func<object, object, object, byte, object>)vmlsl_high_laneq_u32);
            RegisterFunction("vmlsl_high_s16", (Func<object, object, object, object>)vmlsl_high_s16);
            RegisterFunction("vmlsl_high_s32", (Func<object, object, object, object>)vmlsl_high_s32);
            RegisterFunction("vmlsl_high_s8", (Func<object, object, object, object>)vmlsl_high_s8);
            RegisterFunction("vmlsl_high_u16", (Func<object, object, object, object>)vmlsl_high_u16);
            RegisterFunction("vmlsl_high_u32", (Func<object, object, object, object>)vmlsl_high_u32);
            RegisterFunction("vmlsl_high_u8", (Func<object, object, object, object>)vmlsl_high_u8);
            RegisterFunction("vmlsl_lane_s16", (Func<object, object, object, byte, object>)vmlsl_lane_s16);
            RegisterFunction("vmlsl_lane_s32", (Func<object, object, object, byte, object>)vmlsl_lane_s32);
            RegisterFunction("vmlsl_lane_u16", (Func<object, object, object, byte, object>)vmlsl_lane_u16);
            RegisterFunction("vmlsl_lane_u32", (Func<object, object, object, byte, object>)vmlsl_lane_u32);
            RegisterFunction("vmlsl_laneq_s16", (Func<object, object, object, byte, object>)vmlsl_laneq_s16);
            RegisterFunction("vmlsl_laneq_s32", (Func<object, object, object, byte, object>)vmlsl_laneq_s32);
            RegisterFunction("vmlsl_laneq_u16", (Func<object, object, object, byte, object>)vmlsl_laneq_u16);
            RegisterFunction("vmlsl_laneq_u32", (Func<object, object, object, byte, object>)vmlsl_laneq_u32);
            RegisterFunction("vmlsl_s16", (Func<object, object, object, object>)vmlsl_s16);
            RegisterFunction("vmlsl_s32", (Func<object, object, object, object>)vmlsl_s32);
            RegisterFunction("vmlsl_s8", (Func<object, object, object, object>)vmlsl_s8);
            RegisterFunction("vmlsl_u16", (Func<object, object, object, object>)vmlsl_u16);
            RegisterFunction("vmlsl_u32", (Func<object, object, object, object>)vmlsl_u32);
            RegisterFunction("vmlsl_u8", (Func<object, object, object, object>)vmlsl_u8);
            RegisterFunction("vmlsq_lane_s16", (Func<object, object, object, byte, object>)vmlsq_lane_s16);
            RegisterFunction("vmlsq_lane_s32", (Func<object, object, object, byte, object>)vmlsq_lane_s32);
            RegisterFunction("vmlsq_lane_u16", (Func<object, object, object, byte, object>)vmlsq_lane_u16);
            RegisterFunction("vmlsq_lane_u32", (Func<object, object, object, byte, object>)vmlsq_lane_u32);
            RegisterFunction("vmlsq_laneq_s16", (Func<object, object, object, byte, object>)vmlsq_laneq_s16);
            RegisterFunction("vmlsq_laneq_s32", (Func<object, object, object, byte, object>)vmlsq_laneq_s32);
            RegisterFunction("vmlsq_laneq_u16", (Func<object, object, object, byte, object>)vmlsq_laneq_u16);
            RegisterFunction("vmlsq_laneq_u32", (Func<object, object, object, byte, object>)vmlsq_laneq_u32);
            RegisterFunction("vmlsq_n_s16", (Func<object, object, object, object>)vmlsq_n_s16);
            RegisterFunction("vmlsq_n_s32", (Func<object, object, object, object>)vmlsq_n_s32);
            RegisterFunction("vmlsq_n_u16", (Func<object, object, object, object>)vmlsq_n_u16);
            RegisterFunction("vmlsq_n_u32", (Func<object, object, object, object>)vmlsq_n_u32);
            RegisterFunction("vmlsq_s16", (Func<object, object, object, object>)vmlsq_s16);
            RegisterFunction("vmlsq_s32", (Func<object, object, object, object>)vmlsq_s32);
            RegisterFunction("vmlsq_s8", (Func<object, object, object, object>)vmlsq_s8);
            RegisterFunction("vmlsq_u16", (Func<object, object, object, object>)vmlsq_u16);
            RegisterFunction("vmlsq_u32", (Func<object, object, object, object>)vmlsq_u32);
            RegisterFunction("vmlsq_u8", (Func<object, object, object, object>)vmlsq_u8);
            RegisterFunction("vmovl_high_s16", (Func<object, object>)vmovl_high_s16);
            RegisterFunction("vmovl_high_s32", (Func<object, object>)vmovl_high_s32);
            RegisterFunction("vmovl_high_s8", (Func<object, object>)vmovl_high_s8);
            RegisterFunction("vmovl_high_u16", (Func<object, object>)vmovl_high_u16);
            RegisterFunction("vmovl_high_u32", (Func<object, object>)vmovl_high_u32);
            RegisterFunction("vmovl_high_u8", (Func<object, object>)vmovl_high_u8);
            RegisterFunction("vmovl_s16", (Func<object, object>)vmovl_s16);
            RegisterFunction("vmovl_s32", (Func<object, object>)vmovl_s32);
            RegisterFunction("vmovl_s8", (Func<object, object>)vmovl_s8);
            RegisterFunction("vmovl_u16", (Func<object, object>)vmovl_u16);
            RegisterFunction("vmovl_u32", (Func<object, object>)vmovl_u32);
            RegisterFunction("vmovl_u8", (Func<object, object>)vmovl_u8);
            RegisterFunction("vmovn_high_s16", (Func<object, object, object>)vmovn_high_s16);
            RegisterFunction("vmovn_high_s32", (Func<object, object, object>)vmovn_high_s32);
            RegisterFunction("vmovn_high_s64", (Func<object, object, object>)vmovn_high_s64);
            RegisterFunction("vmovn_high_u16", (Func<object, object, object>)vmovn_high_u16);
            RegisterFunction("vmovn_high_u32", (Func<object, object, object>)vmovn_high_u32);
            RegisterFunction("vmovn_high_u64", (Func<object, object, object>)vmovn_high_u64);
            RegisterFunction("vmovn_s16", (Func<object, object>)vmovn_s16);
            RegisterFunction("vmovn_s32", (Func<object, object>)vmovn_s32);
            RegisterFunction("vmovn_s64", (Func<object, object>)vmovn_s64);
            RegisterFunction("vmovn_u16", (Func<object, object>)vmovn_u16);
            RegisterFunction("vmovn_u32", (Func<object, object>)vmovn_u32);
            RegisterFunction("vmovn_u64", (Func<object, object>)vmovn_u64);
            RegisterFunction("vmul_f32", (Func<object, object, object>)vmul_f32);
            RegisterFunction("vmul_f64", (Func<object, object, object>)vmul_f64);
            RegisterFunction("vmul_lane_f32", (Func<object, object, byte, object>)vmul_lane_f32);
            RegisterFunction("vmul_lane_s16", (Func<object, object, byte, object>)vmul_lane_s16);
            RegisterFunction("vmul_lane_s32", (Func<object, object, byte, object>)vmul_lane_s32);
            RegisterFunction("vmul_lane_u16", (Func<object, object, byte, object>)vmul_lane_u16);
            RegisterFunction("vmul_lane_u32", (Func<object, object, byte, object>)vmul_lane_u32);
            RegisterFunction("vmul_laneq_f32", (Func<object, object, byte, object>)vmul_laneq_f32);
            RegisterFunction("vmul_laneq_s16", (Func<object, object, byte, object>)vmul_laneq_s16);
            RegisterFunction("vmul_laneq_s32", (Func<object, object, byte, object>)vmul_laneq_s32);
            RegisterFunction("vmul_laneq_u16", (Func<object, object, byte, object>)vmul_laneq_u16);
            RegisterFunction("vmul_laneq_u32", (Func<object, object, byte, object>)vmul_laneq_u32);
            RegisterFunction("vmul_n_f32", (Func<object, object, object>)vmul_n_f32);
            RegisterFunction("vmul_n_s16", (Func<object, object, object>)vmul_n_s16);
            RegisterFunction("vmul_n_s32", (Func<object, object, object>)vmul_n_s32);
            RegisterFunction("vmul_n_u16", (Func<object, object, object>)vmul_n_u16);
            RegisterFunction("vmul_n_u32", (Func<object, object, object>)vmul_n_u32);
            RegisterFunction("vmul_p8", (Func<object, object, object>)vmul_p8);
            RegisterFunction("vmul_s16", (Func<object, object, object>)vmul_s16);
            RegisterFunction("vmul_s32", (Func<object, object, object>)vmul_s32);
            RegisterFunction("vmul_s8", (Func<object, object, object>)vmul_s8);
            RegisterFunction("vmul_u16", (Func<object, object, object>)vmul_u16);
            RegisterFunction("vmul_u32", (Func<object, object, object>)vmul_u32);
            RegisterFunction("vmul_u8", (Func<object, object, object>)vmul_u8);
            RegisterFunction("vmull_high_lane_s16", (Func<object, object, byte, object>)vmull_high_lane_s16);
            RegisterFunction("vmull_high_lane_s32", (Func<object, object, byte, object>)vmull_high_lane_s32);
            RegisterFunction("vmull_high_lane_u16", (Func<object, object, byte, object>)vmull_high_lane_u16);
            RegisterFunction("vmull_high_lane_u32", (Func<object, object, byte, object>)vmull_high_lane_u32);
            RegisterFunction("vmull_high_laneq_s16", (Func<object, object, byte, object>)vmull_high_laneq_s16);
            RegisterFunction("vmull_high_laneq_s32", (Func<object, object, byte, object>)vmull_high_laneq_s32);
            RegisterFunction("vmull_high_laneq_u16", (Func<object, object, byte, object>)vmull_high_laneq_u16);
            RegisterFunction("vmull_high_laneq_u32", (Func<object, object, byte, object>)vmull_high_laneq_u32);
            RegisterFunction("vmull_high_p8", (Func<object, object, object>)vmull_high_p8);
            RegisterFunction("vmull_high_s16", (Func<object, object, object>)vmull_high_s16);
            RegisterFunction("vmull_high_s32", (Func<object, object, object>)vmull_high_s32);
            RegisterFunction("vmull_high_s8", (Func<object, object, object>)vmull_high_s8);
            RegisterFunction("vmull_high_u16", (Func<object, object, object>)vmull_high_u16);
            RegisterFunction("vmull_high_u32", (Func<object, object, object>)vmull_high_u32);
            RegisterFunction("vmull_high_u8", (Func<object, object, object>)vmull_high_u8);
            RegisterFunction("vmull_lane_s16", (Func<object, object, byte, object>)vmull_lane_s16);
            RegisterFunction("vmull_lane_s32", (Func<object, object, byte, object>)vmull_lane_s32);
            RegisterFunction("vmull_lane_u16", (Func<object, object, byte, object>)vmull_lane_u16);
            RegisterFunction("vmull_lane_u32", (Func<object, object, byte, object>)vmull_lane_u32);
            RegisterFunction("vmull_laneq_s16", (Func<object, object, byte, object>)vmull_laneq_s16);
            RegisterFunction("vmull_laneq_s32", (Func<object, object, byte, object>)vmull_laneq_s32);
            RegisterFunction("vmull_laneq_u16", (Func<object, object, byte, object>)vmull_laneq_u16);
            RegisterFunction("vmull_laneq_u32", (Func<object, object, byte, object>)vmull_laneq_u32);
            RegisterFunction("vmull_p8", (Func<object, object, object>)vmull_p8);
            RegisterFunction("vmull_s16", (Func<object, object, object>)vmull_s16);
            RegisterFunction("vmull_s32", (Func<object, object, object>)vmull_s32);
            RegisterFunction("vmull_s8", (Func<object, object, object>)vmull_s8);
            RegisterFunction("vmull_u16", (Func<object, object, object>)vmull_u16);
            RegisterFunction("vmull_u32", (Func<object, object, object>)vmull_u32);
            RegisterFunction("vmull_u8", (Func<object, object, object>)vmull_u8);
            RegisterFunction("vmulq_f32", (Func<object, object, object>)vmulq_f32);
            RegisterFunction("vmulq_lane_f32", (Func<object, object, byte, object>)vmulq_lane_f32);
            RegisterFunction("vmulq_lane_s16", (Func<object, object, byte, object>)vmulq_lane_s16);
            RegisterFunction("vmulq_lane_s32", (Func<object, object, byte, object>)vmulq_lane_s32);
            RegisterFunction("vmulq_lane_u16", (Func<object, object, byte, object>)vmulq_lane_u16);
            RegisterFunction("vmulq_lane_u32", (Func<object, object, byte, object>)vmulq_lane_u32);
            RegisterFunction("vmulq_laneq_f32", (Func<object, object, byte, object>)vmulq_laneq_f32);
            RegisterFunction("vmulq_laneq_s16", (Func<object, object, byte, object>)vmulq_laneq_s16);
            RegisterFunction("vmulq_laneq_s32", (Func<object, object, byte, object>)vmulq_laneq_s32);
            RegisterFunction("vmulq_laneq_u16", (Func<object, object, byte, object>)vmulq_laneq_u16);
            RegisterFunction("vmulq_laneq_u32", (Func<object, object, byte, object>)vmulq_laneq_u32);
            RegisterFunction("vmulq_n_f32", (Func<object, object, object>)vmulq_n_f32);
            RegisterFunction("vmulq_n_s16", (Func<object, object, object>)vmulq_n_s16);
            RegisterFunction("vmulq_n_s32", (Func<object, object, object>)vmulq_n_s32);
            RegisterFunction("vmulq_n_u16", (Func<object, object, object>)vmulq_n_u16);
            RegisterFunction("vmulq_n_u32", (Func<object, object, object>)vmulq_n_u32);
            RegisterFunction("vmulq_p8", (Func<object, object, object>)vmulq_p8);
            RegisterFunction("vmulq_s16", (Func<object, object, object>)vmulq_s16);
            RegisterFunction("vmulq_s32", (Func<object, object, object>)vmulq_s32);
            RegisterFunction("vmulq_s8", (Func<object, object, object>)vmulq_s8);
            RegisterFunction("vmulq_u16", (Func<object, object, object>)vmulq_u16);
            RegisterFunction("vmulq_u32", (Func<object, object, object>)vmulq_u32);
            RegisterFunction("vmulq_u8", (Func<object, object, object>)vmulq_u8);
            RegisterFunction("vmuls_f32", (Func<object, object, object>)vmuls_f32);
            RegisterFunction("vmuls_lane_f32", (Func<object, object, byte, object>)vmuls_lane_f32);
            RegisterFunction("vmuls_laneq_f32", (Func<object, object, byte, object>)vmuls_laneq_f32);
            RegisterFunction("vmvn_f32", (Func<object, object>)vmvn_f32);
            RegisterFunction("vmvn_f64", (Func<object, object>)vmvn_f64);
            RegisterFunction("vmvn_s16", (Func<object, object>)vmvn_s16);
            RegisterFunction("vmvn_s32", (Func<object, object>)vmvn_s32);
            RegisterFunction("vmvn_s64", (Func<object, object>)vmvn_s64);
            RegisterFunction("vmvn_s8", (Func<object, object>)vmvn_s8);
            RegisterFunction("vmvn_u16", (Func<object, object>)vmvn_u16);
            RegisterFunction("vmvn_u32", (Func<object, object>)vmvn_u32);
            RegisterFunction("vmvn_u64", (Func<object, object>)vmvn_u64);
            RegisterFunction("vmvn_u8", (Func<object, object>)vmvn_u8);
            RegisterFunction("vmvnq_f32", (Func<object, object>)vmvnq_f32);
            RegisterFunction("vmvnq_f64", (Func<object, object>)vmvnq_f64);
            RegisterFunction("vmvnq_s16", (Func<object, object>)vmvnq_s16);
            RegisterFunction("vmvnq_s32", (Func<object, object>)vmvnq_s32);
            RegisterFunction("vmvnq_s64", (Func<object, object>)vmvnq_s64);
            RegisterFunction("vmvnq_s8", (Func<object, object>)vmvnq_s8);
            RegisterFunction("vmvnq_u16", (Func<object, object>)vmvnq_u16);
            RegisterFunction("vmvnq_u32", (Func<object, object>)vmvnq_u32);
            RegisterFunction("vmvnq_u64", (Func<object, object>)vmvnq_u64);
            RegisterFunction("vmvnq_u8", (Func<object, object>)vmvnq_u8);
            RegisterFunction("vneg_f32", (Func<object, object>)vneg_f32);
            RegisterFunction("vneg_f64", (Func<object, object>)vneg_f64);
            RegisterFunction("vneg_s16", (Func<object, object>)vneg_s16);
            RegisterFunction("vneg_s32", (Func<object, object>)vneg_s32);
            RegisterFunction("vneg_s8", (Func<object, object>)vneg_s8);
            RegisterFunction("vnegq_f32", (Func<object, object>)vnegq_f32);
            RegisterFunction("vnegq_s16", (Func<object, object>)vnegq_s16);
            RegisterFunction("vnegq_s32", (Func<object, object>)vnegq_s32);
            RegisterFunction("vnegq_s8", (Func<object, object>)vnegq_s8);
            RegisterFunction("vnegs_f32", (Func<object, object>)vnegs_f32);
            RegisterFunction("vorn_f32", (Func<object, object, object>)vorn_f32);
            RegisterFunction("vorn_f64", (Func<object, object, object>)vorn_f64);
            RegisterFunction("vorn_s16", (Func<object, object, object>)vorn_s16);
            RegisterFunction("vorn_s32", (Func<object, object, object>)vorn_s32);
            RegisterFunction("vorn_s64", (Func<object, object, object>)vorn_s64);
            RegisterFunction("vorn_s8", (Func<object, object, object>)vorn_s8);
            RegisterFunction("vorn_u16", (Func<object, object, object>)vorn_u16);
            RegisterFunction("vorn_u32", (Func<object, object, object>)vorn_u32);
            RegisterFunction("vorn_u64", (Func<object, object, object>)vorn_u64);
            RegisterFunction("vorn_u8", (Func<object, object, object>)vorn_u8);
            RegisterFunction("vornq_f32", (Func<object, object, object>)vornq_f32);
            RegisterFunction("vornq_f64", (Func<object, object, object>)vornq_f64);
            RegisterFunction("vornq_s16", (Func<object, object, object>)vornq_s16);
            RegisterFunction("vornq_s32", (Func<object, object, object>)vornq_s32);
            RegisterFunction("vornq_s64", (Func<object, object, object>)vornq_s64);
            RegisterFunction("vornq_s8", (Func<object, object, object>)vornq_s8);
            RegisterFunction("vornq_u16", (Func<object, object, object>)vornq_u16);
            RegisterFunction("vornq_u32", (Func<object, object, object>)vornq_u32);
            RegisterFunction("vornq_u64", (Func<object, object, object>)vornq_u64);
            RegisterFunction("vornq_u8", (Func<object, object, object>)vornq_u8);
            RegisterFunction("vorr_f32", (Func<object, object, object>)vorr_f32);
            RegisterFunction("vorr_f64", (Func<object, object, object>)vorr_f64);
            RegisterFunction("vorr_s16", (Func<object, object, object>)vorr_s16);
            RegisterFunction("vorr_s32", (Func<object, object, object>)vorr_s32);
            RegisterFunction("vorr_s64", (Func<object, object, object>)vorr_s64);
            RegisterFunction("vorr_s8", (Func<object, object, object>)vorr_s8);
            RegisterFunction("vorr_u16", (Func<object, object, object>)vorr_u16);
            RegisterFunction("vorr_u32", (Func<object, object, object>)vorr_u32);
            RegisterFunction("vorr_u64", (Func<object, object, object>)vorr_u64);
            RegisterFunction("vorr_u8", (Func<object, object, object>)vorr_u8);
            RegisterFunction("vorrq_f32", (Func<object, object, object>)vorrq_f32);
            RegisterFunction("vorrq_f64", (Func<object, object, object>)vorrq_f64);
            RegisterFunction("vorrq_s16", (Func<object, object, object>)vorrq_s16);
            RegisterFunction("vorrq_s32", (Func<object, object, object>)vorrq_s32);
            RegisterFunction("vorrq_s64", (Func<object, object, object>)vorrq_s64);
            RegisterFunction("vorrq_s8", (Func<object, object, object>)vorrq_s8);
            RegisterFunction("vorrq_u16", (Func<object, object, object>)vorrq_u16);
            RegisterFunction("vorrq_u32", (Func<object, object, object>)vorrq_u32);
            RegisterFunction("vorrq_u64", (Func<object, object, object>)vorrq_u64);
            RegisterFunction("vorrq_u8", (Func<object, object, object>)vorrq_u8);
            RegisterFunction("vpadal_s16", (Func<object, object, object>)vpadal_s16);
            RegisterFunction("vpadal_s32", (Func<object, object, object>)vpadal_s32);
            RegisterFunction("vpadal_s8", (Func<object, object, object>)vpadal_s8);
            RegisterFunction("vpadal_u16", (Func<object, object, object>)vpadal_u16);
            RegisterFunction("vpadal_u32", (Func<object, object, object>)vpadal_u32);
            RegisterFunction("vpadal_u8", (Func<object, object, object>)vpadal_u8);
            RegisterFunction("vpadalq_s16", (Func<object, object, object>)vpadalq_s16);
            RegisterFunction("vpadalq_s32", (Func<object, object, object>)vpadalq_s32);
            RegisterFunction("vpadalq_s8", (Func<object, object, object>)vpadalq_s8);
            RegisterFunction("vpadalq_u16", (Func<object, object, object>)vpadalq_u16);
            RegisterFunction("vpadalq_u32", (Func<object, object, object>)vpadalq_u32);
            RegisterFunction("vpadalq_u8", (Func<object, object, object>)vpadalq_u8);
            RegisterFunction("vpadd_f32", (Func<object, object, object>)vpadd_f32);
            RegisterFunction("vpadd_s16", (Func<object, object, object>)vpadd_s16);
            RegisterFunction("vpadd_s32", (Func<object, object, object>)vpadd_s32);
            RegisterFunction("vpadd_s8", (Func<object, object, object>)vpadd_s8);
            RegisterFunction("vpadd_u16", (Func<object, object, object>)vpadd_u16);
            RegisterFunction("vpadd_u32", (Func<object, object, object>)vpadd_u32);
            RegisterFunction("vpadd_u8", (Func<object, object, object>)vpadd_u8);
            RegisterFunction("vpaddl_s16", (Func<object, object>)vpaddl_s16);
            RegisterFunction("vpaddl_s32", (Func<object, object>)vpaddl_s32);
            RegisterFunction("vpaddl_s8", (Func<object, object>)vpaddl_s8);
            RegisterFunction("vpaddl_u16", (Func<object, object>)vpaddl_u16);
            RegisterFunction("vpaddl_u32", (Func<object, object>)vpaddl_u32);
            RegisterFunction("vpaddl_u8", (Func<object, object>)vpaddl_u8);
            RegisterFunction("vpaddlq_s16", (Func<object, object>)vpaddlq_s16);
            RegisterFunction("vpaddlq_s32", (Func<object, object>)vpaddlq_s32);
            RegisterFunction("vpaddlq_s8", (Func<object, object>)vpaddlq_s8);
            RegisterFunction("vpaddlq_u16", (Func<object, object>)vpaddlq_u16);
            RegisterFunction("vpaddlq_u32", (Func<object, object>)vpaddlq_u32);
            RegisterFunction("vpaddlq_u8", (Func<object, object>)vpaddlq_u8);
            RegisterFunction("vpmax_f32", (Func<object, object, object>)vpmax_f32);
            RegisterFunction("vpmax_s16", (Func<object, object, object>)vpmax_s16);
            RegisterFunction("vpmax_s32", (Func<object, object, object>)vpmax_s32);
            RegisterFunction("vpmax_s8", (Func<object, object, object>)vpmax_s8);
            RegisterFunction("vpmax_u16", (Func<object, object, object>)vpmax_u16);
            RegisterFunction("vpmax_u32", (Func<object, object, object>)vpmax_u32);
            RegisterFunction("vpmax_u8", (Func<object, object, object>)vpmax_u8);
            RegisterFunction("vpmin_f32", (Func<object, object, object>)vpmin_f32);
            RegisterFunction("vpmin_s16", (Func<object, object, object>)vpmin_s16);
            RegisterFunction("vpmin_s32", (Func<object, object, object>)vpmin_s32);
            RegisterFunction("vpmin_s8", (Func<object, object, object>)vpmin_s8);
            RegisterFunction("vpmin_u16", (Func<object, object, object>)vpmin_u16);
            RegisterFunction("vpmin_u32", (Func<object, object, object>)vpmin_u32);
            RegisterFunction("vpmin_u8", (Func<object, object, object>)vpmin_u8);
            RegisterFunction("vqabs_s16", (Func<object, object>)vqabs_s16);
            RegisterFunction("vqabs_s32", (Func<object, object>)vqabs_s32);
            RegisterFunction("vqabs_s8", (Func<object, object>)vqabs_s8);
            RegisterFunction("vqabsq_s16", (Func<object, object>)vqabsq_s16);
            RegisterFunction("vqabsq_s32", (Func<object, object>)vqabsq_s32);
            RegisterFunction("vqabsq_s8", (Func<object, object>)vqabsq_s8);
            RegisterFunction("vqadd_s16", (Func<object, object, object>)vqadd_s16);
            RegisterFunction("vqadd_s32", (Func<object, object, object>)vqadd_s32);
            RegisterFunction("vqadd_s64", (Func<object, object, object>)vqadd_s64);
            RegisterFunction("vqadd_s8", (Func<object, object, object>)vqadd_s8);
            RegisterFunction("vqadd_u16", (Func<object, object, object>)vqadd_u16);
            RegisterFunction("vqadd_u32", (Func<object, object, object>)vqadd_u32);
            RegisterFunction("vqadd_u64", (Func<object, object, object>)vqadd_u64);
            RegisterFunction("vqadd_u8", (Func<object, object, object>)vqadd_u8);
            RegisterFunction("vqaddq_s16", (Func<object, object, object>)vqaddq_s16);
            RegisterFunction("vqaddq_s32", (Func<object, object, object>)vqaddq_s32);
            RegisterFunction("vqaddq_s64", (Func<object, object, object>)vqaddq_s64);
            RegisterFunction("vqaddq_s8", (Func<object, object, object>)vqaddq_s8);
            RegisterFunction("vqaddq_u16", (Func<object, object, object>)vqaddq_u16);
            RegisterFunction("vqaddq_u32", (Func<object, object, object>)vqaddq_u32);
            RegisterFunction("vqaddq_u64", (Func<object, object, object>)vqaddq_u64);
            RegisterFunction("vqaddq_u8", (Func<object, object, object>)vqaddq_u8);
            RegisterFunction("vqneg_s16", (Func<object, object>)vqneg_s16);
            RegisterFunction("vqneg_s32", (Func<object, object>)vqneg_s32);
            RegisterFunction("vqneg_s8", (Func<object, object>)vqneg_s8);
            RegisterFunction("vqnegq_s16", (Func<object, object>)vqnegq_s16);
            RegisterFunction("vqnegq_s32", (Func<object, object>)vqnegq_s32);
            RegisterFunction("vqnegq_s8", (Func<object, object>)vqnegq_s8);
            RegisterFunction("vqrshl_s16", (Func<object, object, object>)vqrshl_s16);
            RegisterFunction("vqrshl_s32", (Func<object, object, object>)vqrshl_s32);
            RegisterFunction("vqrshl_s64", (Func<object, object, object>)vqrshl_s64);
            RegisterFunction("vqrshl_s8", (Func<object, object, object>)vqrshl_s8);
            RegisterFunction("vqrshl_u16", (Func<object, object, object>)vqrshl_u16);
            RegisterFunction("vqrshl_u32", (Func<object, object, object>)vqrshl_u32);
            RegisterFunction("vqrshl_u64", (Func<object, object, object>)vqrshl_u64);
            RegisterFunction("vqrshl_u8", (Func<object, object, object>)vqrshl_u8);
            RegisterFunction("vqrshlq_s16", (Func<object, object, object>)vqrshlq_s16);
            RegisterFunction("vqrshlq_s32", (Func<object, object, object>)vqrshlq_s32);
            RegisterFunction("vqrshlq_s64", (Func<object, object, object>)vqrshlq_s64);
            RegisterFunction("vqrshlq_s8", (Func<object, object, object>)vqrshlq_s8);
            RegisterFunction("vqrshlq_u16", (Func<object, object, object>)vqrshlq_u16);
            RegisterFunction("vqrshlq_u32", (Func<object, object, object>)vqrshlq_u32);
            RegisterFunction("vqrshlq_u64", (Func<object, object, object>)vqrshlq_u64);
            RegisterFunction("vqrshlq_u8", (Func<object, object, object>)vqrshlq_u8);
            RegisterFunction("vqrshrn_high_n_s16", (Func<object, object, byte, object>)vqrshrn_high_n_s16);
            RegisterFunction("vqrshrn_high_n_s32", (Func<object, object, byte, object>)vqrshrn_high_n_s32);
            RegisterFunction("vqrshrn_high_n_s64", (Func<object, object, byte, object>)vqrshrn_high_n_s64);
            RegisterFunction("vqrshrn_high_n_u16", (Func<object, object, byte, object>)vqrshrn_high_n_u16);
            RegisterFunction("vqrshrn_high_n_u32", (Func<object, object, byte, object>)vqrshrn_high_n_u32);
            RegisterFunction("vqrshrn_high_n_u64", (Func<object, object, byte, object>)vqrshrn_high_n_u64);
            RegisterFunction("vqrshrn_n_s16", (Func<object, byte, object>)vqrshrn_n_s16);
            RegisterFunction("vqrshrn_n_s32", (Func<object, byte, object>)vqrshrn_n_s32);
            RegisterFunction("vqrshrn_n_s64", (Func<object, byte, object>)vqrshrn_n_s64);
            RegisterFunction("vqrshrn_n_u16", (Func<object, byte, object>)vqrshrn_n_u16);
            RegisterFunction("vqrshrn_n_u32", (Func<object, byte, object>)vqrshrn_n_u32);
            RegisterFunction("vqrshrn_n_u64", (Func<object, byte, object>)vqrshrn_n_u64);
            RegisterFunction("vqrshrun_high_n_s16", (Func<object, object, byte, object>)vqrshrun_high_n_s16);
            RegisterFunction("vqrshrun_high_n_s32", (Func<object, object, byte, object>)vqrshrun_high_n_s32);
            RegisterFunction("vqrshrun_high_n_s64", (Func<object, object, byte, object>)vqrshrun_high_n_s64);
            RegisterFunction("vqrshrun_n_s16", (Func<object, byte, object>)vqrshrun_n_s16);
            RegisterFunction("vqrshrun_n_s32", (Func<object, byte, object>)vqrshrun_n_s32);
            RegisterFunction("vqrshrun_n_s64", (Func<object, byte, object>)vqrshrun_n_s64);
            RegisterFunction("vqshl_n_s16", (Func<object, byte, object>)vqshl_n_s16);
            RegisterFunction("vqshl_n_s32", (Func<object, byte, object>)vqshl_n_s32);
            RegisterFunction("vqshl_n_s64", (Func<object, byte, object>)vqshl_n_s64);
            RegisterFunction("vqshl_n_s8", (Func<object, byte, object>)vqshl_n_s8);
            RegisterFunction("vqshl_n_u16", (Func<object, byte, object>)vqshl_n_u16);
            RegisterFunction("vqshl_n_u32", (Func<object, byte, object>)vqshl_n_u32);
            RegisterFunction("vqshl_n_u64", (Func<object, byte, object>)vqshl_n_u64);
            RegisterFunction("vqshl_n_u8", (Func<object, byte, object>)vqshl_n_u8);
            RegisterFunction("vqshl_s16", (Func<object, object, object>)vqshl_s16);
            RegisterFunction("vqshl_s32", (Func<object, object, object>)vqshl_s32);
            RegisterFunction("vqshl_s64", (Func<object, object, object>)vqshl_s64);
            RegisterFunction("vqshl_s8", (Func<object, object, object>)vqshl_s8);
            RegisterFunction("vqshl_u16", (Func<object, object, object>)vqshl_u16);
            RegisterFunction("vqshl_u32", (Func<object, object, object>)vqshl_u32);
            RegisterFunction("vqshl_u64", (Func<object, object, object>)vqshl_u64);
            RegisterFunction("vqshl_u8", (Func<object, object, object>)vqshl_u8);
            RegisterFunction("vqshlq_n_s16", (Func<object, byte, object>)vqshlq_n_s16);
            RegisterFunction("vqshlq_n_s32", (Func<object, byte, object>)vqshlq_n_s32);
            RegisterFunction("vqshlq_n_s64", (Func<object, byte, object>)vqshlq_n_s64);
            RegisterFunction("vqshlq_n_s8", (Func<object, byte, object>)vqshlq_n_s8);
            RegisterFunction("vqshlq_n_u16", (Func<object, byte, object>)vqshlq_n_u16);
            RegisterFunction("vqshlq_n_u32", (Func<object, byte, object>)vqshlq_n_u32);
            RegisterFunction("vqshlq_n_u64", (Func<object, byte, object>)vqshlq_n_u64);
            RegisterFunction("vqshlq_n_u8", (Func<object, byte, object>)vqshlq_n_u8);
            RegisterFunction("vqshlq_s16", (Func<object, object, object>)vqshlq_s16);
            RegisterFunction("vqshlq_s32", (Func<object, object, object>)vqshlq_s32);
            RegisterFunction("vqshlq_s64", (Func<object, object, object>)vqshlq_s64);
            RegisterFunction("vqshlq_s8", (Func<object, object, object>)vqshlq_s8);
            RegisterFunction("vqshlq_u16", (Func<object, object, object>)vqshlq_u16);
            RegisterFunction("vqshlq_u32", (Func<object, object, object>)vqshlq_u32);
            RegisterFunction("vqshlq_u64", (Func<object, object, object>)vqshlq_u64);
            RegisterFunction("vqshlq_u8", (Func<object, object, object>)vqshlq_u8);
            RegisterFunction("vqshlu_n_s16", (Func<object, byte, object>)vqshlu_n_s16);
            RegisterFunction("vqshlu_n_s32", (Func<object, byte, object>)vqshlu_n_s32);
            RegisterFunction("vqshlu_n_s64", (Func<object, byte, object>)vqshlu_n_s64);
            RegisterFunction("vqshlu_n_s8", (Func<object, byte, object>)vqshlu_n_s8);
            RegisterFunction("vqshluq_n_s16", (Func<object, byte, object>)vqshluq_n_s16);
            RegisterFunction("vqshluq_n_s32", (Func<object, byte, object>)vqshluq_n_s32);
            RegisterFunction("vqshluq_n_s64", (Func<object, byte, object>)vqshluq_n_s64);
            RegisterFunction("vqshluq_n_s8", (Func<object, byte, object>)vqshluq_n_s8);
            RegisterFunction("vqshrn_high_n_s16", (Func<object, object, byte, object>)vqshrn_high_n_s16);
            RegisterFunction("vqshrn_high_n_s32", (Func<object, object, byte, object>)vqshrn_high_n_s32);
            RegisterFunction("vqshrn_high_n_s64", (Func<object, object, byte, object>)vqshrn_high_n_s64);
            RegisterFunction("vqshrn_high_n_u16", (Func<object, object, byte, object>)vqshrn_high_n_u16);
            RegisterFunction("vqshrn_high_n_u32", (Func<object, object, byte, object>)vqshrn_high_n_u32);
            RegisterFunction("vqshrn_high_n_u64", (Func<object, object, byte, object>)vqshrn_high_n_u64);
            RegisterFunction("vqshrn_n_s16", (Func<object, byte, object>)vqshrn_n_s16);
            RegisterFunction("vqshrn_n_s32", (Func<object, byte, object>)vqshrn_n_s32);
            RegisterFunction("vqshrn_n_s64", (Func<object, byte, object>)vqshrn_n_s64);
            RegisterFunction("vqshrn_n_u16", (Func<object, byte, object>)vqshrn_n_u16);
            RegisterFunction("vqshrn_n_u32", (Func<object, byte, object>)vqshrn_n_u32);
            RegisterFunction("vqshrn_n_u64", (Func<object, byte, object>)vqshrn_n_u64);
            RegisterFunction("vqshrun_high_n_s16", (Func<object, object, byte, object>)vqshrun_high_n_s16);
            RegisterFunction("vqshrun_high_n_s32", (Func<object, object, byte, object>)vqshrun_high_n_s32);
            RegisterFunction("vqshrun_high_n_s64", (Func<object, object, byte, object>)vqshrun_high_n_s64);
            RegisterFunction("vqshrun_n_s16", (Func<object, byte, object>)vqshrun_n_s16);
            RegisterFunction("vqshrun_n_s32", (Func<object, byte, object>)vqshrun_n_s32);
            RegisterFunction("vqshrun_n_s64", (Func<object, byte, object>)vqshrun_n_s64);
            RegisterFunction("vqsub_s16", (Func<object, object, object>)vqsub_s16);
            RegisterFunction("vqsub_s32", (Func<object, object, object>)vqsub_s32);
            RegisterFunction("vqsub_s64", (Func<object, object, object>)vqsub_s64);
            RegisterFunction("vqsub_s8", (Func<object, object, object>)vqsub_s8);
            RegisterFunction("vqsub_u16", (Func<object, object, object>)vqsub_u16);
            RegisterFunction("vqsub_u32", (Func<object, object, object>)vqsub_u32);
            RegisterFunction("vqsub_u64", (Func<object, object, object>)vqsub_u64);
            RegisterFunction("vqsub_u8", (Func<object, object, object>)vqsub_u8);
            RegisterFunction("vqsubq_s16", (Func<object, object, object>)vqsubq_s16);
            RegisterFunction("vqsubq_s32", (Func<object, object, object>)vqsubq_s32);
            RegisterFunction("vqsubq_s64", (Func<object, object, object>)vqsubq_s64);
            RegisterFunction("vqsubq_s8", (Func<object, object, object>)vqsubq_s8);
            RegisterFunction("vqsubq_u16", (Func<object, object, object>)vqsubq_u16);
            RegisterFunction("vqsubq_u32", (Func<object, object, object>)vqsubq_u32);
            RegisterFunction("vqsubq_u64", (Func<object, object, object>)vqsubq_u64);
            RegisterFunction("vqsubq_u8", (Func<object, object, object>)vqsubq_u8);
            RegisterFunction("vqvtbl1_s8", (Func<object, object, object>)vqvtbl1_s8);
            RegisterFunction("vqvtbl1_u8", (Func<object, object, object>)vqvtbl1_u8);
            RegisterFunction("vqvtbx1_s8", (Func<object, object, object, object>)vqvtbx1_s8);
            RegisterFunction("vqvtbx1_u8", (Func<object, object, object, object>)vqvtbx1_u8);
            RegisterFunction("vraddhn_high_s16", (Func<object, object, object, object>)vraddhn_high_s16);
            RegisterFunction("vraddhn_high_s32", (Func<object, object, object, object>)vraddhn_high_s32);
            RegisterFunction("vraddhn_high_s64", (Func<object, object, object, object>)vraddhn_high_s64);
            RegisterFunction("vraddhn_high_u16", (Func<object, object, object, object>)vraddhn_high_u16);
            RegisterFunction("vraddhn_high_u32", (Func<object, object, object, object>)vraddhn_high_u32);
            RegisterFunction("vraddhn_high_u64", (Func<object, object, object, object>)vraddhn_high_u64);
            RegisterFunction("vraddhn_s16", (Func<object, object, object>)vraddhn_s16);
            RegisterFunction("vraddhn_s32", (Func<object, object, object>)vraddhn_s32);
            RegisterFunction("vraddhn_s64", (Func<object, object, object>)vraddhn_s64);
            RegisterFunction("vraddhn_u16", (Func<object, object, object>)vraddhn_u16);
            RegisterFunction("vraddhn_u32", (Func<object, object, object>)vraddhn_u32);
            RegisterFunction("vraddhn_u64", (Func<object, object, object>)vraddhn_u64);
            RegisterFunction("vrecpe_f32", (Func<object, object>)vrecpe_f32);
            RegisterFunction("vrecpe_u32", (Func<object, object>)vrecpe_u32);
            RegisterFunction("vrecpeq_f32", (Func<object, object>)vrecpeq_f32);
            RegisterFunction("vrecpeq_u32", (Func<object, object>)vrecpeq_u32);
            RegisterFunction("vrecps_f32", (Func<object, object, object>)vrecps_f32);
            RegisterFunction("vrecpsq_f32", (Func<object, object, object>)vrecpsq_f32);
            RegisterFunction("vrhadd_s16", (Func<object, object, object>)vrhadd_s16);
            RegisterFunction("vrhadd_s32", (Func<object, object, object>)vrhadd_s32);
            RegisterFunction("vrhadd_s8", (Func<object, object, object>)vrhadd_s8);
            RegisterFunction("vrhadd_u16", (Func<object, object, object>)vrhadd_u16);
            RegisterFunction("vrhadd_u32", (Func<object, object, object>)vrhadd_u32);
            RegisterFunction("vrhadd_u8", (Func<object, object, object>)vrhadd_u8);
            RegisterFunction("vrhaddq_s16", (Func<object, object, object>)vrhaddq_s16);
            RegisterFunction("vrhaddq_s32", (Func<object, object, object>)vrhaddq_s32);
            RegisterFunction("vrhaddq_s8", (Func<object, object, object>)vrhaddq_s8);
            RegisterFunction("vrhaddq_u16", (Func<object, object, object>)vrhaddq_u16);
            RegisterFunction("vrhaddq_u32", (Func<object, object, object>)vrhaddq_u32);
            RegisterFunction("vrhaddq_u8", (Func<object, object, object>)vrhaddq_u8);
            RegisterFunction("vrnd_f32", (Func<object, object>)vrnd_f32);
            RegisterFunction("vrnd_f64", (Func<object, object>)vrnd_f64);
            RegisterFunction("vrnda_f32", (Func<object, object>)vrnda_f32);
            RegisterFunction("vrnda_f64", (Func<object, object>)vrnda_f64);
            RegisterFunction("vrndaq_f32", (Func<object, object>)vrndaq_f32);
            RegisterFunction("vrndas_f32", (Func<object, object>)vrndas_f32);
            RegisterFunction("vrndm_f32", (Func<object, object>)vrndm_f32);
            RegisterFunction("vrndm_f64", (Func<object, object>)vrndm_f64);
            RegisterFunction("vrndmq_f32", (Func<object, object>)vrndmq_f32);
            RegisterFunction("vrndms_f32", (Func<object, object>)vrndms_f32);
            RegisterFunction("vrndn_f32", (Func<object, object>)vrndn_f32);
            RegisterFunction("vrndn_f64", (Func<object, object>)vrndn_f64);
            RegisterFunction("vrndnq_f32", (Func<object, object>)vrndnq_f32);
            RegisterFunction("vrndns_f32", (Func<object, object>)vrndns_f32);
            RegisterFunction("vrndp_f32", (Func<object, object>)vrndp_f32);
            RegisterFunction("vrndp_f64", (Func<object, object>)vrndp_f64);
            RegisterFunction("vrndpq_f32", (Func<object, object>)vrndpq_f32);
            RegisterFunction("vrndps_f32", (Func<object, object>)vrndps_f32);
            RegisterFunction("vrndq_f32", (Func<object, object>)vrndq_f32);
            RegisterFunction("vrnds_f32", (Func<object, object>)vrnds_f32);
            RegisterFunction("vrshl_s16", (Func<object, object, object>)vrshl_s16);
            RegisterFunction("vrshl_s32", (Func<object, object, object>)vrshl_s32);
            RegisterFunction("vrshl_s64", (Func<object, object, object>)vrshl_s64);
            RegisterFunction("vrshl_s8", (Func<object, object, object>)vrshl_s8);
            RegisterFunction("vrshl_u16", (Func<object, object, object>)vrshl_u16);
            RegisterFunction("vrshl_u32", (Func<object, object, object>)vrshl_u32);
            RegisterFunction("vrshl_u64", (Func<object, object, object>)vrshl_u64);
            RegisterFunction("vrshl_u8", (Func<object, object, object>)vrshl_u8);
            RegisterFunction("vrshlq_s16", (Func<object, object, object>)vrshlq_s16);
            RegisterFunction("vrshlq_s32", (Func<object, object, object>)vrshlq_s32);
            RegisterFunction("vrshlq_s64", (Func<object, object, object>)vrshlq_s64);
            RegisterFunction("vrshlq_s8", (Func<object, object, object>)vrshlq_s8);
            RegisterFunction("vrshlq_u16", (Func<object, object, object>)vrshlq_u16);
            RegisterFunction("vrshlq_u32", (Func<object, object, object>)vrshlq_u32);
            RegisterFunction("vrshlq_u64", (Func<object, object, object>)vrshlq_u64);
            RegisterFunction("vrshlq_u8", (Func<object, object, object>)vrshlq_u8);
            RegisterFunction("vrshr_n_s16", (Func<object, byte, object>)vrshr_n_s16);
            RegisterFunction("vrshr_n_s32", (Func<object, byte, object>)vrshr_n_s32);
            RegisterFunction("vrshr_n_s64", (Func<object, byte, object>)vrshr_n_s64);
            RegisterFunction("vrshr_n_s8", (Func<object, byte, object>)vrshr_n_s8);
            RegisterFunction("vrshr_n_u16", (Func<object, byte, object>)vrshr_n_u16);
            RegisterFunction("vrshr_n_u32", (Func<object, byte, object>)vrshr_n_u32);
            RegisterFunction("vrshr_n_u64", (Func<object, byte, object>)vrshr_n_u64);
            RegisterFunction("vrshr_n_u8", (Func<object, byte, object>)vrshr_n_u8);
            RegisterFunction("vrshrn_high_n_s16", (Func<object, object, byte, object>)vrshrn_high_n_s16);
            RegisterFunction("vrshrn_high_n_s32", (Func<object, object, byte, object>)vrshrn_high_n_s32);
            RegisterFunction("vrshrn_high_n_s64", (Func<object, object, byte, object>)vrshrn_high_n_s64);
            RegisterFunction("vrshrn_high_n_u16", (Func<object, object, byte, object>)vrshrn_high_n_u16);
            RegisterFunction("vrshrn_high_n_u32", (Func<object, object, byte, object>)vrshrn_high_n_u32);
            RegisterFunction("vrshrn_high_n_u64", (Func<object, object, byte, object>)vrshrn_high_n_u64);
            RegisterFunction("vrshrn_n_s16", (Func<object, byte, object>)vrshrn_n_s16);
            RegisterFunction("vrshrn_n_s32", (Func<object, byte, object>)vrshrn_n_s32);
            RegisterFunction("vrshrn_n_s64", (Func<object, byte, object>)vrshrn_n_s64);
            RegisterFunction("vrshrn_n_u16", (Func<object, byte, object>)vrshrn_n_u16);
            RegisterFunction("vrshrn_n_u32", (Func<object, byte, object>)vrshrn_n_u32);
            RegisterFunction("vrshrn_n_u64", (Func<object, byte, object>)vrshrn_n_u64);
            RegisterFunction("vrshrq_n_s16", (Func<object, byte, object>)vrshrq_n_s16);
            RegisterFunction("vrshrq_n_s32", (Func<object, byte, object>)vrshrq_n_s32);
            RegisterFunction("vrshrq_n_s64", (Func<object, byte, object>)vrshrq_n_s64);
            RegisterFunction("vrshrq_n_s8", (Func<object, byte, object>)vrshrq_n_s8);
            RegisterFunction("vrshrq_n_u16", (Func<object, byte, object>)vrshrq_n_u16);
            RegisterFunction("vrshrq_n_u32", (Func<object, byte, object>)vrshrq_n_u32);
            RegisterFunction("vrshrq_n_u64", (Func<object, byte, object>)vrshrq_n_u64);
            RegisterFunction("vrshrq_n_u8", (Func<object, byte, object>)vrshrq_n_u8);
            RegisterFunction("vrsqrte_f32", (Func<object, object>)vrsqrte_f32);
            RegisterFunction("vrsqrte_u32", (Func<object, object>)vrsqrte_u32);
            RegisterFunction("vrsqrteq_f32", (Func<object, object>)vrsqrteq_f32);
            RegisterFunction("vrsqrteq_u32", (Func<object, object>)vrsqrteq_u32);
            RegisterFunction("vrsqrts_f32", (Func<object, object, object>)vrsqrts_f32);
            RegisterFunction("vrsqrtsq_f32", (Func<object, object, object>)vrsqrtsq_f32);
            RegisterFunction("vrsra_n_s16", (Func<object, object, byte, object>)vrsra_n_s16);
            RegisterFunction("vrsra_n_s32", (Func<object, object, byte, object>)vrsra_n_s32);
            RegisterFunction("vrsra_n_s64", (Func<object, object, byte, object>)vrsra_n_s64);
            RegisterFunction("vrsra_n_s8", (Func<object, object, byte, object>)vrsra_n_s8);
            RegisterFunction("vrsra_n_u16", (Func<object, object, byte, object>)vrsra_n_u16);
            RegisterFunction("vrsra_n_u32", (Func<object, object, byte, object>)vrsra_n_u32);
            RegisterFunction("vrsra_n_u64", (Func<object, object, byte, object>)vrsra_n_u64);
            RegisterFunction("vrsra_n_u8", (Func<object, object, byte, object>)vrsra_n_u8);
            RegisterFunction("vrsraq_n_s16", (Func<object, object, byte, object>)vrsraq_n_s16);
            RegisterFunction("vrsraq_n_s32", (Func<object, object, byte, object>)vrsraq_n_s32);
            RegisterFunction("vrsraq_n_s64", (Func<object, object, byte, object>)vrsraq_n_s64);
            RegisterFunction("vrsraq_n_s8", (Func<object, object, byte, object>)vrsraq_n_s8);
            RegisterFunction("vrsraq_n_u16", (Func<object, object, byte, object>)vrsraq_n_u16);
            RegisterFunction("vrsraq_n_u32", (Func<object, object, byte, object>)vrsraq_n_u32);
            RegisterFunction("vrsraq_n_u64", (Func<object, object, byte, object>)vrsraq_n_u64);
            RegisterFunction("vrsraq_n_u8", (Func<object, object, byte, object>)vrsraq_n_u8);
            RegisterFunction("vrsubhn_high_s16", (Func<object, object, object, object>)vrsubhn_high_s16);
            RegisterFunction("vrsubhn_high_s32", (Func<object, object, object, object>)vrsubhn_high_s32);
            RegisterFunction("vrsubhn_high_s64", (Func<object, object, object, object>)vrsubhn_high_s64);
            RegisterFunction("vrsubhn_high_u16", (Func<object, object, object, object>)vrsubhn_high_u16);
            RegisterFunction("vrsubhn_high_u32", (Func<object, object, object, object>)vrsubhn_high_u32);
            RegisterFunction("vrsubhn_high_u64", (Func<object, object, object, object>)vrsubhn_high_u64);
            RegisterFunction("vrsubhn_s16", (Func<object, object, object>)vrsubhn_s16);
            RegisterFunction("vrsubhn_s32", (Func<object, object, object>)vrsubhn_s32);
            RegisterFunction("vrsubhn_s64", (Func<object, object, object>)vrsubhn_s64);
            RegisterFunction("vrsubhn_u16", (Func<object, object, object>)vrsubhn_u16);
            RegisterFunction("vrsubhn_u32", (Func<object, object, object>)vrsubhn_u32);
            RegisterFunction("vrsubhn_u64", (Func<object, object, object>)vrsubhn_u64);
            RegisterFunction("vset_lane_f32", (Func<object, byte, float, object>)vset_lane_f32);
            RegisterFunction("vset_lane_s16", (Func<object, byte, short, object>)vset_lane_s16);
            RegisterFunction("vset_lane_s32", (Func<object, byte, int, object>)vset_lane_s32);
            RegisterFunction("vset_lane_s8", (Func<object, byte, sbyte, object>)vset_lane_s8);
            RegisterFunction("vset_lane_u16", (Func<object, byte, ushort, object>)vset_lane_u16);
            RegisterFunction("vset_lane_u32", (Func<object, byte, uint, object>)vset_lane_u32);
            RegisterFunction("vset_lane_u8", (Func<object, byte, byte, object>)vset_lane_u8);
            RegisterFunction("vsetq_lane_f32", (Func<object, byte, float, object>)vsetq_lane_f32);
            RegisterFunction("vsetq_lane_f64", (Func<object, byte, double, object>)vsetq_lane_f64);
            RegisterFunction("vsetq_lane_s16", (Func<object, byte, short, object>)vsetq_lane_s16);
            RegisterFunction("vsetq_lane_s32", (Func<object, byte, int, object>)vsetq_lane_s32);
            RegisterFunction("vsetq_lane_s64", (Func<object, byte, long, object>)vsetq_lane_s64);
            RegisterFunction("vsetq_lane_s8", (Func<object, byte, sbyte, object>)vsetq_lane_s8);
            RegisterFunction("vsetq_lane_u16", (Func<object, byte, ushort, object>)vsetq_lane_u16);
            RegisterFunction("vsetq_lane_u32", (Func<object, byte, uint, object>)vsetq_lane_u32);
            RegisterFunction("vsetq_lane_u64", (Func<object, byte, ulong, object>)vsetq_lane_u64);
            RegisterFunction("vsetq_lane_u8", (Func<object, byte, byte, object>)vsetq_lane_u8);
            RegisterFunction("vshl_n_s16", (Func<object, byte, object>)vshl_n_s16);
            RegisterFunction("vshl_n_s32", (Func<object, byte, object>)vshl_n_s32);
            RegisterFunction("vshl_n_s64", (Func<object, byte, object>)vshl_n_s64);
            RegisterFunction("vshl_n_s8", (Func<object, byte, object>)vshl_n_s8);
            RegisterFunction("vshl_n_u16", (Func<object, byte, object>)vshl_n_u16);
            RegisterFunction("vshl_n_u32", (Func<object, byte, object>)vshl_n_u32);
            RegisterFunction("vshl_n_u64", (Func<object, byte, object>)vshl_n_u64);
            RegisterFunction("vshl_n_u8", (Func<object, byte, object>)vshl_n_u8);
            RegisterFunction("vshl_s16", (Func<object, object, object>)vshl_s16);
            RegisterFunction("vshl_s32", (Func<object, object, object>)vshl_s32);
            RegisterFunction("vshl_s64", (Func<object, object, object>)vshl_s64);
            RegisterFunction("vshl_s8", (Func<object, object, object>)vshl_s8);
            RegisterFunction("vshl_u16", (Func<object, object, object>)vshl_u16);
            RegisterFunction("vshl_u32", (Func<object, object, object>)vshl_u32);
            RegisterFunction("vshl_u64", (Func<object, object, object>)vshl_u64);
            RegisterFunction("vshl_u8", (Func<object, object, object>)vshl_u8);
            RegisterFunction("vshll_high_n_s16", (Func<object, byte, object>)vshll_high_n_s16);
            RegisterFunction("vshll_high_n_s32", (Func<object, byte, object>)vshll_high_n_s32);
            RegisterFunction("vshll_high_n_s8", (Func<object, byte, object>)vshll_high_n_s8);
            RegisterFunction("vshll_high_n_u16", (Func<object, byte, object>)vshll_high_n_u16);
            RegisterFunction("vshll_high_n_u32", (Func<object, byte, object>)vshll_high_n_u32);
            RegisterFunction("vshll_high_n_u8", (Func<object, byte, object>)vshll_high_n_u8);
            RegisterFunction("vshll_n_s16", (Func<object, byte, object>)vshll_n_s16);
            RegisterFunction("vshll_n_s32", (Func<object, byte, object>)vshll_n_s32);
            RegisterFunction("vshll_n_s8", (Func<object, byte, object>)vshll_n_s8);
            RegisterFunction("vshll_n_u16", (Func<object, byte, object>)vshll_n_u16);
            RegisterFunction("vshll_n_u32", (Func<object, byte, object>)vshll_n_u32);
            RegisterFunction("vshll_n_u8", (Func<object, byte, object>)vshll_n_u8);
            RegisterFunction("vshlq_n_s16", (Func<object, byte, object>)vshlq_n_s16);
            RegisterFunction("vshlq_n_s64", (Func<object, byte, object>)vshlq_n_s64);
            RegisterFunction("vshlq_n_s8", (Func<object, byte, object>)vshlq_n_s8);
            RegisterFunction("vshlq_n_u16", (Func<object, byte, object>)vshlq_n_u16);
            RegisterFunction("vshlq_n_u32", (Func<object, byte, object>)vshlq_n_u32);
            RegisterFunction("vshlq_n_u64", (Func<object, byte, object>)vshlq_n_u64);
            RegisterFunction("vshlq_n_u8", (Func<object, byte, object>)vshlq_n_u8);
            RegisterFunction("vshlq_s16", (Func<object, object, object>)vshlq_s16);
            RegisterFunction("vshlq_s32", (Func<object, object, object>)vshlq_s32);
            RegisterFunction("vshlq_s64", (Func<object, object, object>)vshlq_s64);
            RegisterFunction("vshlq_s8", (Func<object, object, object>)vshlq_s8);
            RegisterFunction("vshlq_u16", (Func<object, object, object>)vshlq_u16);
            RegisterFunction("vshlq_u32", (Func<object, object, object>)vshlq_u32);
            RegisterFunction("vshlq_u64", (Func<object, object, object>)vshlq_u64);
            RegisterFunction("vshlq_u8", (Func<object, object, object>)vshlq_u8);
            RegisterFunction("vshr_n_s16", (Func<object, byte, object>)vshr_n_s16);
            RegisterFunction("vshr_n_s32", (Func<object, byte, object>)vshr_n_s32);
            RegisterFunction("vshr_n_s64", (Func<object, byte, object>)vshr_n_s64);
            RegisterFunction("vshr_n_s8", (Func<object, byte, object>)vshr_n_s8);
            RegisterFunction("vshr_n_u16", (Func<object, byte, object>)vshr_n_u16);
            RegisterFunction("vshr_n_u32", (Func<object, byte, object>)vshr_n_u32);
            RegisterFunction("vshr_n_u64", (Func<object, byte, object>)vshr_n_u64);
            RegisterFunction("vshr_n_u8", (Func<object, byte, object>)vshr_n_u8);
            RegisterFunction("vshrn_high_n_s16", (Func<object, object, byte, object>)vshrn_high_n_s16);
            RegisterFunction("vshrn_high_n_s32", (Func<object, object, byte, object>)vshrn_high_n_s32);
            RegisterFunction("vshrn_high_n_s64", (Func<object, object, byte, object>)vshrn_high_n_s64);
            RegisterFunction("vshrn_high_n_u16", (Func<object, object, byte, object>)vshrn_high_n_u16);
            RegisterFunction("vshrn_high_n_u32", (Func<object, object, byte, object>)vshrn_high_n_u32);
            RegisterFunction("vshrn_high_n_u64", (Func<object, object, byte, object>)vshrn_high_n_u64);
            RegisterFunction("vshrn_n_s16", (Func<object, byte, object>)vshrn_n_s16);
            RegisterFunction("vshrn_n_s32", (Func<object, byte, object>)vshrn_n_s32);
            RegisterFunction("vshrn_n_s64", (Func<object, byte, object>)vshrn_n_s64);
            RegisterFunction("vshrn_n_u16", (Func<object, byte, object>)vshrn_n_u16);
            RegisterFunction("vshrn_n_u32", (Func<object, byte, object>)vshrn_n_u32);
            RegisterFunction("vshrn_n_u64", (Func<object, byte, object>)vshrn_n_u64);
            RegisterFunction("vshrq_n_s16", (Func<object, byte, object>)vshrq_n_s16);
            RegisterFunction("vshrq_n_s32", (Func<object, byte, object>)vshrq_n_s32);
            RegisterFunction("vshrq_n_s64", (Func<object, byte, object>)vshrq_n_s64);
            RegisterFunction("vshrq_n_s8", (Func<object, byte, object>)vshrq_n_s8);
            RegisterFunction("vshrq_n_u16", (Func<object, byte, object>)vshrq_n_u16);
            RegisterFunction("vshrq_n_u32", (Func<object, byte, object>)vshrq_n_u32);
            RegisterFunction("vshrq_n_u64", (Func<object, byte, object>)vshrq_n_u64);
            RegisterFunction("vshrq_n_u8", (Func<object, byte, object>)vshrq_n_u8);
            RegisterFunction("vsqrt_f64", (Func<object, object>)vsqrt_f64);
            RegisterFunction("vsqrts_f32", (Func<object, object>)vsqrts_f32);
            RegisterFunction("vsra_n_s16", (Func<object, object, byte, object>)vsra_n_s16);
            RegisterFunction("vsra_n_s32", (Func<object, object, byte, object>)vsra_n_s32);
            RegisterFunction("vsra_n_s64", (Func<object, object, byte, object>)vsra_n_s64);
            RegisterFunction("vsra_n_s8", (Func<object, object, byte, object>)vsra_n_s8);
            RegisterFunction("vsra_n_u16", (Func<object, object, byte, object>)vsra_n_u16);
            RegisterFunction("vsra_n_u32", (Func<object, object, byte, object>)vsra_n_u32);
            RegisterFunction("vsra_n_u64", (Func<object, object, byte, object>)vsra_n_u64);
            RegisterFunction("vsra_n_u8", (Func<object, object, byte, object>)vsra_n_u8);
            RegisterFunction("vsraq_n_s16", (Func<object, object, byte, object>)vsraq_n_s16);
            RegisterFunction("vsraq_n_s32", (Func<object, object, byte, object>)vsraq_n_s32);
            RegisterFunction("vsraq_n_s64", (Func<object, object, byte, object>)vsraq_n_s64);
            RegisterFunction("vsraq_n_s8", (Func<object, object, byte, object>)vsraq_n_s8);
            RegisterFunction("vsraq_n_u16", (Func<object, object, byte, object>)vsraq_n_u16);
            RegisterFunction("vsraq_n_u32", (Func<object, object, byte, object>)vsraq_n_u32);
            RegisterFunction("vsraq_n_u64", (Func<object, object, byte, object>)vsraq_n_u64);
            RegisterFunction("vsraq_n_u8", (Func<object, object, byte, object>)vsraq_n_u8);
            RegisterFunction("vsri_n_s16", (Func<object, object, byte, object>)vsri_n_s16);
            RegisterFunction("vsri_n_s32", (Func<object, object, byte, object>)vsri_n_s32);
            RegisterFunction("vsri_n_s8", (Func<object, object, byte, object>)vsri_n_s8);
            RegisterFunction("vsri_n_u16", (Func<object, object, byte, object>)vsri_n_u16);
            RegisterFunction("vsri_n_u32", (Func<object, object, byte, object>)vsri_n_u32);
            RegisterFunction("vsri_n_u8", (Func<object, object, byte, object>)vsri_n_u8);
            RegisterFunction("vsriq_n_s16", (Func<object, object, byte, object>)vsriq_n_s16);
            RegisterFunction("vsriq_n_s32", (Func<object, object, byte, object>)vsriq_n_s32);
            RegisterFunction("vsriq_n_s64", (Func<object, object, byte, object>)vsriq_n_s64);
            RegisterFunction("vsriq_n_s8", (Func<object, object, byte, object>)vsriq_n_s8);
            RegisterFunction("vsriq_n_u16", (Func<object, object, byte, object>)vsriq_n_u16);
            RegisterFunction("vsriq_n_u32", (Func<object, object, byte, object>)vsriq_n_u32);
            RegisterFunction("vsriq_n_u64", (Func<object, object, byte, object>)vsriq_n_u64);
            RegisterFunction("vsriq_n_u8", (Func<object, object, byte, object>)vsriq_n_u8);
            RegisterAction("vst1_f32", (Action<object, object>)vst1_f32);
            RegisterAction("vst1_f64", (Action<object, object>)vst1_f64);
            RegisterAction("vst1_lane_f32", (Action<object, object, byte>)vst1_lane_f32);
            RegisterAction("vst1_lane_s16", (Action<object, object, byte>)vst1_lane_s16);
            RegisterAction("vst1_lane_s32", (Action<object, object, byte>)vst1_lane_s32);
            RegisterAction("vst1_lane_s8", (Action<object, object, byte>)vst1_lane_s8);
            RegisterAction("vst1_lane_u16", (Action<object, object, byte>)vst1_lane_u16);
            RegisterAction("vst1_lane_u32", (Action<object, object, byte>)vst1_lane_u32);
            RegisterAction("vst1_lane_u8", (Action<object, object, byte>)vst1_lane_u8);
            RegisterAction("vst1_s16", (Action<object, object>)vst1_s16);
            RegisterAction("vst1_s32", (Action<object, object>)vst1_s32);
            RegisterAction("vst1_s64", (Action<object, object>)vst1_s64);
            RegisterAction("vst1_s8", (Action<object, object>)vst1_s8);
            RegisterAction("vst1_u16", (Action<object, object>)vst1_u16);
            RegisterAction("vst1_u32", (Action<object, object>)vst1_u32);
            RegisterAction("vst1_u64", (Action<object, object>)vst1_u64);
            RegisterAction("vst1_u8", (Action<object, object>)vst1_u8);
            RegisterAction("vst1q_f32", (Action<object, object>)vst1q_f32);
            RegisterAction("vst1q_f64", (Action<object, object>)vst1q_f64);
            RegisterAction("vst1q_lane_f32", (Action<object, object, byte>)vst1q_lane_f32);
            RegisterAction("vst1q_lane_f64", (Action<object, object, byte>)vst1q_lane_f64);
            RegisterAction("vst1q_lane_s16", (Action<object, object, byte>)vst1q_lane_s16);
            RegisterAction("vst1q_lane_s32", (Action<object, object, byte>)vst1q_lane_s32);
            RegisterAction("vst1q_lane_s64", (Action<object, object, byte>)vst1q_lane_s64);
            RegisterAction("vst1q_lane_s8", (Action<object, object, byte>)vst1q_lane_s8);
            RegisterAction("vst1q_lane_u16", (Action<object, object, byte>)vst1q_lane_u16);
            RegisterAction("vst1q_lane_u32", (Action<object, object, byte>)vst1q_lane_u32);
            RegisterAction("vst1q_lane_u64", (Action<object, object, byte>)vst1q_lane_u64);
            RegisterAction("vst1q_lane_u8", (Action<object, object, byte>)vst1q_lane_u8);
            RegisterAction("vst1q_s16", (Action<object, object>)vst1q_s16);
            RegisterAction("vst1q_s32", (Action<object, object>)vst1q_s32);
            RegisterAction("vst1q_s64", (Action<object, object>)vst1q_s64);
            RegisterAction("vst1q_s8", (Action<object, object>)vst1q_s8);
            RegisterAction("vst1q_u16", (Action<object, object>)vst1q_u16);
            RegisterAction("vst1q_u32", (Action<object, object>)vst1q_u32);
            RegisterAction("vst1q_u64", (Action<object, object>)vst1q_u64);
            RegisterAction("vst1q_u8", (Action<object, object>)vst1q_u8);
            RegisterFunction("vsub_f32", (Func<object, object, object>)vsub_f32);
            RegisterFunction("vsub_f64", (Func<object, object, object>)vsub_f64);
            RegisterFunction("vsub_s16", (Func<object, object, object>)vsub_s16);
            RegisterFunction("vsub_s32", (Func<object, object, object>)vsub_s32);
            RegisterFunction("vsub_s64", (Func<object, object, object>)vsub_s64);
            RegisterFunction("vsub_s8", (Func<object, object, object>)vsub_s8);
            RegisterFunction("vsub_u16", (Func<object, object, object>)vsub_u16);
            RegisterFunction("vsub_u32", (Func<object, object, object>)vsub_u32);
            RegisterFunction("vsub_u64", (Func<object, object, object>)vsub_u64);
            RegisterFunction("vsub_u8", (Func<object, object, object>)vsub_u8);
            RegisterFunction("vsubhn_high_s16", (Func<object, object, object, object>)vsubhn_high_s16);
            RegisterFunction("vsubhn_high_s32", (Func<object, object, object, object>)vsubhn_high_s32);
            RegisterFunction("vsubhn_high_s64", (Func<object, object, object, object>)vsubhn_high_s64);
            RegisterFunction("vsubhn_high_u16", (Func<object, object, object, object>)vsubhn_high_u16);
            RegisterFunction("vsubhn_high_u32", (Func<object, object, object, object>)vsubhn_high_u32);
            RegisterFunction("vsubhn_high_u64", (Func<object, object, object, object>)vsubhn_high_u64);
            RegisterFunction("vsubhn_s16", (Func<object, object, object>)vsubhn_s16);
            RegisterFunction("vsubhn_s32", (Func<object, object, object>)vsubhn_s32);
            RegisterFunction("vsubhn_s64", (Func<object, object, object>)vsubhn_s64);
            RegisterFunction("vsubhn_u16", (Func<object, object, object>)vsubhn_u16);
            RegisterFunction("vsubhn_u32", (Func<object, object, object>)vsubhn_u32);
            RegisterFunction("vsubhn_u64", (Func<object, object, object>)vsubhn_u64);
            RegisterFunction("vsubl_high_s16", (Func<object, object, object>)vsubl_high_s16);
            RegisterFunction("vsubl_high_s32", (Func<object, object, object>)vsubl_high_s32);
            RegisterFunction("vsubl_high_s8", (Func<object, object, object>)vsubl_high_s8);
            RegisterFunction("vsubl_high_u16", (Func<object, object, object>)vsubl_high_u16);
            RegisterFunction("vsubl_high_u32", (Func<object, object, object>)vsubl_high_u32);
            RegisterFunction("vsubl_high_u8", (Func<object, object, object>)vsubl_high_u8);
            RegisterFunction("vsubl_s16", (Func<object, object, object>)vsubl_s16);
            RegisterFunction("vsubl_s32", (Func<object, object, object>)vsubl_s32);
            RegisterFunction("vsubl_s8", (Func<object, object, object>)vsubl_s8);
            RegisterFunction("vsubl_u16", (Func<object, object, object>)vsubl_u16);
            RegisterFunction("vsubl_u32", (Func<object, object, object>)vsubl_u32);
            RegisterFunction("vsubl_u8", (Func<object, object, object>)vsubl_u8);
            RegisterFunction("vsubq_f32", (Func<object, object, object>)vsubq_f32);
            RegisterFunction("vsubq_s16", (Func<object, object, object>)vsubq_s16);
            RegisterFunction("vsubq_s32", (Func<object, object, object>)vsubq_s32);
            RegisterFunction("vsubq_s64", (Func<object, object, object>)vsubq_s64);
            RegisterFunction("vsubq_s8", (Func<object, object, object>)vsubq_s8);
            RegisterFunction("vsubq_u16", (Func<object, object, object>)vsubq_u16);
            RegisterFunction("vsubq_u32", (Func<object, object, object>)vsubq_u32);
            RegisterFunction("vsubq_u64", (Func<object, object, object>)vsubq_u64);
            RegisterFunction("vsubq_u8", (Func<object, object, object>)vsubq_u8);
            RegisterFunction("vsubs_f32", (Func<object, object, object>)vsubs_f32);
            RegisterFunction("vsubw_high_s16", (Func<object, object, object>)vsubw_high_s16);
            RegisterFunction("vsubw_high_s32", (Func<object, object, object>)vsubw_high_s32);
            RegisterFunction("vsubw_high_s8", (Func<object, object, object>)vsubw_high_s8);
            RegisterFunction("vsubw_high_u16", (Func<object, object, object>)vsubw_high_u16);
            RegisterFunction("vsubw_high_u32", (Func<object, object, object>)vsubw_high_u32);
            RegisterFunction("vsubw_high_u8", (Func<object, object, object>)vsubw_high_u8);
            RegisterFunction("vsubw_s16", (Func<object, object, object>)vsubw_s16);
            RegisterFunction("vsubw_s32", (Func<object, object, object>)vsubw_s32);
            RegisterFunction("vsubw_s8", (Func<object, object, object>)vsubw_s8);
            RegisterFunction("vsubw_u16", (Func<object, object, object>)vsubw_u16);
            RegisterFunction("vsubw_u32", (Func<object, object, object>)vsubw_u32);
            RegisterFunction("vsubw_u8", (Func<object, object, object>)vsubw_u8);
            RegisterFunction("vtst_f32", (Func<object, object, object>)vtst_f32);
            RegisterFunction("vtst_s16", (Func<object, object, object>)vtst_s16);
            RegisterFunction("vtst_s32", (Func<object, object, object>)vtst_s32);
            RegisterFunction("vtst_s8", (Func<object, object, object>)vtst_s8);
            RegisterFunction("vtst_u16", (Func<object, object, object>)vtst_u16);
            RegisterFunction("vtst_u32", (Func<object, object, object>)vtst_u32);
            RegisterFunction("vtst_u8", (Func<object, object, object>)vtst_u8);
            RegisterFunction("vtstq_f32", (Func<object, object, object>)vtstq_f32);
            RegisterFunction("vtstq_s16", (Func<object, object, object>)vtstq_s16);
            RegisterFunction("vtstq_s32", (Func<object, object, object>)vtstq_s32);
            RegisterFunction("vtstq_s8", (Func<object, object, object>)vtstq_s8);
            RegisterFunction("vtstq_u16", (Func<object, object, object>)vtstq_u16);
            RegisterFunction("vtstq_u32", (Func<object, object, object>)vtstq_u32);
            RegisterFunction("vtstq_u8", (Func<object, object, object>)vtstq_u8);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["vaba_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vaba_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
    A32: VABA.S16 Dd, Dn, Dm
    A64: SABA Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vaba_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaba_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vaba_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
    A32: VABA.S32 Dd, Dn, Dm
    A64: SABA Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vaba_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaba_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vaba_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
    A32: VABA.S8 Dd, Dn, Dm
    A64: SABA Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vaba_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaba_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vaba_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
    A32: VABA.U16 Dd, Dn, Dm
    A64: UABA Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vaba_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaba_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vaba_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
    A32: VABA.U32 Dd, Dn, Dm
    A64: UABA Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vaba_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaba_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vaba_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
    A32: VABA.U8 Dd, Dn, Dm
    A64: UABA Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vaba_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaba_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vabal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
    A32: VABAL.S16 Qd, Dn+1, Dm+1
    A64: SABAL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vabal_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vabal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
    A32: VABAL.S32 Qd, Dn+1, Dm+1
    A64: SABAL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vabal_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_high_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vabal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
    A32: VABAL.S8 Qd, Dn+1, Dm+1
    A64: SABAL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vabal_high_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vabal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
    A32: VABAL.U16 Qd, Dn+1, Dm+1
    A64: UABAL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vabal_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vabal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
    A32: VABAL.U32 Qd, Dn+1, Dm+1
    A64: UABAL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vabal_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_high_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vabal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
    A32: VABAL.U8 Qd, Dn+1, Dm+1
    A64: UABAL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vabal_high_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_high_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vabal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
    A32: VABAL.S16 Qd, Dn, Dm
    A64: SABAL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vabal_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vabal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
    A32: VABAL.S32 Qd, Dn, Dm
    A64: SABAL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vabal_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vabal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
    A32: VABAL.S8 Qd, Dn, Dm
    A64: SABAL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vabal_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vabal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
    A32: VABAL.U16 Qd, Dn, Dm
    A64: UABAL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vabal_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vabal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
    A32: VABAL.U32 Qd, Dn, Dm
    A64: UABAL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vabal_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabal_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vabal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
    A32: VABAL.U8 Qd, Dn, Dm
    A64: UABAL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vabal_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabal_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabaq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vabaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
    A32: VABA.S16 Qd, Qn, Qm
    A64: SABA Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vabaq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabaq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vabaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
    A32: VABA.S32 Qd, Qn, Qm
    A64: SABA Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vabaq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabaq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vabaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
    A32: VABA.S8 Qd, Qn, Qm
    A64: SABA Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vabaq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabaq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vabaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
    A32: VABA.U16 Qd, Qn, Qm
    A64: UABA Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vabaq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabaq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vabaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
    A32: VABA.U32 Qd, Qn, Qm
    A64: UABA Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vabaq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabaq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vabaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
    A32: VABA.U8 Qd, Qn, Qm
    A64: UABA Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vabaq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabaq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabd_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vabd_f32 (float32x2_t a, float32x2_t b)
    A32: VABD.F32 Dd, Dn, Dm
    A64: FABD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vabd_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabd_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vabd_s16 (int16x4_t a, int16x4_t b)
    A32: VABD.S16 Dd, Dn, Dm
    A64: SABD Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vabd_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabd_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vabd_s32 (int32x2_t a, int32x2_t b)
    A32: VABD.S32 Dd, Dn, Dm
    A64: SABD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vabd_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabd_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vabd_s8 (int8x8_t a, int8x8_t b)
    A32: VABD.S8 Dd, Dn, Dm
    A64: SABD Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vabd_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabd_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vabd_u16 (uint16x4_t a, uint16x4_t b)
    A32: VABD.U16 Dd, Dn, Dm
    A64: UABD Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vabd_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabd_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vabd_u32 (uint32x2_t a, uint32x2_t b)
    A32: VABD.U32 Dd, Dn, Dm
    A64: UABD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vabd_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabd_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vabd_u8 (uint8x8_t a, uint8x8_t b)
    A32: VABD.U8 Dd, Dn, Dm
    A64: UABD Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vabd_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabd_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vabdl_high_s16 (int16x8_t a, int16x8_t b)
    A32: VABDL.S16 Qd, Dn+1, Dm+1
    A64: SABDL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vabdl_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vabdl_high_s32 (int32x4_t a, int32x4_t b)
    A32: VABDL.S32 Qd, Dn+1, Dm+1
    A64: SABDL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vabdl_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_high_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vabdl_high_s8 (int8x16_t a, int8x16_t b)
    A32: VABDL.S8 Qd, Dn+1, Dm+1
    A64: SABDL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vabdl_high_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vabdl_high_u16 (uint16x8_t a, uint16x8_t b)
    A32: VABDL.U16 Qd, Dn+1, Dm+1
    A64: UABDL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vabdl_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vabdl_high_u32 (uint32x4_t a, uint32x4_t b)
    A32: VABDL.U32 Qd, Dn+1, Dm+1
    A64: UABDL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vabdl_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_high_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vabdl_high_u8 (uint8x16_t a, uint8x16_t b)
    A32: VABDL.U8 Qd, Dn+1, Dm+1
    A64: UABDL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vabdl_high_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_high_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vabdl_s16 (int16x4_t a, int16x4_t b)
    A32: VABDL.S16 Qd, Dn, Dm
    A64: SABDL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vabdl_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vabdl_s32 (int32x2_t a, int32x2_t b)
    A32: VABDL.S32 Qd, Dn, Dm
    A64: SABDL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vabdl_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vabdl_s8 (int8x8_t a, int8x8_t b)
    A32: VABDL.S8 Qd, Dn, Dm
    A64: SABDL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vabdl_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vabdl_u16 (uint16x4_t a, uint16x4_t b)
    A32: VABDL.U16 Qd, Dn, Dm
    A64: UABDL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vabdl_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vabdl_u32 (uint32x2_t a, uint32x2_t b)
    A32: VABDL.U32 Qd, Dn, Dm
    A64: UABDL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vabdl_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdl_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vabdl_u8 (uint8x8_t a, uint8x8_t b)
    A32: VABDL.U8 Qd, Dn, Dm
    A64: UABDL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vabdl_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdl_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vabdq_f32 (float32x4_t a, float32x4_t b)
    A32: VABD.F32 Qd, Qn, Qm
    A64: FABD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vabdq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vabdq_s16 (int16x8_t a, int16x8_t b)
    A32: VABD.S16 Qd, Qn, Qm
    A64: SABD Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vabdq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vabdq_s32 (int32x4_t a, int32x4_t b)
    A32: VABD.S32 Qd, Qn, Qm
    A64: SABD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vabdq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vabdq_s8 (int8x16_t a, int8x16_t b)
    A32: VABD.S8 Qd, Qn, Qm
    A64: SABD Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vabdq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vabdq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VABD.U16 Qd, Qn, Qm
    A64: UABD Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vabdq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vabdq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VABD.U32 Qd, Qn, Qm
    A64: UABD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vabdq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabdq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vabdq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VABD.U8 Qd, Qn, Qm
    A64: UABD Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vabdq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabdq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabs_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vabs_f32 (float32x2_t a)
    A32: VABS.F32 Dd, Dm
    A64: FABS Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vabs_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabs_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vabs_f64 (float64x1_t a)
    A32: VABS.F64 Dd, Dm
    A64: FABS Dd, Dn
    
    
    Instruction Documentation: [vabs_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabs_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vabs_s16 (int16x4_t a)
    A32: VABS.S16 Dd, Dm
    A64: ABS Vd.4H, Vn.4H
    
    
    Instruction Documentation: [vabs_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabs_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vabs_s32 (int32x2_t a)
    A32: VABS.S32 Dd, Dm
    A64: ABS Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vabs_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabs_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vabs_s8 (int8x8_t a)
    A32: VABS.S8 Dd, Dm
    A64: ABS Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vabs_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabs_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabsq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vabsq_f32 (float32x4_t a)
    A32: VABS.F32 Qd, Qm
    A64: FABS Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vabsq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabsq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vabsq_s16 (int16x8_t a)
    A32: VABS.S16 Qd, Qm
    A64: ABS Vd.8H, Vn.8H
    
    
    Instruction Documentation: [vabsq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabsq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vabsq_s32 (int32x4_t a)
    A32: VABS.S32 Qd, Qm
    A64: ABS Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vabsq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabsq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vabsq_s8 (int8x16_t a)
    A32: VABS.S8 Qd, Qm
    A64: ABS Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vabsq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabsq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vabss_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vabss_f32 (float32_t a)
    A32: VABS.F32 Sd, Sm
    A64: FABS Sd, Sn The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vabss_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vabss_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vadd_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vadd_f32 (float32x2_t a, float32x2_t b)
    A32: VADD.F32 Dd, Dn, Dm
    A64: FADD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vadd_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vadd_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vadd_f64 (float64x1_t a, float64x1_t b)
    A32: VADD.F64 Dd, Dn, Dm
    A64: FADD Dd, Dn, Dm
    
    
    Instruction Documentation: [vadd_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vadd_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vadd_s16 (int16x4_t a, int16x4_t b)
    A32: VADD.I16 Dd, Dn, Dm
    A64: ADD Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vadd_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vadd_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vadd_s32 (int32x2_t a, int32x2_t b)
    A32: VADD.I32 Dd, Dn, Dm
    A64: ADD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vadd_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vadd_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vadd_s64 (int64x1_t a, int64x1_t b)
    A32: VADD.I64 Dd, Dn, Dm
    A64: ADD Dd, Dn, Dm
    
    
    Instruction Documentation: [vadd_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vadd_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vadd_s8 (int8x8_t a, int8x8_t b)
    A32: VADD.I8 Dd, Dn, Dm
    A64: ADD Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vadd_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vadd_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vadd_u16 (uint16x4_t a, uint16x4_t b)
    A32: VADD.I16 Dd, Dn, Dm
    A64: ADD Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vadd_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vadd_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vadd_u32 (uint32x2_t a, uint32x2_t b)
    A32: VADD.I32 Dd, Dn, Dm
    A64: ADD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vadd_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vadd_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vadd_u64 (uint64x1_t a, uint64x1_t b)
    A32: VADD.I64 Dd, Dn, Dm
    A64: ADD Dd, Dn, Dm
    
    
    Instruction Documentation: [vadd_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vadd_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vadd_u8 (uint8x8_t a, uint8x8_t b)
    A32: VADD.I8 Dd, Dn, Dm
    A64: ADD Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vadd_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadd_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vaddhn_high_s16 (int8x8_t r, int16x8_t a, int16x8_t b)
    A32: VADDHN.I16 Dd+1, Qn, Qm
    A64: ADDHN2 Vd.16B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vaddhn_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vaddhn_high_s32 (int16x4_t r, int32x4_t a, int32x4_t b)
    A32: VADDHN.I32 Dd+1, Qn, Qm
    A64: ADDHN2 Vd.8H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vaddhn_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_high_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vaddhn_high_s64 (int32x2_t r, int64x2_t a, int64x2_t b)
    A32: VADDHN.I64 Dd+1, Qn, Qm
    A64: ADDHN2 Vd.4S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vaddhn_high_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vaddhn_high_u16 (uint8x8_t r, uint16x8_t a, uint16x8_t b)
    A32: VADDHN.I16 Dd+1, Qn, Qm
    A64: ADDHN2 Vd.16B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vaddhn_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vaddhn_high_u32 (uint16x4_t r, uint32x4_t a, uint32x4_t b)
    A32: VADDHN.I32 Dd+1, Qn, Qm
    A64: ADDHN2 Vd.8H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vaddhn_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_high_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vaddhn_high_u64 (uint32x2_t r, uint64x2_t a, uint64x2_t b)
    A32: VADDHN.I64 Dd+1, Qn, Qm
    A64: ADDHN2 Vd.4S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vaddhn_high_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_high_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vaddhn_s16 (int16x8_t a, int16x8_t b)
    A32: VADDHN.I16 Dd, Qn, Qm
    A64: ADDHN Vd.8B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vaddhn_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vaddhn_s32 (int32x4_t a, int32x4_t b)
    A32: VADDHN.I32 Dd, Qn, Qm
    A64: ADDHN Vd.4H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vaddhn_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vaddhn_s64 (int64x2_t a, int64x2_t b)
    A32: VADDHN.I64 Dd, Qn, Qm
    A64: ADDHN Vd.2S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vaddhn_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vaddhn_u16 (uint16x8_t a, uint16x8_t b)
    A32: VADDHN.I16 Dd, Qn, Qm
    A64: ADDHN Vd.8B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vaddhn_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vaddhn_u32 (uint32x4_t a, uint32x4_t b)
    A32: VADDHN.I32 Dd, Qn, Qm
    A64: ADDHN Vd.4H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vaddhn_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddhn_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vaddhn_u64 (uint64x2_t a, uint64x2_t b)
    A32: VADDHN.I64 Dd, Qn, Qm
    A64: ADDHN Vd.2S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vaddhn_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddhn_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vaddl_high_s16 (int16x8_t a, int16x8_t b)
    A32: VADDL.S16 Qd, Dn+1, Dm+1
    A64: SADDL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vaddl_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vaddl_high_s32 (int32x4_t a, int32x4_t b)
    A32: VADDL.S32 Qd, Dn+1, Dm+1
    A64: SADDL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vaddl_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_high_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vaddl_high_s8 (int8x16_t a, int8x16_t b)
    A32: VADDL.S8 Qd, Dn+1, Dm+1
    A64: SADDL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vaddl_high_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vaddl_high_u16 (uint16x8_t a, uint16x8_t b)
    A32: VADDL.U16 Qd, Dn+1, Dm+1
    A64: UADDL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vaddl_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vaddl_high_u32 (uint32x4_t a, uint32x4_t b)
    A32: VADDL.U32 Qd, Dn+1, Dm+1
    A64: UADDL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vaddl_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_high_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vaddl_high_u8 (uint8x16_t a, uint8x16_t b)
    A32: VADDL.U8 Qd, Dn+1, Dm+1
    A64: UADDL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vaddl_high_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_high_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vaddl_s16 (int16x4_t a, int16x4_t b)
    A32: VADDL.S16 Qd, Dn, Dm
    A64: SADDL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vaddl_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vaddl_s32 (int32x2_t a, int32x2_t b)
    A32: VADDL.S32 Qd, Dn, Dm
    A64: SADDL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vaddl_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vaddl_s8 (int8x8_t a, int8x8_t b)
    A32: VADDL.S8 Qd, Dn, Dm
    A64: SADDL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vaddl_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vaddl_u16 (uint16x4_t a, uint16x4_t b)
    A32: VADDL.U16 Qd, Dn, Dm
    A64: UADDL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vaddl_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vaddl_u32 (uint32x2_t a, uint32x2_t b)
    A32: VADDL.U32 Qd, Dn, Dm
    A64: UADDL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vaddl_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddl_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vaddl_u8 (uint8x8_t a, uint8x8_t b)
    A32: VADDL.U8 Qd, Dn, Dm
    A64: UADDL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vaddl_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddl_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vaddq_f32 (float32x4_t a, float32x4_t b)
    A32: VADD.F32 Qd, Qn, Qm
    A64: FADD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vaddq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vaddq_s16 (int16x8_t a, int16x8_t b)
    A32: VADD.I16 Qd, Qn, Qm
    A64: ADD Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vaddq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vaddq_s32 (int32x4_t a, int32x4_t b)
    A32: VADD.I32 Qd, Qn, Qm
    A64: ADD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vaddq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vaddq_s64 (int64x2_t a, int64x2_t b)
    A32: VADD.I64 Qd, Qn, Qm
    A64: ADD Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vaddq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vaddq_s8 (int8x16_t a, int8x16_t b)
    A32: VADD.I8 Qd, Qn, Qm
    A64: ADD Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vaddq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vaddq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VADD.I16 Qd, Qn, Qm
    A64: ADD Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vaddq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vaddq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VADD.I32 Qd, Qn, Qm
    A64: ADD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vaddq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vaddq_u64 (uint64x2_t a, uint64x2_t b)
    A32: VADD.I64 Qd, Qn, Qm
    A64: ADD Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vaddq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vaddq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VADD.I8 Qd, Qn, Qm
    A64: ADD Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vaddq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vadds_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vadds_f32 (float32_t a, float32_t b)
    A32: VADD.F32 Sd, Sn, Sm
    A64: FADD Sd, Sn, Sm The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vadds_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vadds_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vaddw_high_s16 (int32x4_t a, int16x8_t b)
    A32: VADDW.S16 Qd, Qn, Dm+1
    A64: SADDW2 Vd.4S, Vn.4S, Vm.8H
    
    
    Instruction Documentation: [vaddw_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vaddw_high_s32 (int64x2_t a, int32x4_t b)
    A32: VADDW.S32 Qd, Qn, Dm+1
    A64: SADDW2 Vd.2D, Vn.2D, Vm.4S
    
    
    Instruction Documentation: [vaddw_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_high_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vaddw_high_s8 (int16x8_t a, int8x16_t b)
    A32: VADDW.S8 Qd, Qn, Dm+1
    A64: SADDW2 Vd.8H, Vn.8H, Vm.16B
    
    
    Instruction Documentation: [vaddw_high_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vaddw_high_u16 (uint32x4_t a, uint16x8_t b)
    A32: VADDW.U16 Qd, Qn, Dm+1
    A64: UADDW2 Vd.4S, Vn.4S, Vm.8H
    
    
    Instruction Documentation: [vaddw_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vaddw_high_u32 (uint64x2_t a, uint32x4_t b)
    A32: VADDW.U32 Qd, Qn, Dm+1
    A64: UADDW2 Vd.2D, Vn.2D, Vm.4S
    
    
    Instruction Documentation: [vaddw_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_high_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vaddw_high_u8 (uint16x8_t a, uint8x16_t b)
    A32: VADDW.U8 Qd, Qn, Dm+1
    A64: UADDW2 Vd.8H, Vn.8H, Vm.16B
    
    
    Instruction Documentation: [vaddw_high_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_high_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vaddw_s16 (int32x4_t a, int16x4_t b)
    A32: VADDW.S16 Qd, Qn, Dm
    A64: SADDW Vd.4S, Vn.4S, Vm.4H
    
    
    Instruction Documentation: [vaddw_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vaddw_s32 (int64x2_t a, int32x2_t b)
    A32: VADDW.S32 Qd, Qn, Dm
    A64: SADDW Vd.2D, Vn.2D, Vm.2S
    
    
    Instruction Documentation: [vaddw_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vaddw_s8 (int16x8_t a, int8x8_t b)
    A32: VADDW.S8 Qd, Qn, Dm
    A64: SADDW Vd.8H, Vn.8H, Vm.8B
    
    
    Instruction Documentation: [vaddw_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vaddw_u16 (uint32x4_t a, uint16x4_t b)
    A32: VADDW.U16 Qd, Qn, Dm
    A64: UADDW Vd.4S, Vn.4S, Vm.4H
    
    
    Instruction Documentation: [vaddw_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vaddw_u32 (uint64x2_t a, uint32x2_t b)
    A32: VADDW.U32 Qd, Qn, Dm
    A64: UADDW Vd.2D, Vn.2D, Vm.2S
    
    
    Instruction Documentation: [vaddw_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaddw_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vaddw_u8 (uint16x8_t a, uint8x8_t b)
    A32: VADDW.U8 Qd, Qn, Dm
    A64: UADDW Vd.8H, Vn.8H, Vm.8B
    
    
    Instruction Documentation: [vaddw_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaddw_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vand_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vand_f32 (float32x2_t a, float32x2_t b)
    A32: VAND Dd, Dn, Dm
    A64: AND Vd.8B, Vn.8B, Vm.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vand_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vand_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vand_f64 (float64x1_t a, float64x1_t b)
    A32: VAND Dd, Dn, Dm
    A64: AND Vd.8B, Vn.8B, Vm.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vand_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vand_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vand_s16 (int16x4_t a, int16x4_t b)
    A32: VAND Dd, Dn, Dm
    A64: AND Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vand_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vand_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vand_s32 (int32x2_t a, int32x2_t b)
    A32: VAND Dd, Dn, Dm
    A64: AND Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vand_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vand_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vand_s64 (int64x1_t a, int64x1_t b)
    A32: VAND Dd, Dn, Dm
    A64: AND Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vand_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vand_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vand_s8 (int8x8_t a, int8x8_t b)
    A32: VAND Dd, Dn, Dm
    A64: AND Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vand_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vand_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vand_u16 (uint16x4_t a, uint16x4_t b)
    A32: VAND Dd, Dn, Dm
    A64: AND Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vand_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vand_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vand_u32 (uint32x2_t a, uint32x2_t b)
    A32: VAND Dd, Dn, Dm
    A64: AND Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vand_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vand_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vand_u64 (uint64x1_t a, uint64x1_t b)
    A32: VAND Dd, Dn, Dm
    A64: AND Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vand_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vand_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vand_u8 (uint8x8_t a, uint8x8_t b)
    A32: VAND Dd, Dn, Dm
    A64: AND Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vand_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vand_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vandq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vandq_f32 (float32x4_t a, float32x4_t b)
    A32: VAND Qd, Qn, Qm
    A64: AND Vd.16B, Vn.16B, Vm.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vandq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vandq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vandq_f64 (float64x2_t a, float64x2_t b)
    A32: VAND Qd, Qn, Qm
    A64: AND Vd.16B, Vn.16B, Vm.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vandq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vandq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vandq_s16 (int16x8_t a, int16x8_t b)
    A32: VAND Qd, Qn, Qm
    A64: AND Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vandq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vandq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vandq_s32 (int32x4_t a, int32x4_t b)
    A32: VAND Qd, Qn, Qm
    A64: AND Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vandq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vandq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vandq_s64 (int64x2_t a, int64x2_t b)
    A32: VAND Qd, Qn, Qm
    A64: AND Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vandq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vandq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vandq_s8 (int8x16_t a, int8x16_t b)
    A32: VAND Qd, Qn, Qm
    A64: AND Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vandq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vandq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vandq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VAND Qd, Qn, Qm
    A64: AND Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vandq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vandq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vandq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VAND Qd, Qn, Qm
    A64: AND Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vandq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vandq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vandq_u64 (uint64x2_t a, uint64x2_t b)
    A32: VAND Qd, Qn, Qm
    A64: AND Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vandq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vandq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vandq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VAND Qd, Qn, Qm
    A64: AND Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vandq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vandq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbic_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vbic_f32 (float32x2_t a, float32x2_t b)
    A32: VBIC Dd, Dn, Dm
    A64: BIC Vd.8B, Vn.8B, Vm.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vbic_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbic_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vbic_f64 (float64x1_t a, float64x1_t b)
    A32: VBIC Dd, Dn, Dm
    A64: BIC Vd.8B, Vn.8B, Vm.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vbic_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbic_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vbic_s16 (int16x4_t a, int16x4_t b)
    A32: VBIC Dd, Dn, Dm
    A64: BIC Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbic_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbic_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vbic_s32 (int32x2_t a, int32x2_t b)
    A32: VBIC Dd, Dn, Dm
    A64: BIC Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbic_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbic_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vbic_s64 (int64x1_t a, int64x1_t b)
    A32: VBIC Dd, Dn, Dm
    A64: BIC Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbic_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbic_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vbic_s8 (int8x8_t a, int8x8_t b)
    A32: VBIC Dd, Dn, Dm
    A64: BIC Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbic_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbic_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vbic_u16 (uint16x4_t a, uint16x4_t b)
    A32: VBIC Dd, Dn, Dm
    A64: BIC Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbic_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbic_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vbic_u32 (uint32x2_t a, uint32x2_t b)
    A32: VBIC Dd, Dn, Dm
    A64: BIC Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbic_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbic_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vbic_u64 (uint64x1_t a, uint64x1_t b)
    A32: VBIC Dd, Dn, Dm
    A64: BIC Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbic_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbic_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vbic_u8 (uint8x8_t a, uint8x8_t b)
    A32: VBIC Dd, Dn, Dm
    A64: BIC Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbic_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbic_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbicq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vbicq_f32 (float32x4_t a, float32x4_t b)
    A32: VBIC Qd, Qn, Qm
    A64: BIC Vd.16B, Vn.16B, Vm.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vbicq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbicq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vbicq_f64 (float64x2_t a, float64x2_t b)
    A32: VBIC Qd, Qn, Qm
    A64: BIC Vd.16B, Vn.16B, Vm.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vbicq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbicq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vbicq_s16 (int16x8_t a, int16x8_t b)
    A32: VBIC Qd, Qn, Qm
    A64: BIC Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbicq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbicq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vbicq_s32 (int32x4_t a, int32x4_t b)
    A32: VBIC Qd, Qn, Qm
    A64: BIC Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbicq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbicq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vbicq_s64 (int64x2_t a, int64x2_t b)
    A32: VBIC Qd, Qn, Qm
    A64: BIC Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbicq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbicq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vbicq_s8 (int8x16_t a, int8x16_t b)
    A32: VBIC Qd, Qn, Qm
    A64: BIC Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbicq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbicq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vbicq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VBIC Qd, Qn, Qm
    A64: BIC Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbicq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbicq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vbicq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VBIC Qd, Qn, Qm
    A64: BIC Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbicq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbicq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vbicq_u64 (uint64x2_t a, uint64x2_t b)
    A32: VBIC Qd, Qn, Qm
    A64: BIC Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbicq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbicq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vbicq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VBIC Qd, Qn, Qm
    A64: BIC Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbicq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbicq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbsl_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vbsl_f32 (uint32x2_t a, float32x2_t b, float32x2_t c)
    A32: VBSL Dd, Dn, Dm
    A64: BSL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbsl_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbsl_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vbsl_f64 (uint64x1_t a, float64x1_t b, float64x1_t c)
    A32: VBSL Dd, Dn, Dm
    A64: BSL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbsl_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbsl_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vbsl_s16 (uint16x4_t a, int16x4_t b, int16x4_t c)
    A32: VBSL Dd, Dn, Dm
    A64: BSL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbsl_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbsl_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vbsl_s32 (uint32x2_t a, int32x2_t b, int32x2_t c)
    A32: VBSL Dd, Dn, Dm
    A64: BSL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbsl_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbsl_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vbsl_s64 (uint64x1_t a, int64x1_t b, int64x1_t c)
    A32: VBSL Dd, Dn, Dm
    A64: BSL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbsl_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbsl_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vbsl_s8 (uint8x8_t a, int8x8_t b, int8x8_t c)
    A32: VBSL Dd, Dn, Dm
    A64: BSL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbsl_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbsl_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vbsl_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
    A32: VBSL Dd, Dn, Dm
    A64: BSL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbsl_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbsl_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vbsl_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
    A32: VBSL Dd, Dn, Dm
    A64: BSL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbsl_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbsl_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vbsl_u64 (uint64x1_t a, uint64x1_t b, uint64x1_t c)
    A32: VBSL Dd, Dn, Dm
    A64: BSL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbsl_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbsl_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vbsl_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
    A32: VBSL Dd, Dn, Dm
    A64: BSL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vbsl_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbsl_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbslq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vbslq_f32 (uint32x4_t a, float32x4_t b, float32x4_t c)
    A32: VBSL Qd, Qn, Qm
    A64: BSL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbslq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbslq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vbslq_f64 (uint64x2_t a, float64x2_t b, float64x2_t c)
    A32: VBSL Qd, Qn, Qm
    A64: BSL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbslq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbslq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vbslq_s16 (uint16x8_t a, int16x8_t b, int16x8_t c)
    A32: VBSL Qd, Qn, Qm
    A64: BSL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbslq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbslq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vbslq_s32 (uint32x4_t a, int32x4_t b, int32x4_t c)
    A32: VBSL Qd, Qn, Qm
    A64: BSL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbslq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbslq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vbslq_s64 (uint64x2_t a, int64x2_t b, int64x2_t c)
    A32: VBSL Qd, Qn, Qm
    A64: BSL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbslq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbslq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vbslq_s8 (uint8x16_t a, int8x16_t b, int8x16_t c)
    A32: VBSL Qd, Qn, Qm
    A64: BSL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbslq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbslq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vbslq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
    A32: VBSL Qd, Qn, Qm
    A64: BSL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbslq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbslq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vbslq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
    A32: VBSL Qd, Qn, Qm
    A64: BSL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbslq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbslq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vbslq_u64 (uint64x2_t a, uint64x2_t b, uint64x2_t c)
    A32: VBSL Qd, Qn, Qm
    A64: BSL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbslq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vbslq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vbslq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
    A32: VBSL Qd, Qn, Qm
    A64: BSL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vbslq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vbslq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcage_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcage_f32 (float32x2_t a, float32x2_t b)
    A32: VACGE.F32 Dd, Dn, Dm
    A64: FACGE Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcage_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcage_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcageq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcageq_f32 (float32x4_t a, float32x4_t b)
    A32: VACGE.F32 Qd, Qn, Qm
    A64: FACGE Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcageq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcageq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcagt_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcagt_f32 (float32x2_t a, float32x2_t b)
    A32: VACGT.F32 Dd, Dn, Dm
    A64: FACGT Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcagt_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagt_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcagtq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcagtq_f32 (float32x4_t a, float32x4_t b)
    A32: VACGT.F32 Qd, Qn, Qm
    A64: FACGT Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcagtq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcagtq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcale_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcale_f32 (float32x2_t a, float32x2_t b)
    A32: VACLE.F32 Dd, Dn, Dm
    A64: FACGE Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcale_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcale_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcaleq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcaleq_f32 (float32x4_t a, float32x4_t b)
    A32: VACLE.F32 Qd, Qn, Qm
    A64: FACGE Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcaleq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaleq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcalt_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcalt_f32 (float32x2_t a, float32x2_t b)
    A32: VACLT.F32 Dd, Dn, Dm
    A64: FACGT Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcalt_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcalt_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcaltq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcaltq_f32 (float32x4_t a, float32x4_t b)
    A32: VACLT.F32 Qd, Qn, Qm
    A64: FACGT Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcaltq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcaltq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vceq_f32 (float32x2_t a, float32x2_t b)
    A32: VCEQ.F32 Dd, Dn, Dm
    A64: FCMEQ Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vceq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vceq_s16 (int16x4_t a, int16x4_t b)
    A32: VCEQ.I16 Dd, Dn, Dm
    A64: CMEQ Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vceq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vceq_s32 (int32x2_t a, int32x2_t b)
    A32: VCEQ.I32 Dd, Dn, Dm
    A64: CMEQ Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vceq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vceq_s8 (int8x8_t a, int8x8_t b)
    A32: VCEQ.I8 Dd, Dn, Dm
    A64: CMEQ Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vceq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vceq_u16 (uint16x4_t a, uint16x4_t b)
    A32: VCEQ.I16 Dd, Dn, Dm
    A64: CMEQ Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vceq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vceq_u32 (uint32x2_t a, uint32x2_t b)
    A32: VCEQ.I32 Dd, Dn, Dm
    A64: CMEQ Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vceq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vceq_u8 (uint8x8_t a, uint8x8_t b)
    A32: VCEQ.I8 Dd, Dn, Dm
    A64: CMEQ Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vceq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceqq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vceqq_f32 (float32x4_t a, float32x4_t b)
    A32: VCEQ.F32 Qd, Qn, Qm
    A64: FCMEQ Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vceqq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceqq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vceqq_s16 (int16x8_t a, int16x8_t b)
    A32: VCEQ.I16 Qd, Qn, Qm
    A64: CMEQ Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vceqq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceqq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vceqq_s32 (int32x4_t a, int32x4_t b)
    A32: VCEQ.I32 Qd, Qn, Qm
    A64: CMEQ Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vceqq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceqq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vceqq_s8 (int8x16_t a, int8x16_t b)
    A32: VCEQ.I8 Qd, Qn, Qm
    A64: CMEQ Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vceqq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceqq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vceqq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VCEQ.I16 Qd, Qn, Qm
    A64: CMEQ Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vceqq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceqq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vceqq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VCEQ.I32 Qd, Qn, Qm
    A64: CMEQ Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vceqq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vceqq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vceqq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VCEQ.I8 Qd, Qn, Qm
    A64: CMEQ Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vceqq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vceqq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcge_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcge_f32 (float32x2_t a, float32x2_t b)
    A32: VCGE.F32 Dd, Dn, Dm
    A64: FCMGE Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcge_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcge_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vcge_s16 (int16x4_t a, int16x4_t b)
    A32: VCGE.S16 Dd, Dn, Dm
    A64: CMGE Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vcge_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcge_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcge_s32 (int32x2_t a, int32x2_t b)
    A32: VCGE.S32 Dd, Dn, Dm
    A64: CMGE Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcge_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcge_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vcge_s8 (int8x8_t a, int8x8_t b)
    A32: VCGE.S8 Dd, Dn, Dm
    A64: CMGE Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vcge_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcge_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vcge_u16 (uint16x4_t a, uint16x4_t b)
    A32: VCGE.U16 Dd, Dn, Dm
    A64: CMHS Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vcge_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcge_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcge_u32 (uint32x2_t a, uint32x2_t b)
    A32: VCGE.U32 Dd, Dn, Dm
    A64: CMHS Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcge_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcge_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vcge_u8 (uint8x8_t a, uint8x8_t b)
    A32: VCGE.U8 Dd, Dn, Dm
    A64: CMHS Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vcge_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcge_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgeq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcgeq_f32 (float32x4_t a, float32x4_t b)
    A32: VCGE.F32 Qd, Qn, Qm
    A64: FCMGE Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcgeq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgeq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vcgeq_s16 (int16x8_t a, int16x8_t b)
    A32: VCGE.S16 Qd, Qn, Qm
    A64: CMGE Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vcgeq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgeq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcgeq_s32 (int32x4_t a, int32x4_t b)
    A32: VCGE.S32 Qd, Qn, Qm
    A64: CMGE Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcgeq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgeq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vcgeq_s8 (int8x16_t a, int8x16_t b)
    A32: VCGE.S8 Qd, Qn, Qm
    A64: CMGE Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vcgeq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgeq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vcgeq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VCGE.U16 Qd, Qn, Qm
    A64: CMHS Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vcgeq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgeq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcgeq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VCGE.U32 Qd, Qn, Qm
    A64: CMHS Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcgeq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgeq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vcgeq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VCGE.U8 Qd, Qn, Qm
    A64: CMHS Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vcgeq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgeq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgt_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcgt_f32 (float32x2_t a, float32x2_t b)
    A32: VCGT.F32 Dd, Dn, Dm
    A64: FCMGT Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcgt_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgt_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vcgt_s16 (int16x4_t a, int16x4_t b)
    A32: VCGT.S16 Dd, Dn, Dm
    A64: CMGT Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vcgt_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgt_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcgt_s32 (int32x2_t a, int32x2_t b)
    A32: VCGT.S32 Dd, Dn, Dm
    A64: CMGT Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcgt_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgt_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vcgt_s8 (int8x8_t a, int8x8_t b)
    A32: VCGT.S8 Dd, Dn, Dm
    A64: CMGT Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vcgt_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgt_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vcgt_u16 (uint16x4_t a, uint16x4_t b)
    A32: VCGT.U16 Dd, Dn, Dm
    A64: CMHI Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vcgt_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgt_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcgt_u32 (uint32x2_t a, uint32x2_t b)
    A32: VCGT.U32 Dd, Dn, Dm
    A64: CMHI Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcgt_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgt_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vcgt_u8 (uint8x8_t a, uint8x8_t b)
    A32: VCGT.U8 Dd, Dn, Dm
    A64: CMHI Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vcgt_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgt_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgtq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcgtq_f32 (float32x4_t a, float32x4_t b)
    A32: VCGT.F32 Qd, Qn, Qm
    A64: FCMGT Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcgtq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgtq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vcgtq_s16 (int16x8_t a, int16x8_t b)
    A32: VCGT.S16 Qd, Qn, Qm
    A64: CMGT Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vcgtq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgtq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcgtq_s32 (int32x4_t a, int32x4_t b)
    A32: VCGT.S32 Qd, Qn, Qm
    A64: CMGT Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcgtq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgtq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vcgtq_s8 (int8x16_t a, int8x16_t b)
    A32: VCGT.S8 Qd, Qn, Qm
    A64: CMGT Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vcgtq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgtq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vcgtq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VCGT.U16 Qd, Qn, Qm
    A64: CMHI Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vcgtq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgtq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcgtq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VCGT.U32 Qd, Qn, Qm
    A64: CMHI Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcgtq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcgtq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vcgtq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VCGT.U8 Qd, Qn, Qm
    A64: CMHI Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vcgtq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcgtq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcle_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcle_f32 (float32x2_t a, float32x2_t b)
    A32: VCLE.F32 Dd, Dn, Dm
    A64: FCMGE Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcle_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcle_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vcle_s16 (int16x4_t a, int16x4_t b)
    A32: VCLE.S16 Dd, Dn, Dm
    A64: CMGE Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vcle_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcle_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcle_s32 (int32x2_t a, int32x2_t b)
    A32: VCLE.S32 Dd, Dn, Dm
    A64: CMGE Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcle_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcle_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vcle_s8 (int8x8_t a, int8x8_t b)
    A32: VCLE.S8 Dd, Dn, Dm
    A64: CMGE Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vcle_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcle_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vcle_u16 (uint16x4_t a, uint16x4_t b)
    A32: VCLE.U16 Dd, Dn, Dm
    A64: CMHS Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vcle_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcle_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcle_u32 (uint32x2_t a, uint32x2_t b)
    A32: VCLE.U32 Dd, Dn, Dm
    A64: CMHS Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vcle_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcle_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vcle_u8 (uint8x8_t a, uint8x8_t b)
    A32: VCLE.U8 Dd, Dn, Dm
    A64: CMHS Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vcle_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcle_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcleq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcleq_f32 (float32x4_t a, float32x4_t b)
    A32: VCLE.F32 Qd, Qn, Qm
    A64: FCMGE Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcleq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcleq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vcleq_s16 (int16x8_t a, int16x8_t b)
    A32: VCLE.S16 Qd, Qn, Qm
    A64: CMGE Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vcleq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcleq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcleq_s32 (int32x4_t a, int32x4_t b)
    A32: VCLE.S32 Qd, Qn, Qm
    A64: CMGE Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcleq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcleq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vcleq_s8 (int8x16_t a, int8x16_t b)
    A32: VCLE.S8 Qd, Qn, Qm
    A64: CMGE Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vcleq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcleq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vcleq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VCLE.U16 Qd, Qn, Qm
    A64: CMHS Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vcleq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcleq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcleq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VCLE.U32 Qd, Qn, Qm
    A64: CMHS Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcleq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcleq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vcleq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VCLE.U8 Qd, Qn, Qm
    A64: CMHS Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vcleq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcleq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcls_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vcls_s16 (int16x4_t a)
    A32: VCLS.S16 Dd, Dm
    A64: CLS Vd.4H, Vn.4H
    
    
    Instruction Documentation: [vcls_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcls_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vcls_s32 (int32x2_t a)
    A32: VCLS.S32 Dd, Dm
    A64: CLS Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcls_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcls_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vcls_s8 (int8x8_t a)
    A32: VCLS.S8 Dd, Dm
    A64: CLS Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vcls_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcls_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclsq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vclsq_s16 (int16x8_t a)
    A32: VCLS.S16 Qd, Qm
    A64: CLS Vd.8H, Vn.8H
    
    
    Instruction Documentation: [vclsq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclsq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vclsq_s32 (int32x4_t a)
    A32: VCLS.S32 Qd, Qm
    A64: CLS Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vclsq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclsq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vclsq_s8 (int8x16_t a)
    A32: VCLS.S8 Qd, Qm
    A64: CLS Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vclsq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclsq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclt_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vclt_f32 (float32x2_t a, float32x2_t b)
    A32: VCLT.F32 Dd, Dn, Dm
    A64: FCMGT Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vclt_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclt_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vclt_s16 (int16x4_t a, int16x4_t b)
    A32: VCLT.S16 Dd, Dn, Dm
    A64: CMGT Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vclt_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclt_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vclt_s32 (int32x2_t a, int32x2_t b)
    A32: VCLT.S32 Dd, Dn, Dm
    A64: CMGT Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vclt_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclt_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vclt_s8 (int8x8_t a, int8x8_t b)
    A32: VCLT.S8 Dd, Dn, Dm
    A64: CMGT Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vclt_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclt_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vclt_u16 (uint16x4_t a, uint16x4_t b)
    A32: VCLT.U16 Dd, Dn, Dm
    A64: CMHI Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vclt_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclt_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vclt_u32 (uint32x2_t a, uint32x2_t b)
    A32: VCLT.U32 Dd, Dn, Dm
    A64: CMHI Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vclt_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclt_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vclt_u8 (uint8x8_t a, uint8x8_t b)
    A32: VCLT.U8 Dd, Dn, Dm
    A64: CMHI Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vclt_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclt_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcltq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcltq_f32 (float32x4_t a, float32x4_t b)
    A32: VCLT.F32 Qd, Qn, Qm
    A64: FCMGT Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcltq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcltq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vcltq_s16 (int16x8_t a, int16x8_t b)
    A32: VCLT.S16 Qd, Qn, Qm
    A64: CMGT Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vcltq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcltq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcltq_s32 (int32x4_t a, int32x4_t b)
    A32: VCLT.S32 Qd, Qn, Qm
    A64: CMGT Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcltq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcltq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vcltq_s8 (int8x16_t a, int8x16_t b)
    A32: VCLT.S8 Qd, Qn, Qm
    A64: CMGT Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vcltq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcltq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vcltq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VCLT.U16 Qd, Qn, Qm
    A64: CMHI Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vcltq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcltq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcltq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VCLT.U32 Qd, Qn, Qm
    A64: CMHI Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vcltq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcltq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vcltq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VCLT.U8 Qd, Qn, Qm
    A64: CMHI Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vcltq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcltq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclz_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vclz_s16 (int16x4_t a)
    A32: VCLZ.I16 Dd, Dm
    A64: CLZ Vd.4H, Vn.4H
    
    
    Instruction Documentation: [vclz_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclz_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vclz_s32 (int32x2_t a)
    A32: VCLZ.I32 Dd, Dm
    A64: CLZ Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vclz_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclz_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vclz_s8 (int8x8_t a)
    A32: VCLZ.I8 Dd, Dm
    A64: CLZ Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vclz_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclz_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vclz_u16 (uint16x4_t a)
    A32: VCLZ.I16 Dd, Dm
    A64: CLZ Vd.4H, Vn.4H
    
    
    Instruction Documentation: [vclz_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclz_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vclz_u32 (uint32x2_t a)
    A32: VCLZ.I32 Dd, Dm
    A64: CLZ Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vclz_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclz_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vclz_u8 (uint8x8_t a)
    A32: VCLZ.I8 Dd, Dm
    A64: CLZ Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vclz_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclz_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclzq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vclzq_s16 (int16x8_t a)
    A32: VCLZ.I16 Qd, Qm
    A64: CLZ Vd.8H, Vn.8H
    
    
    Instruction Documentation: [vclzq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclzq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vclzq_s32 (int32x4_t a)
    A32: VCLZ.I32 Qd, Qm
    A64: CLZ Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vclzq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclzq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vclzq_s8 (int8x16_t a)
    A32: VCLZ.I8 Qd, Qm
    A64: CLZ Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vclzq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclzq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vclzq_u16 (uint16x8_t a)
    A32: VCLZ.I16 Qd, Qm
    A64: CLZ Vd.8H, Vn.8H
    
    
    Instruction Documentation: [vclzq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclzq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vclzq_u32 (uint32x4_t a)
    A32: VCLZ.I32 Qd, Qm
    A64: CLZ Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vclzq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vclzq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vclzq_u8 (uint8x16_t a)
    A32: VCLZ.I8 Qd, Qm
    A64: CLZ Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vclzq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vclzq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcnt_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vcnt_s8 (int8x8_t a)
    A32: VCNT.I8 Dd, Dm
    A64: CNT Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vcnt_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcnt_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vcnt_u8 (uint8x8_t a)
    A32: VCNT.I8 Dd, Dm
    A64: CNT Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vcnt_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcnt_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcntq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vcntq_s8 (int8x16_t a)
    A32: VCNT.I8 Qd, Qm
    A64: CNT Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vcntq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcntq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vcntq_u8 (uint8x16_t a)
    A32: VCNT.I8 Qd, Qm
    A64: CNT Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vcntq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcntq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_f32_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vcvt_f32_s32 (int32x2_t a)
    A32: VCVT.F32.S32 Dd, Dm
    A64: SCVTF Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvt_f32_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_f32_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vcvt_f32_u32 (uint32x2_t a)
    A32: VCVT.F32.U32 Dd, Dm
    A64: UCVTF Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvt_f32_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_f32_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vcvt_s32_f32 (float32x2_t a)
    A32: VCVT.S32.F32 Dd, Dm
    A64: FCVTZS Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvt_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvt_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcvt_u32_f32 (float32x2_t a)
    A32: VCVT.U32.F32 Dd, Dm
    A64: FCVTZU Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvt_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvt_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvta_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vcvta_s32_f32 (float32x2_t a)
    A32: VCVTA.S32.F32 Dd, Dm
    A64: FCVTAS Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvta_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvta_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcvta_u32_f32 (float32x2_t a)
    A32: VCVTA.U32.F32 Dd, Dm
    A64: FCVTAU Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvta_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvta_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtaq_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vcvtaq_s32_f32 (float32x4_t a)
    A32: VCVTA.S32.F32 Qd, Qm
    A64: FCVTAS Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtaq_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtaq_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcvtaq_u32_f32 (float32x4_t a)
    A32: VCVTA.U32.F32 Qd, Qm
    A64: FCVTAU Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtaq_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtaq_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtas_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vcvtas_s32_f32 (float32_t a)
    A32: VCVTA.S32.F32 Sd, Sm
    A64: FCVTAS Sd, Sn
    
    
    Instruction Documentation: [vcvtas_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtas_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcvtas_u32_f32 (float32_t a)
    A32: VCVTA.U32.F32 Sd, Sm
    A64: FCVTAU Sd, Sn
    
    
    Instruction Documentation: [vcvtas_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtas_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtm_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vcvtm_s32_f32 (float32x2_t a)
    A32: VCVTM.S32.F32 Dd, Dm
    A64: FCVTMS Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvtm_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtm_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcvtm_u32_f32 (float32x2_t a)
    A32: VCVTM.U32.F32 Dd, Dm
    A64: FCVTMU Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvtm_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtm_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtmq_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vcvtmq_s32_f32 (float32x4_t a)
    A32: VCVTM.S32.F32 Qd, Qm
    A64: FCVTMS Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtmq_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtmq_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcvtmq_u32_f32 (float32x4_t a)
    A32: VCVTM.U32.F32 Qd, Qm
    A64: FCVTMU Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtmq_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtmq_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtms_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vcvtms_s32_f32 (float32_t a)
    A32: VCVTM.S32.F32 Sd, Sm
    A64: FCVTMS Sd, Sn
    
    
    Instruction Documentation: [vcvtms_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtms_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcvtms_u32_f32 (float32_t a)
    A32: VCVTM.U32.F32 Sd, Sm
    A64: FCVTMU Sd, Sn
    
    
    Instruction Documentation: [vcvtms_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtms_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtn_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vcvtn_s32_f32 (float32x2_t a)
    A32: VCVTN.S32.F32 Dd, Dm
    A64: FCVTNS Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvtn_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtn_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcvtn_u32_f32 (float32x2_t a)
    A32: VCVTN.U32.F32 Dd, Dm
    A64: FCVTNU Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvtn_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtn_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtnq_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vcvtnq_s32_f32 (float32x4_t a)
    A32: VCVTN.S32.F32 Qd, Qm
    A64: FCVTNS Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtnq_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtnq_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcvtnq_u32_f32 (float32x4_t a)
    A32: VCVTN.U32.F32 Qd, Qm
    A64: FCVTNU Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtnq_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtnq_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtns_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vcvtns_s32_f32 (float32_t a)
    A32: VCVTN.S32.F32 Sd, Sm
    A64: FCVTNS Sd, Sn
    
    
    Instruction Documentation: [vcvtns_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtns_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcvtns_u32_f32 (float32_t a)
    A32: VCVTN.U32.F32 Sd, Sm
    A64: FCVTNU Sd, Sn
    
    
    Instruction Documentation: [vcvtns_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtns_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtp_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vcvtp_s32_f32 (float32x2_t a)
    A32: VCVTP.S32.F32 Dd, Dm
    A64: FCVTPS Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvtp_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtp_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vcvtp_u32_f32 (float32x2_t a)
    A32: VCVTP.U32.F32 Dd, Dm
    A64: FCVTPU Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vcvtp_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtp_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtpq_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vcvtpq_s32_f32 (float32x4_t a)
    A32: VCVTP.S32.F32 Qd, Qm
    A64: FCVTPS Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtpq_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtpq_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcvtpq_u32_f32 (float32x4_t a)
    A32: VCVTP.U32.F32 Qd, Qm
    A64: FCVTPU Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtpq_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtpq_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtps_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vcvtps_s32_f32 (float32_t a)
    A32: VCVTP.S32.F32 Sd, Sm
    A64: FCVTPS Sd, Sn
    
    
    Instruction Documentation: [vcvtps_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtps_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcvtps_u32_f32 (float32_t a)
    A32: VCVTP.U32.F32 Sd, Sm
    A64: FCVTPU Sd, Sn
    
    
    Instruction Documentation: [vcvtps_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtps_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtq_f32_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vcvtq_f32_s32 (int32x4_t a)
    A32: VCVT.F32.S32 Qd, Qm
    A64: SCVTF Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtq_f32_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtq_f32_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vcvtq_f32_u32 (uint32x4_t a)
    A32: VCVT.F32.U32 Qd, Qm
    A64: UCVTF Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtq_f32_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_f32_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtq_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vcvtq_s32_f32 (float32x4_t a)
    A32: VCVT.S32.F32 Qd, Qm
    A64: FCVTZS Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtq_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvtq_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vcvtq_u32_f32 (float32x4_t a)
    A32: VCVT.U32.F32 Qd, Qm
    A64: FCVTZU Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vcvtq_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvtq_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvts_f32_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vcvts_f32_s32 (int32_t a)
    A32: VCVT.F32.S32 Sd, Sm
    A64: SCVTF Sd, Sn
    
    
    Instruction Documentation: [vcvts_f32_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvts_f32_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vcvts_f32_u32 (uint32_t a)
    A32: VCVT.F32.U32 Sd, Sm
    A64: UCVTF Sd, Sn
    
    
    Instruction Documentation: [vcvts_f32_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_f32_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvts_s32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vcvts_s32_f32 (float32_t a)
    A32: VCVT.S32.F32 Sd, Sm
    A64: FCVTZS Sd, Sn
    
    
    Instruction Documentation: [vcvts_s32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_s32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vcvts_u32_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vcvts_u32_f32 (float32_t a)
    A32: VCVT.U32.F32 Sd, Sm
    A64: FCVTZU Sd, Sn
    
    
    Instruction Documentation: [vcvts_u32_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vcvts_u32_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdiv_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vdiv_f64 (float64x1_t a, float64x1_t b)
    A32: VDIV.F64 Dd, Dn, Dm
    A64: FDIV Dd, Dn, Dm
    
    
    Instruction Documentation: [vdiv_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdiv_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdivs_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vdivs_f32 (float32_t a, float32_t b)
    A32: VDIV.F32 Sd, Sn, Sm
    A64: FDIV Sd, Sn, Sm The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vdivs_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdivs_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vdup_lane_f32 (float32x2_t vec, const int lane)
    A32: VDUP.32 Dd, Dm[index]
    A64: DUP Vd.2S, Vn.S[index]
    
    
    Instruction Documentation: [vdup_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vdup_lane_s16 (int16x4_t vec, const int lane)
    A32: VDUP.16 Dd, Dm[index]
    A64: DUP Vd.4H, Vn.H[index]
    
    
    Instruction Documentation: [vdup_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vdup_lane_s32 (int32x2_t vec, const int lane)
    A32: VDUP.32 Dd, Dm[index]
    A64: DUP Vd.2S, Vn.S[index]
    
    
    Instruction Documentation: [vdup_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vdup_lane_s8 (int8x8_t vec, const int lane)
    A32: VDUP.8 Dd, Dm[index]
    A64: DUP Vd.8B, Vn.B[index]
    
    
    Instruction Documentation: [vdup_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vdup_lane_u16 (uint16x4_t vec, const int lane)
    A32: VDUP.16 Dd, Dm[index]
    A64: DUP Vd.4H, Vn.H[index]
    
    
    Instruction Documentation: [vdup_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vdup_lane_u32 (uint32x2_t vec, const int lane)
    A32: VDUP.32 Dd, Dm[index]
    A64: DUP Vd.2S, Vn.S[index]
    
    
    Instruction Documentation: [vdup_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vdup_lane_u8 (uint8x8_t vec, const int lane)
    A32: VDUP.8 Dd, Dm[index]
    A64: DUP Vd.8B, Vn.B[index]
    
    
    Instruction Documentation: [vdup_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_lane_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vdup_laneq_f32 (float32x4_t vec, const int lane)
    A32: VDUP.32 Dd, Dm[index]
    A64: DUP Vd.2S, Vn.S[index]
    
    
    Instruction Documentation: [vdup_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vdup_laneq_s16 (int16x8_t vec, const int lane)
    A32: VDUP.16 Dd, Dm[index]
    A64: DUP Vd.4H, Vn.H[index]
    
    
    Instruction Documentation: [vdup_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vdup_laneq_s32 (int32x4_t vec, const int lane)
    A32: VDUP.32 Dd, Dm[index]
    A64: DUP Vd.2S, Vn.S[index]
    
    
    Instruction Documentation: [vdup_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_laneq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vdup_laneq_s8 (int8x16_t vec, const int lane)
    A32: VDUP.8 Dd, Dm[index]
    A64: DUP Vd.8B, Vn.B[index]
    
    
    Instruction Documentation: [vdup_laneq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vdup_laneq_u16 (uint16x8_t vec, const int lane)
    A32: VDUP.16 Dd, Dm[index]
    A64: DUP Vd.4H, Vn.H[index]
    
    
    Instruction Documentation: [vdup_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vdup_laneq_u32 (uint32x4_t vec, const int lane)
    A32: VDUP.32 Dd, Dm[index]
    A64: DUP Vd.2S, Vn.S[index]
    
    
    Instruction Documentation: [vdup_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_laneq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vdup_laneq_u8 (uint8x16_t vec, const int lane)
    A32: VDUP.8 Dd, Dm[index]
    A64: DUP Vd.8B, Vn.B[index]
    
    
    Instruction Documentation: [vdup_laneq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_laneq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_n_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vdup_n_f32 (float32_t value)
    A32: VDUP Dd, Dm[0]
    A64: DUP Vd.2S, Vn.S[0]
    
    
    Instruction Documentation: [vdup_n_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vdup_n_s16 (int16_t value)
    A32: VDUP.16 Dd, Rt
    A64: DUP Vd.4H, Rn
    
    
    Instruction Documentation: [vdup_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vdup_n_s32 (int32_t value)
    A32: VDUP.32 Dd, Rt
    A64: DUP Vd.2S, Rn
    
    
    Instruction Documentation: [vdup_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vdup_n_s8 (int8_t value)
    A32: VDUP.8 Dd, Rt
    A64: DUP Vd.8B, Rn
    
    
    Instruction Documentation: [vdup_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vdup_n_u16 (uint16_t value)
    A32: VDUP.16 Dd, Rt
    A64: DUP Vd.4H, Rn
    
    
    Instruction Documentation: [vdup_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vdup_n_u32 (uint32_t value)
    A32: VDUP.32 Dd, Rt
    A64: DUP Vd.2S, Rn
    
    
    Instruction Documentation: [vdup_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdup_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vdup_n_u8 (uint8_t value)
    A32: VDUP.8 Dd, Rt
    A64: DUP Vd.8B, Rn
    
    
    Instruction Documentation: [vdup_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdup_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vdupq_lane_f32 (float32x2_t vec, const int lane)
    A32: VDUP.32 Qd, Dm[index]
    A64: DUP Vd.4S, Vn.S[index]
    
    
    Instruction Documentation: [vdupq_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vdupq_lane_s16 (int16x8_t vec, const int lane)
    A32: VDUP.16 Qd, Dm[index]
    A64: DUP Vd.8H, Vn.H[index]
    
    
    Instruction Documentation: [vdupq_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vdupq_lane_s32 (int32x4_t vec, const int lane)
    A32: VDUP.32 Qd, Dm[index]
    A64: DUP Vd.4S, Vn.S[index]
    
    
    Instruction Documentation: [vdupq_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vdupq_lane_s8 (int8x16_t vec, const int lane)
    A32: VDUP.8 Qd, Dm[index]
    A64: DUP Vd.16B, Vn.B[index]
    
    
    Instruction Documentation: [vdupq_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vdupq_lane_u16 (uint16x8_t vec, const int lane)
    A32: VDUP.16 Qd, Dm[index]
    A64: DUP Vd.8H, Vn.H[index]
    
    
    Instruction Documentation: [vdupq_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vdupq_lane_u32 (uint32x4_t vec, const int lane)
    A32: VDUP.32 Qd, Dm[index]
    A64: DUP Vd.4S, Vn.S[index]
    
    
    Instruction Documentation: [vdupq_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vdupq_lane_u8 (uint8x16_t vec, const int lane)
    A32: VDUP.8 Qd, Dm[index]
    A64: DUP Vd.16B, Vn.B[index]
    
    
    Instruction Documentation: [vdupq_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_lane_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_n_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vdupq_n_f32 (float32_t value)
    A32: VDUP Qd, Dm[0]
    A64: DUP Vd.4S, Vn.S[0]
    
    
    Instruction Documentation: [vdupq_n_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vdupq_n_s16 (int16_t value)
    A32: VDUP.16 Qd, Rt
    A64: DUP Vd.8H, Rn
    
    
    Instruction Documentation: [vdupq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vdupq_n_s32 (int32_t value)
    A32: VDUP.32 Qd, Rt
    A64: DUP Vd.4S, Rn
    
    
    Instruction Documentation: [vdupq_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vdupq_n_s8 (int8_t value)
    A32: VDUP.8 Qd, Rt
    A64: DUP Vd.16B, Rn
    
    
    Instruction Documentation: [vdupq_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vdupq_n_u16 (uint16_t value)
    A32: VDUP.16 Qd, Rt
    A64: DUP Vd.8H, Rn
    
    
    Instruction Documentation: [vdupq_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vdupq_n_u32 (uint32_t value)
    A32: VDUP.32 Qd, Rt
    A64: DUP Vd.4S, Rn
    
    
    Instruction Documentation: [vdupq_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vdupq_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vdupq_n_u8 (uint8_t value)
    A32: VDUP.8 Qd, Rt
    A64: DUP Vd.16B, Rn
    
    
    Instruction Documentation: [vdupq_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vdupq_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veor_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t veor_f32 (float32x2_t a, float32x2_t b)
    A32: VEOR Dd, Dn, Dm
    A64: EOR Vd.8B, Vn.8B, Vm.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [veor_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veor_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t veor_f64 (float64x1_t a, float64x1_t b)
    A32: VEOR Dd, Dn, Dm
    A64: EOR Vd.8B, Vn.8B, Vm.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [veor_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veor_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t veor_s16 (int16x4_t a, int16x4_t b)
    A32: VEOR Dd, Dn, Dm
    A64: EOR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [veor_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veor_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t veor_s32 (int32x2_t a, int32x2_t b)
    A32: VEOR Dd, Dn, Dm
    A64: EOR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [veor_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veor_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t veor_s64 (int64x1_t a, int64x1_t b)
    A32: VEOR Dd, Dn, Dm
    A64: EOR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [veor_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veor_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t veor_s8 (int8x8_t a, int8x8_t b)
    A32: VEOR Dd, Dn, Dm
    A64: EOR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [veor_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veor_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t veor_u16 (uint16x4_t a, uint16x4_t b)
    A32: VEOR Dd, Dn, Dm
    A64: EOR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [veor_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veor_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t veor_u32 (uint32x2_t a, uint32x2_t b)
    A32: VEOR Dd, Dn, Dm
    A64: EOR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [veor_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veor_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t veor_u64 (uint64x1_t a, uint64x1_t b)
    A32: VEOR Dd, Dn, Dm
    A64: EOR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [veor_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veor_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t veor_u8 (uint8x8_t a, uint8x8_t b)
    A32: VEOR Dd, Dn, Dm
    A64: EOR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [veor_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/veor_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veorq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t veorq_f32 (float32x4_t a, float32x4_t b)
    A32: VEOR Qd, Qn, Qm
    A64: EOR Vd.16B, Vn.16B, Vm.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [veorq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veorq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t veorq_f64 (float64x2_t a, float64x2_t b)
    A32: VEOR Qd, Qn, Qm
    A64: EOR Vd.16B, Vn.16B, Vm.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [veorq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veorq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t veorq_s16 (int16x8_t a, int16x8_t b)
    A32: VEOR Qd, Qn, Qm
    A64: EOR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [veorq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veorq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t veorq_s32 (int32x4_t a, int32x4_t b)
    A32: VEOR Qd, Qn, Qm
    A64: EOR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [veorq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veorq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t veorq_s64 (int64x2_t a, int64x2_t b)
    A32: VEOR Qd, Qn, Qm
    A64: EOR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [veorq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veorq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t veorq_s8 (int8x16_t a, int8x16_t b)
    A32: VEOR Qd, Qn, Qm
    A64: EOR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [veorq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veorq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t veorq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VEOR Qd, Qn, Qm
    A64: EOR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [veorq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veorq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t veorq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VEOR Qd, Qn, Qm
    A64: EOR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [veorq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veorq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t veorq_u64 (uint64x2_t a, uint64x2_t b)
    A32: VEOR Qd, Qn, Qm
    A64: EOR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [veorq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["veorq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t veorq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VEOR Qd, Qn, Qm
    A64: EOR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [veorq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/veorq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vext_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vext_f32 (float32x2_t a, float32x2_t b, const int n)
    A32: VEXT.8 Dd, Dn, Dm, #(n*4)
    A64: EXT Vd.8B, Vn.8B, Vm.8B, #(n*4)
    
    
    Instruction Documentation: [vext_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vext_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vext_s16 (int16x4_t a, int16x4_t b, const int n)
    A32: VEXT.8 Dd, Dn, Dm, #(n*2)
    A64: EXT Vd.8B, Vn.8B, Vm.8B, #(n*2)
    
    
    Instruction Documentation: [vext_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vext_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vext_s32 (int32x2_t a, int32x2_t b, const int n)
    A32: VEXT.8 Dd, Dn, Dm, #(n*4)
    A64: EXT Vd.8B, Vn.8B, Vm.8B, #(n*4)
    
    
    Instruction Documentation: [vext_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vext_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vext_s8 (uint8x8_t a, uint8x8_t b, const int n)
    A32: VEXT.8 Dd, Dn, Dm, #n
    A64: EXT Vd.8B, Vn.8B, Vm.8B, #n
    
    
    Instruction Documentation: [vext_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vext_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vextq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vextq_f32 (float32x4_t a, float32x4_t b, const int n)
    A32: VEXT.8 Qd, Qn, Qm, #(n*4)
    A64: EXT Vd.16B, Vn.16B, Vm.16B, #(n*4)
    
    
    Instruction Documentation: [vextq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vextq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vextq_f64 (float64x2_t a, float64x2_t b, const int n)
    A32: VEXT.8 Qd, Qn, Qm, #(n*8)
    A64: EXT Vd.16B, Vn.16B, Vm.16B, #(n*8)
    
    
    Instruction Documentation: [vextq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vextq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vextq_s16 (int16x8_t a, int16x8_t b, const int n)
    A32: VEXT.8 Qd, Qn, Qm, #(n*2)
    A64: EXT Vd.16B, Vn.16B, Vm.16B, #(n*2)
    
    
    Instruction Documentation: [vextq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vextq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vextq_s32 (int32x4_t a, int32x4_t b, const int n)
    A32: VEXT.8 Qd, Qn, Qm, #(n*4)
    A64: EXT Vd.16B, Vn.16B, Vm.16B, #(n*4)
    
    
    Instruction Documentation: [vextq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vextq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vextq_s64 (int64x2_t a, int64x2_t b, const int n)
    A32: VEXT.8 Qd, Qn, Qm, #(n*8)
    A64: EXT Vd.16B, Vn.16B, Vm.16B, #(n*8)
    
    
    Instruction Documentation: [vextq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vextq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vextq_s8 (uint8x16_t a, uint8x16_t b, const int n)
    A32: VEXT.8 Qd, Qn, Qm, #n
    A64: EXT Vd.16B, Vn.16B, Vm.16B, #n
    
    
    Instruction Documentation: [vextq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vextq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfma_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vfma_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
    A32: VFMA.F32 Dd, Dn, Dm
    A64: FMLA Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vfma_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfma_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vfma_f64 (float64x1_t a, float64x1_t b, float64x1_t c)
    A32: VFMA.F64 Dd, Dn, Dm
    A64: FMADD Dd, Dn, Dm, Da
    
    
    Instruction Documentation: [vfma_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfma_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmaq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vfmaq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
    A32: VFMA.F32 Qd, Qn, Qm
    A64: FMLA Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vfmaq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmaq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmas_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vfmas_f32 (float32_t a, float32_t b, float32_t c)
    A32: VFMA.F32 Sd, Sn, Sm
    A64: FMADD Sd, Sn, Sm, Sa The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vfmas_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmas_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfms_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vfms_f32 (float32x2_t a, float32x2_t b, float32x2_t c)
    A32: VFMS.F32 Dd, Dn, Dm
    A64: FMLS Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vfms_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfms_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vfms_f64 (float64x1_t a, float64x1_t b, float64x1_t c)
    A32: VFMS.F64 Dd, Dn, Dm
    A64: FMSUB Dd, Dn, Dm, Da
    
    
    Instruction Documentation: [vfms_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfms_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmsq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vfmsq_f32 (float32x4_t a, float32x4_t b, float32x4_t c)
    A32: VFMS.F32 Qd, Qn, Qm
    A64: FMLS Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vfmsq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmsq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfmss_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vfmss_f32 (float32_t a, float32_t b, float32_t c)
    A32: VFMS.F32 Sd, Sn, Sm
    A64: FMSUB Sd, Sn, Sm, Sa The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vfmss_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfmss_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfnma_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vfnma_f64 (float64x1_t a, float64x1_t b, float64x1_t c)
    A32: VFNMA.F64 Dd, Dn, Dm
    A64: FNMADD Dd, Dn, Dm, Da The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vfnma_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfnma_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfnmas_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vfnmas_f32 (float32_t a, float32_t b, float32_t c)
    A32: VFNMA.F32 Sd, Sn, Sm
    A64: FNMADD Sd, Sn, Sm, Sa The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vfnmas_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfnmas_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfnms_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vfnms_f64 (float64x1_t a, float64x1_t b, float64x1_t c)
    A32: VFNMS.F64 Dd, Dn, Dm
    A64: FNMSUB Dd, Dn, Dm, Da The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vfnms_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfnms_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vfnmss_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vfnmss_f32 (float32_t a, float32_t b, float32_t c)
    A32: VFNMS.F32 Sd, Sn, Sm
    A64: FNMSUB Sd, Sn, Sm, Sa The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vfnmss_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vfnmss_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vget_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vget_lane_f32 (float32x2_t v, const int lane)
    A32: VMOV.F32 Sd, Sm
    A64: DUP Sd, Vn.S[lane]
    
    
    Instruction Documentation: [vget_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vget_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vget_lane_s16 (int16x4_t v, const int lane)
    A32: VMOV.S16 Rt, Dn[lane]
    A64: SMOV Wd, Vn.H[lane]
    
    
    Instruction Documentation: [vget_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vget_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vget_lane_s32 (int32x2_t v, const int lane)
    A32: VMOV.32 Rt, Dn[lane]
    A64: SMOV Wd, Vn.S[lane]
    
    
    Instruction Documentation: [vget_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vget_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vget_lane_s8 (int8x8_t v, const int lane)
    A32: VMOV.S8 Rt, Dn[lane]
    A64: SMOV Wd, Vn.B[lane]
    
    
    Instruction Documentation: [vget_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vget_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vget_lane_u16 (uint16x4_t v, const int lane)
    A32: VMOV.U16 Rt, Dn[lane]
    A64: UMOV Wd, Vn.H[lane]
    
    
    Instruction Documentation: [vget_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vget_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vget_lane_u32 (uint32x2_t v, const int lane)
    A32: VMOV.32 Rt, Dn[lane]
    A64: UMOV Wd, Vn.S[lane]
    
    
    Instruction Documentation: [vget_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vget_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vget_lane_u8 (uint8x8_t v, const int lane)
    A32: VMOV.U8 Rt, Dn[lane]
    A64: UMOV Wd, Vn.B[lane]
    
    
    Instruction Documentation: [vget_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vget_lane_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vgetq_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vgetq_lane_f32 (float32x4_t v, const int lane)
    A32: VMOV.F32 Sd, Sm
    A64: DUP Sd, Vn.S[lane]
    
    
    Instruction Documentation: [vgetq_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vgetq_lane_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64_t vgetq_lane_f64 (float64x2_t v, const int lane)
    A32: VMOV.F64 Dd, Dm
    A64: DUP Dd, Vn.D[lane]
    
    
    Instruction Documentation: [vgetq_lane_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vgetq_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16_t vgetq_lane_s16 (int16x8_t v, const int lane)
    A32: VMOV.S16 Rt, Dn[lane]
    A64: SMOV Wd, Vn.H[lane]
    
    
    Instruction Documentation: [vgetq_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vgetq_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32_t vgetq_lane_s32 (int32x4_t v, const int lane)
    A32: VMOV.32 Rt, Dn[lane]
    A64: SMOV Wd, Vn.S[lane]
    
    
    Instruction Documentation: [vgetq_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vgetq_lane_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64_t vgetq_lane_s64 (int64x2_t v, const int lane)
    A32: VMOV Rt, Rt2, Dm
    A64: UMOV Xd, Vn.D[lane]
    
    
    Instruction Documentation: [vgetq_lane_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vgetq_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8_t vgetq_lane_s8 (int8x16_t v, const int lane)
    A32: VMOV.S8 Rt, Dn[lane]
    A64: SMOV Wd, Vn.B[lane]
    
    
    Instruction Documentation: [vgetq_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vgetq_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16_t vgetq_lane_u16 (uint16x8_t v, const int lane)
    A32: VMOV.U16 Rt, Dn[lane]
    A64: UMOV Wd, Vn.H[lane]
    
    
    Instruction Documentation: [vgetq_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vgetq_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32_t vgetq_lane_u32 (uint32x4_t v, const int lane)
    A32: VMOV.32 Rt, Dn[lane]
    A64: UMOV Wd, Vn.S[lane]
    
    
    Instruction Documentation: [vgetq_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vgetq_lane_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64_t vgetq_lane_u64 (uint64x2_t v, const int lane)
    A32: VMOV Rt, Rt2, Dm
    A64: UMOV Xd, Vn.D[lane]
    
    
    Instruction Documentation: [vgetq_lane_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vgetq_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8_t vgetq_lane_u8 (uint8x16_t v, const int lane)
    A32: VMOV.U8 Rt, Dn[lane]
    A64: UMOV Wd, Vn.B[lane]
    
    
    Instruction Documentation: [vgetq_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vgetq_lane_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhadd_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vhadd_s16 (int16x4_t a, int16x4_t b)
    A32: VHADD.S16 Dd, Dn, Dm
    A64: SHADD Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vhadd_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhadd_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vhadd_s32 (int32x2_t a, int32x2_t b)
    A32: VHADD.S32 Dd, Dn, Dm
    A64: SHADD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vhadd_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhadd_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vhadd_s8 (int8x8_t a, int8x8_t b)
    A32: VHADD.S8 Dd, Dn, Dm
    A64: SHADD Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vhadd_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhadd_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vhadd_u16 (uint16x4_t a, uint16x4_t b)
    A32: VHADD.U16 Dd, Dn, Dm
    A64: UHADD Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vhadd_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhadd_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vhadd_u32 (uint32x2_t a, uint32x2_t b)
    A32: VHADD.U32 Dd, Dn, Dm
    A64: UHADD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vhadd_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhadd_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vhadd_u8 (uint8x8_t a, uint8x8_t b)
    A32: VHADD.U8 Dd, Dn, Dm
    A64: UHADD Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vhadd_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhadd_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhaddq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vhaddq_s16 (int16x8_t a, int16x8_t b)
    A32: VHADD.S16 Qd, Qn, Qm
    A64: SHADD Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vhaddq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhaddq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vhaddq_s32 (int32x4_t a, int32x4_t b)
    A32: VHADD.S32 Qd, Qn, Qm
    A64: SHADD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vhaddq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhaddq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vhaddq_s8 (int8x16_t a, int8x16_t b)
    A32: VHADD.S8 Qd, Qn, Qm
    A64: SHADD Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vhaddq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhaddq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vhaddq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VHADD.U16 Qd, Qn, Qm
    A64: UHADD Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vhaddq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhaddq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vhaddq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VHADD.U32 Qd, Qn, Qm
    A64: UHADD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vhaddq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhaddq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vhaddq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VHADD.U8 Qd, Qn, Qm
    A64: UHADD Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vhaddq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhaddq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsub_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vhsub_s16 (int16x4_t a, int16x4_t b)
    A32: VHSUB.S16 Dd, Dn, Dm
    A64: SHSUB Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vhsub_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsub_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vhsub_s32 (int32x2_t a, int32x2_t b)
    A32: VHSUB.S32 Dd, Dn, Dm
    A64: SHSUB Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vhsub_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsub_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vhsub_s8 (int8x8_t a, int8x8_t b)
    A32: VHSUB.S8 Dd, Dn, Dm
    A64: SHSUB Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vhsub_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsub_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vhsub_u16 (uint16x4_t a, uint16x4_t b)
    A32: VHSUB.U16 Dd, Dn, Dm
    A64: UHSUB Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vhsub_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsub_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vhsub_u32 (uint32x2_t a, uint32x2_t b)
    A32: VHSUB.U32 Dd, Dn, Dm
    A64: UHSUB Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vhsub_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsub_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vhsub_u8 (uint8x8_t a, uint8x8_t b)
    A32: VHSUB.U8 Dd, Dn, Dm
    A64: UHSUB Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vhsub_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsub_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsubq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vhsubq_s16 (int16x8_t a, int16x8_t b)
    A32: VHSUB.S16 Qd, Qn, Qm
    A64: SHSUB Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vhsubq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsubq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vhsubq_s32 (int32x4_t a, int32x4_t b)
    A32: VHSUB.S32 Qd, Qn, Qm
    A64: SHSUB Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vhsubq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsubq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vhsubq_s8 (int8x16_t a, int8x16_t b)
    A32: VHSUB.S8 Qd, Qn, Qm
    A64: SHSUB Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vhsubq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsubq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vhsubq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VHSUB.U16 Qd, Qn, Qm
    A64: UHSUB Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vhsubq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsubq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vhsubq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VHSUB.U32 Qd, Qn, Qm
    A64: UHSUB Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vhsubq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vhsubq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vhsubq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VHSUB.U8 Qd, Qn, Qm
    A64: UHSUB Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vhsubq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vhsubq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_dup_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vld1_dup_f32 (float32_t const * ptr)
    A32: VLD1.32 { Dd[] }, [Rn]
    A64: LD1R { Vt.2S }, [Xn]
    
    
    Instruction Documentation: [vld1_dup_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_dup_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vld1_dup_s16 (int16_t const * ptr)
    A32: VLD1.16 { Dd[] }, [Rn]
    A64: LD1R { Vt.4H }, [Xn]
    
    
    Instruction Documentation: [vld1_dup_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_dup_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vld1_dup_s32 (int32_t const * ptr)
    A32: VLD1.32 { Dd[] }, [Rn]
    A64: LD1R { Vt.2S }, [Xn]
    
    
    Instruction Documentation: [vld1_dup_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_dup_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vld1_dup_s8 (int8_t const * ptr)
    A32: VLD1.8 { Dd[] }, [Rn]
    A64: LD1R { Vt.8B }, [Xn]
    
    
    Instruction Documentation: [vld1_dup_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_dup_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vld1_dup_u16 (uint16_t const * ptr)
    A32: VLD1.16 { Dd[] }, [Rn]
    A64: LD1R { Vt.4H }, [Xn]
    
    
    Instruction Documentation: [vld1_dup_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_dup_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vld1_dup_u32 (uint32_t const * ptr)
    A32: VLD1.32 { Dd[] }, [Rn]
    A64: LD1R { Vt.2S }, [Xn]
    
    
    Instruction Documentation: [vld1_dup_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_dup_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vld1_dup_u8 (uint8_t const * ptr)
    A32: VLD1.8 { Dd[] }, [Rn]
    A64: LD1R { Vt.8B }, [Xn]
    
    
    Instruction Documentation: [vld1_dup_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_dup_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vld1_f32 (float32_t const * ptr)
    A32: VLD1.32 Dd, [Rn]
    A64: LD1 Vt.2S, [Xn]
    
    
    Instruction Documentation: [vld1_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vld1_f64 (float64_t const * ptr)
    A32: VLD1.64 Dd, [Rn]
    A64: LD1 Vt.1D, [Xn]
    
    
    Instruction Documentation: [vld1_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vld1_lane_f32 (float32_t const * ptr, float32x2_t src, const int lane)
    A32: VLD1.32 { Dd[index] }, [Rn]
    A64: LD1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vld1_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vld1_lane_s16 (int16_t const * ptr, int16x4_t src, const int lane)
    A32: VLD1.16 { Dd[index] }, [Rn]
    A64: LD1 { Vt.H }[index], [Xn]
    
    
    Instruction Documentation: [vld1_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vld1_lane_s32 (int32_t const * ptr, int32x2_t src, const int lane)
    A32: VLD1.32 { Dd[index] }, [Rn]
    A64: LD1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vld1_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vld1_lane_s8 (int8_t const * ptr, int8x8_t src, const int lane)
    A32: VLD1.8 { Dd[index] }, [Rn]
    A64: LD1 { Vt.B }[index], [Xn]
    
    
    Instruction Documentation: [vld1_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vld1_lane_u16 (uint16_t const * ptr, uint16x4_t src, const int lane)
    A32: VLD1.16 { Dd[index] }, [Rn]
    A64: LD1 { Vt.H }[index], [Xn]
    
    
    Instruction Documentation: [vld1_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vld1_lane_u32 (uint32_t const * ptr, uint32x2_t src, const int lane)
    A32: VLD1.32 { Dd[index] }, [Rn]
    A64: LD1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vld1_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vld1_lane_u8 (uint8_t const * ptr, uint8x8_t src, const int lane)
    A32: VLD1.8 { Dd[index] }, [Rn]
    A64: LD1 { Vt.B }[index], [Xn]
    
    
    Instruction Documentation: [vld1_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_lane_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vld1_s16 (int16_t const * ptr)
    A32: VLD1.16 Dd, [Rn]
    A64: LD1 Vt.4H, [Xn]
    
    
    Instruction Documentation: [vld1_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vld1_s32 (int32_t const * ptr)
    A32: VLD1.32 Dd, [Rn]
    A64: LD1 Vt.2S, [Xn]
    
    
    Instruction Documentation: [vld1_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vld1_s64 (int64_t const * ptr)
    A32: VLD1.64 Dd, [Rn]
    A64: LD1 Vt.1D, [Xn]
    
    
    Instruction Documentation: [vld1_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vld1_s8 (int8_t const * ptr)
    A32: VLD1.8 Dd, [Rn]
    A64: LD1 Vt.8B, [Xn]
    
    
    Instruction Documentation: [vld1_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vld1_u16 (uint16_t const * ptr)
    A32: VLD1.16 Dd, [Rn]
    A64: LD1 Vt.4H, [Xn]
    
    
    Instruction Documentation: [vld1_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vld1_u32 (uint32_t const * ptr)
    A32: VLD1.32 Dd, [Rn]
    A64: LD1 Vt.2S, [Xn]
    
    
    Instruction Documentation: [vld1_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vld1_u64 (uint64_t const * ptr)
    A32: VLD1.64 Dd, [Rn]
    A64: LD1 Vt.1D, [Xn]
    
    
    Instruction Documentation: [vld1_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vld1_u8 (uint8_t const * ptr)
    A32: VLD1.8 Dd, [Rn]
    A64: LD1 Vt.8B, [Xn]
    
    
    Instruction Documentation: [vld1_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_dup_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vld1q_dup_f32 (float32_t const * ptr)
    A32: VLD1.32 { Dd[], Dd+1[] }, [Rn]
    A64: LD1R { Vt.4S }, [Xn]
    
    
    Instruction Documentation: [vld1q_dup_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_dup_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vld1q_dup_s16 (int16_t const * ptr)
    A32: VLD1.16 { Dd[], Dd+1[] }, [Rn]
    A64: LD1R { Vt.8H }, [Xn]
    
    
    Instruction Documentation: [vld1q_dup_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_dup_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vld1q_dup_s32 (int32_t const * ptr)
    A32: VLD1.32 { Dd[], Dd+1[] }, [Rn]
    A64: LD1R { Vt.4S }, [Xn]
    
    
    Instruction Documentation: [vld1q_dup_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_dup_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vld1q_dup_s8 (int8_t const * ptr)
    A32: VLD1.8 { Dd[], Dd+1[] }, [Rn]
    A64: LD1R { Vt.16B }, [Xn]
    
    
    Instruction Documentation: [vld1q_dup_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_dup_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vld1q_dup_u16 (uint16_t const * ptr)
    A32: VLD1.16 { Dd[], Dd+1[] }, [Rn]
    A64: LD1R { Vt.8H }, [Xn]
    
    
    Instruction Documentation: [vld1q_dup_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_dup_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vld1q_dup_u32 (uint32_t const * ptr)
    A32: VLD1.32 { Dd[], Dd+1[] }, [Rn]
    A64: LD1R { Vt.4S }, [Xn]
    
    
    Instruction Documentation: [vld1q_dup_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_dup_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vld1q_dup_u8 (uint8_t const * ptr)
    A32: VLD1.8 { Dd[], Dd+1[] }, [Rn]
    A64: LD1R { Vt.16B }, [Xn]
    
    
    Instruction Documentation: [vld1q_dup_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_dup_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vld1q_f32 (float32_t const * ptr)
    A32: VLD1.32 Dd, Dd+1, [Rn]
    A64: LD1 Vt.4S, [Xn]
    
    
    Instruction Documentation: [vld1q_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vld1q_f64 (float64_t const * ptr)
    A32: VLD1.64 Dd, Dd+1, [Rn]
    A64: LD1 Vt.2D, [Xn]
    
    
    Instruction Documentation: [vld1q_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vld1q_lane_f32 (float32_t const * ptr, float32x4_t src, const int lane)
    A32: VLD1.32 { Dd[index] }, [Rn]
    A64: LD1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vld1q_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_lane_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vld1q_lane_f64 (float64_t const * ptr, float64x2_t src, const int lane)
    A32: VLDR.64 Dd, [Rn]
    A64: LD1 { Vt.D }[index], [Xn]
    
    
    Instruction Documentation: [vld1q_lane_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vld1q_lane_s16 (int16_t const * ptr, int16x8_t src, const int lane)
    A32: VLD1.16 { Dd[index] }, [Rn]
    A64: LD1 { Vt.H }[index], [Xn]
    
    
    Instruction Documentation: [vld1q_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vld1q_lane_s32 (int32_t const * ptr, int32x4_t src, const int lane)
    A32: VLD1.32 { Dd[index] }, [Rn]
    A64: LD1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vld1q_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_lane_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vld1q_lane_s64 (int64_t const * ptr, int64x2_t src, const int lane)
    A32: VLDR.64 Dd, [Rn]
    A64: LD1 { Vt.D }[index], [Xn]
    
    
    Instruction Documentation: [vld1q_lane_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vld1q_lane_s8 (int8_t const * ptr, int8x16_t src, const int lane)
    A32: VLD1.8 { Dd[index] }, [Rn]
    A64: LD1 { Vt.B }[index], [Xn]
    
    
    Instruction Documentation: [vld1q_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vld1q_lane_u16 (uint16_t const * ptr, uint16x8_t src, const int lane)
    A32: VLD1.16 { Dd[index] }, [Rn]
    A64: LD1 { Vt.H }[index], [Xn]
    
    
    Instruction Documentation: [vld1q_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vld1q_lane_u32 (uint32_t const * ptr, uint32x4_t src, const int lane)
    A32: VLD1.32 { Dd[index] }, [Rn]
    A64: LD1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vld1q_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_lane_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vld1q_lane_u64 (uint64_t const * ptr, uint64x2_t src, const int lane)
    A32: VLDR.64 Dd, [Rn]
    A64: LD1 { Vt.D }[index], [Xn]
    
    
    Instruction Documentation: [vld1q_lane_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vld1q_lane_u8 (uint8_t const * ptr, uint8x16_t src, const int lane)
    A32: VLD1.8 { Dd[index] }, [Rn]
    A64: LD1 { Vt.B }[index], [Xn]
    
    
    Instruction Documentation: [vld1q_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_lane_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vld1q_s16 (int16_t const * ptr)
    A32: VLD1.16 Dd, Dd+1, [Rn]
    A64: LD1 Vt.8H, [Xn]
    
    
    Instruction Documentation: [vld1q_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vld1q_s32 (int32_t const * ptr)
    A32: VLD1.32 Dd, Dd+1, [Rn]
    A64: LD1 Vt.4S, [Xn]
    
    
    Instruction Documentation: [vld1q_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vld1q_s64 (int64_t const * ptr)
    A32: VLD1.64 Dd, Dd+1, [Rn]
    A64: LD1 Vt.2D, [Xn]
    
    
    Instruction Documentation: [vld1q_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vld1q_s8 (int8_t const * ptr)
    A32: VLD1.8 Dd, Dd+1, [Rn]
    A64: LD1 Vt.16B, [Xn]
    
    
    Instruction Documentation: [vld1q_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vld1q_u64 (uint64_t const * ptr)
    A32: VLD1.64 Dd, Dd+1, [Rn]
    A64: LD1 Vt.2D, [Xn]
    
    
    Instruction Documentation: [vld1q_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vld1q_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vld1q_u8 (uint8_t const * ptr)
    A32: VLD1.8 Dd, Dd+1, [Rn]
    A64: LD1 Vt.16B, [Xn]
    
    
    Instruction Documentation: [vld1q_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vld1q_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmax_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vmax_f32 (float32x2_t a, float32x2_t b)
    A32: VMAX.F32 Dd, Dn, Dm
    A64: FMAX Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmax_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmax_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmax_s16 (int16x4_t a, int16x4_t b)
    A32: VMAX.S16 Dd, Dn, Dm
    A64: SMAX Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmax_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmax_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmax_s32 (int32x2_t a, int32x2_t b)
    A32: VMAX.S32 Dd, Dn, Dm
    A64: SMAX Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmax_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmax_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vmax_s8 (int8x8_t a, int8x8_t b)
    A32: VMAX.S8 Dd, Dn, Dm
    A64: SMAX Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmax_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmax_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmax_u16 (uint16x4_t a, uint16x4_t b)
    A32: VMAX.U16 Dd, Dn, Dm
    A64: UMAX Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmax_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmax_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmax_u32 (uint32x2_t a, uint32x2_t b)
    A32: VMAX.U32 Dd, Dn, Dm
    A64: UMAX Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmax_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmax_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vmax_u8 (uint8x8_t a, uint8x8_t b)
    A32: VMAX.U8 Dd, Dn, Dm
    A64: UMAX Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmax_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmax_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxnm_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vmaxnm_f32 (float32x2_t a, float32x2_t b)
    A32: VMAXNM.F32 Dd, Dn, Dm
    A64: FMAXNM Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmaxnm_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxnm_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vmaxnm_f64 (float64x1_t a, float64x1_t b)
    A32: VMAXNM.F64 Dd, Dn, Dm
    A64: FMAXNM Dd, Dn, Dm
    
    
    Instruction Documentation: [vmaxnm_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnm_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxnmq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vmaxnmq_f32 (float32x4_t a, float32x4_t b)
    A32: VMAXNM.F32 Qd, Qn, Qm
    A64: FMAXNM Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmaxnmq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnmq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxnms_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vmaxnms_f32 (float32_t a, float32_t b)
    A32: VMAXNM.F32 Sd, Sn, Sm
    A64: FMAXNM Sd, Sn, Sm
    
    
    Instruction Documentation: [vmaxnms_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxnms_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vmaxq_f32 (float32x4_t a, float32x4_t b)
    A32: VMAX.F32 Qd, Qn, Qm
    A64: FMAX Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmaxq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmaxq_s16 (int16x8_t a, int16x8_t b)
    A32: VMAX.S16 Qd, Qn, Qm
    A64: SMAX Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmaxq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmaxq_s32 (int32x4_t a, int32x4_t b)
    A32: VMAX.S32 Qd, Qn, Qm
    A64: SMAX Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmaxq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vmaxq_s8 (int8x16_t a, int8x16_t b)
    A32: VMAX.S8 Qd, Qn, Qm
    A64: SMAX Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmaxq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmaxq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VMAX.U16 Qd, Qn, Qm
    A64: UMAX Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmaxq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmaxq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VMAX.U32 Qd, Qn, Qm
    A64: UMAX Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmaxq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmaxq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vmaxq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VMAX.U8 Qd, Qn, Qm
    A64: UMAX Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmaxq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmaxq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmin_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vmin_f32 (float32x2_t a, float32x2_t b)
    A32: VMIN.F32 Dd, Dn, Dm
    A64: FMIN Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmin_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmin_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmin_s16 (int16x4_t a, int16x4_t b)
    A32: VMIN.S16 Dd, Dn, Dm
    A64: SMIN Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmin_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmin_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmin_s32 (int32x2_t a, int32x2_t b)
    A32: VMIN.S32 Dd, Dn, Dm
    A64: SMIN Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmin_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmin_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vmin_s8 (int8x8_t a, int8x8_t b)
    A32: VMIN.S8 Dd, Dn, Dm
    A64: SMIN Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmin_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmin_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmin_u16 (uint16x4_t a, uint16x4_t b)
    A32: VMIN.U16 Dd, Dn, Dm
    A64: UMIN Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmin_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmin_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmin_u32 (uint32x2_t a, uint32x2_t b)
    A32: VMIN.U32 Dd, Dn, Dm
    A64: UMIN Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmin_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmin_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vmin_u8 (uint8x8_t a, uint8x8_t b)
    A32: VMIN.U8 Dd, Dn, Dm
    A64: UMIN Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmin_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmin_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminnm_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vminnm_f32 (float32x2_t a, float32x2_t b)
    A32: VMINNM.F32 Dd, Dn, Dm
    A64: FMINNM Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vminnm_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminnm_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vminnm_f64 (float64x1_t a, float64x1_t b)
    A32: VMINNM.F64 Dd, Dn, Dm
    A64: FMINNM Dd, Dn, Dm
    
    
    Instruction Documentation: [vminnm_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnm_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminnmq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vminnmq_f32 (float32x4_t a, float32x4_t b)
    A32: VMINNM.F32 Qd, Qn, Qm
    A64: FMINNM Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vminnmq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnmq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminnms_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vminnms_f32 (float32_t a, float32_t b)
    A32: VMINNM.F32 Sd, Sn, Sm
    A64: FMINNM Sd, Sn, Sm
    
    
    Instruction Documentation: [vminnms_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminnms_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vminq_f32 (float32x4_t a, float32x4_t b)
    A32: VMIN.F32 Qd, Qn, Qm
    A64: FMIN Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vminq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vminq_s16 (int16x8_t a, int16x8_t b)
    A32: VMIN.S16 Qd, Qn, Qm
    A64: SMIN Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vminq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vminq_s32 (int32x4_t a, int32x4_t b)
    A32: VMIN.S32 Qd, Qn, Qm
    A64: SMIN Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vminq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vminq_s8 (int8x16_t a, int8x16_t b)
    A32: VMIN.S8 Qd, Qn, Qm
    A64: SMIN Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vminq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vminq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VMIN.U16 Qd, Qn, Qm
    A64: UMIN Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vminq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vminq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VMIN.U32 Qd, Qn, Qm
    A64: UMIN Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vminq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vminq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vminq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VMIN.U8 Qd, Qn, Qm
    A64: UMIN Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vminq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vminq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmla_lane_s16 (int16x4_t a, int16x4_t b, int16x4_t v, const int lane)
    A32: VMLA.I16 Dd, Dn, Dm[lane]
    A64: MLA Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmla_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmla_lane_s32 (int32x2_t a, int32x2_t b, int32x2_t v, const int lane)
    A32: VMLA.I32 Dd, Dn, Dm[lane]
    A64: MLA Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmla_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmla_lane_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
    A32: VMLA.I16 Dd, Dn, Dm[lane]
    A64: MLA Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmla_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmla_lane_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
    A32: VMLA.I32 Dd, Dn, Dm[lane]
    A64: MLA Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmla_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmla_laneq_s16 (int16x4_t a, int16x4_t b, int16x8_t v, const int lane)
    A32: VMLA.I16 Dd, Dn, Dm[lane]
    A64: MLA Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmla_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmla_laneq_s32 (int32x2_t a, int32x2_t b, int32x4_t v, const int lane)
    A32: VMLA.I32 Dd, Dn, Dm[lane]
    A64: MLA Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmla_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmla_laneq_u16 (uint16x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
    A32: VMLA.I16 Dd, Dn, Dm[lane]
    A64: MLA Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmla_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmla_laneq_u32 (uint32x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
    A32: VMLA.I32 Dd, Dn, Dm[lane]
    A64: MLA Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmla_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmla_n_s16 (int16x4_t a, int16x4_t b, int16_t c)
    A32: VMLA.I16 Dd, Dn, Dm[0]
    A64: MLA Vd.4H, Vn.4H, Vm.H[0]
    
    
    Instruction Documentation: [vmla_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmla_n_s32 (int32x2_t a, int32x2_t b, int32_t c)
    A32: VMLA.I32 Dd, Dn, Dm[0]
    A64: MLA Vd.2S, Vn.2S, Vm.S[0]
    
    
    Instruction Documentation: [vmla_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmla_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)
    A32: VMLA.I16 Dd, Dn, Dm[0]
    A64: MLA Vd.4H, Vn.4H, Vm.H[0]
    
    
    Instruction Documentation: [vmla_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmla_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)
    A32: VMLA.I32 Dd, Dn, Dm[0]
    A64: MLA Vd.2S, Vn.2S, Vm.S[0]
    
    
    Instruction Documentation: [vmla_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmla_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
    A32: VMLA.I16 Dd, Dn, Dm
    A64: MLA Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmla_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmla_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
    A32: VMLA.I32 Dd, Dn, Dm
    A64: MLA Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmla_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vmla_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
    A32: VMLA.I8 Dd, Dn, Dm
    A64: MLA Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmla_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmla_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
    A32: VMLA.I16 Dd, Dn, Dm
    A64: MLA Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmla_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmla_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
    A32: VMLA.I32 Dd, Dn, Dm
    A64: MLA Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmla_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmla_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vmla_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
    A32: VMLA.I8 Dd, Dn, Dm
    A64: MLA Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmla_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmla_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlal_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t v, const int lane)
    A32: VMLAL.S16 Qd, Dn+1, Dm[lane]
    A64: SMLAL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlal_high_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlal_high_lane_s32 (int64x2_t a, int32x4_t b, int32x2_t v, const int lane)
    A32: VMLAL.S32 Qd, Dn+1, Dm[lane]
    A64: SMLAL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlal_high_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlal_high_lane_u16 (uint32x4_t a, uint16x8_t b, uint16x4_t v, const int lane)
    A32: VMLAL.U16 Qd, Dn+1, Dm[lane]
    A64: UMLAL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlal_high_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlal_high_lane_u32 (uint64x2_t a, uint32x4_t b, uint32x2_t v, const int lane)
    A32: VMLAL.U32 Qd, Dn+1, Dm[lane]
    A64: UMLAL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlal_high_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlal_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t v, const int lane)
    A32: VMLAL.S16 Qd, Dn+1, Dm[lane]
    A64: SMLAL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlal_high_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlal_high_laneq_s32 (int64x2_t a, int32x4_t b, int32x4_t v, const int lane)
    A32: VMLAL.S32 Qd, Dn+1, Dm[lane]
    A64: SMLAL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlal_high_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlal_high_laneq_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t v, const int lane)
    A32: VMLAL.U16 Qd, Dn+1, Dm[lane]
    A64: UMLAL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlal_high_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlal_high_laneq_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t v, const int lane)
    A32: VMLAL.U32 Qd, Dn+1, Dm[lane]
    A64: UMLAL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlal_high_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlal_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
    A32: VMLAL.S16 Qd, Dn+1, Dm+1
    A64: SMLAL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmlal_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlal_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
    A32: VMLAL.S32 Qd, Dn+1, Dm+1
    A64: SMLAL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmlal_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlal_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
    A32: VMLAL.S8 Qd, Dn+1, Dm+1
    A64: SMLAL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmlal_high_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlal_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
    A32: VMLAL.U16 Qd, Dn+1, Dm+1
    A64: UMLAL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmlal_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlal_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
    A32: VMLAL.U32 Qd, Dn+1, Dm+1
    A64: UMLAL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmlal_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_high_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlal_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
    A32: VMLAL.U8 Qd, Dn+1, Dm+1
    A64: UMLAL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmlal_high_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_high_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlal_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t v, const int lane)
    A32: VMLAL.S16 Qd, Dn, Dm[lane]
    A64: SMLAL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlal_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlal_lane_s32 (int64x2_t a, int32x2_t b, int32x2_t v, const int lane)
    A32: VMLAL.S32 Qd, Dn, Dm[lane]
    A64: SMLAL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlal_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlal_lane_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
    A32: VMLAL.U16 Qd, Dn, Dm[lane]
    A64: UMLAL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlal_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlal_lane_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
    A32: VMLAL.U32 Qd, Dn, Dm[lane]
    A64: UMLAL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlal_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlal_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t v, const int lane)
    A32: VMLAL.S16 Qd, Dn, Dm[lane]
    A64: SMLAL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlal_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlal_laneq_s32 (int64x2_t a, int32x2_t b, int32x4_t v, const int lane)
    A32: VMLAL.S32 Qd, Dn, Dm[lane]
    A64: SMLAL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlal_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlal_laneq_u16 (uint32x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
    A32: VMLAL.U16 Qd, Dn, Dm[lane]
    A64: UMLAL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlal_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlal_laneq_u32 (uint64x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
    A32: VMLAL.U32 Qd, Dn, Dm[lane]
    A64: UMLAL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlal_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlal_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
    A32: VMLAL.S16 Qd, Dn, Dm
    A64: SMLAL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmlal_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlal_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
    A32: VMLAL.S32 Qd, Dn, Dm
    A64: SMLAL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmlal_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlal_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
    A32: VMLAL.S8 Qd, Dn, Dm
    A64: SMLAL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmlal_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlal_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
    A32: VMLAL.U16 Qd, Dn, Dm
    A64: UMLAL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmlal_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlal_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
    A32: VMLAL.U32 Qd, Dn, Dm
    A64: UMLAL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmlal_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlal_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlal_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
    A32: VMLAL.U8 Qd, Dn, Dm
    A64: UMLAL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmlal_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlal_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlaq_lane_s16 (int16x8_t a, int16x8_t b, int16x4_t v, const int lane)
    A32: VMLA.I16 Qd, Qn, Dm[lane]
    A64: MLA Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlaq_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlaq_lane_s32 (int32x4_t a, int32x4_t b, int32x2_t v, const int lane)
    A32: VMLA.I32 Qd, Qn, Dm[lane]
    A64: MLA Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlaq_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlaq_lane_u16 (uint16x8_t a, uint16x8_t b, uint16x4_t v, const int lane)
    A32: VMLA.I16 Qd, Qn, Dm[lane]
    A64: MLA Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlaq_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlaq_lane_u32 (uint32x4_t a, uint32x4_t b, uint32x2_t v, const int lane)
    A32: VMLA.I32 Qd, Qn, Dm[lane]
    A64: MLA Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlaq_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlaq_laneq_s16 (int16x8_t a, int16x8_t b, int16x8_t v, const int lane)
    A32: VMLA.I16 Qd, Qn, Dm[lane]
    A64: MLA Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlaq_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlaq_laneq_s32 (int32x4_t a, int32x4_t b, int32x4_t v, const int lane)
    A32: VMLA.I32 Qd, Qn, Dm[lane]
    A64: MLA Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlaq_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlaq_laneq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t v, const int lane)
    A32: VMLA.I16 Qd, Qn, Dm[lane]
    A64: MLA Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlaq_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlaq_laneq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t v, const int lane)
    A32: VMLA.I32 Qd, Qn, Dm[lane]
    A64: MLA Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlaq_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlaq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
    A32: VMLA.I16 Qd, Qn, Dm[0]
    A64: MLA Vd.8H, Vn.8H, Vm.H[0]
    
    
    Instruction Documentation: [vmlaq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlaq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)
    A32: VMLA.I32 Qd, Qn, Dm[0]
    A64: MLA Vd.4S, Vn.4S, Vm.S[0]
    
    
    Instruction Documentation: [vmlaq_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlaq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)
    A32: VMLA.I16 Qd, Qn, Dm[0]
    A64: MLA Vd.8H, Vn.8H, Vm.H[0]
    
    
    Instruction Documentation: [vmlaq_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlaq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)
    A32: VMLA.I32 Qd, Qn, Dm[0]
    A64: MLA Vd.4S, Vn.4S, Vm.S[0]
    
    
    Instruction Documentation: [vmlaq_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlaq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
    A32: VMLA.I16 Qd, Qn, Qm
    A64: MLA Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmlaq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlaq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
    A32: VMLA.I32 Qd, Qn, Qm
    A64: MLA Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmlaq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vmlaq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
    A32: VMLA.I8 Qd, Qn, Qm
    A64: MLA Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmlaq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlaq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
    A32: VMLA.I16 Qd, Qn, Qm
    A64: MLA Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmlaq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlaq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
    A32: VMLA.I32 Qd, Qn, Qm
    A64: MLA Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmlaq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlaq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vmlaq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
    A32: VMLA.I8 Qd, Qn, Qm
    A64: MLA Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmlaq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlaq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmls_lane_s16 (int16x4_t a, int16x4_t b, int16x4_t v, const int lane)
    A32: VMLS.I16 Dd, Dn, Dm[lane]
    A64: MLS Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmls_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmls_lane_s32 (int32x2_t a, int32x2_t b, int32x2_t v, const int lane)
    A32: VMLS.I32 Dd, Dn, Dm[lane]
    A64: MLS Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmls_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmls_lane_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
    A32: VMLS.I16 Dd, Dn, Dm[lane]
    A64: MLS Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmls_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmls_lane_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
    A32: VMLS.I32 Dd, Dn, Dm[lane]
    A64: MLS Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmls_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmls_laneq_s16 (int16x4_t a, int16x4_t b, int16x8_t v, const int lane)
    A32: VMLS.I16 Dd, Dn, Dm[lane]
    A64: MLS Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmls_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmls_laneq_s32 (int32x2_t a, int32x2_t b, int32x4_t v, const int lane)
    A32: VMLS.I32 Dd, Dn, Dm[lane]
    A64: MLS Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmls_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmls_laneq_u16 (uint16x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
    A32: VMLS.I16 Dd, Dn, Dm[lane]
    A64: MLS Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmls_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmls_laneq_u32 (uint32x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
    A32: VMLS.I32 Dd, Dn, Dm[lane]
    A64: MLS Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmls_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmls_n_s16 (int16x4_t a, int16x4_t b, int16_t c)
    A32: VMLS.I16 Dd, Dn, Dm[0]
    A64: MLS Vd.4H, Vn.4H, Vm.H[0]
    
    
    Instruction Documentation: [vmls_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmls_n_s32 (int32x2_t a, int32x2_t b, int32_t c)
    A32: VMLS.I32 Dd, Dn, Dm[0]
    A64: MLS Vd.2S, Vn.2S, Vm.S[0]
    
    
    Instruction Documentation: [vmls_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmls_n_u16 (uint16x4_t a, uint16x4_t b, uint16_t c)
    A32: VMLS.I16 Dd, Dn, Dm[0]
    A64: MLS Vd.4H, Vn.4H, Vm.H[0]
    
    
    Instruction Documentation: [vmls_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmls_n_u32 (uint32x2_t a, uint32x2_t b, uint32_t c)
    A32: VMLS.I32 Dd, Dn, Dm[0]
    A64: MLS Vd.2S, Vn.2S, Vm.S[0]
    
    
    Instruction Documentation: [vmls_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmls_s16 (int16x4_t a, int16x4_t b, int16x4_t c)
    A32: VMLS.I16 Dd, Dn, Dm
    A64: MLS Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmls_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmls_s32 (int32x2_t a, int32x2_t b, int32x2_t c)
    A32: VMLS.I32 Dd, Dn, Dm
    A64: MLS Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmls_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vmls_s8 (int8x8_t a, int8x8_t b, int8x8_t c)
    A32: VMLS.I8 Dd, Dn, Dm
    A64: MLS Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmls_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmls_u16 (uint16x4_t a, uint16x4_t b, uint16x4_t c)
    A32: VMLS.I16 Dd, Dn, Dm
    A64: MLS Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmls_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmls_u32 (uint32x2_t a, uint32x2_t b, uint32x2_t c)
    A32: VMLS.I32 Dd, Dn, Dm
    A64: MLS Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmls_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmls_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vmls_u8 (uint8x8_t a, uint8x8_t b, uint8x8_t c)
    A32: VMLS.I8 Dd, Dn, Dm
    A64: MLS Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmls_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmls_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlsl_high_lane_s16 (int32x4_t a, int16x8_t b, int16x4_t v, const int lane)
    A32: VMLSL.S16 Qd, Dn+1, Dm[lane]
    A64: SMLSL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsl_high_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlsl_high_lane_s32 (int64x2_t a, int32x4_t b, int32x2_t v, const int lane)
    A32: VMLSL.S32 Qd, Dn+1, Dm[lane]
    A64: SMLSL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsl_high_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlsl_high_lane_u16 (uint32x4_t a, uint16x8_t b, uint16x4_t v, const int lane)
    A32: VMLSL.U16 Qd, Dn+1, Dm[lane]
    A64: UMLSL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsl_high_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlsl_high_lane_u32 (uint64x2_t a, uint32x4_t b, uint32x2_t v, const int lane)
    A32: VMLSL.U32 Qd, Dn+1, Dm[lane]
    A64: UMLSL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsl_high_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlsl_high_laneq_s16 (int32x4_t a, int16x8_t b, int16x8_t v, const int lane)
    A32: VMLSL.S16 Qd, Dn+1, Dm[lane]
    A64: SMLSL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsl_high_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlsl_high_laneq_s32 (int64x2_t a, int32x4_t b, int32x4_t v, const int lane)
    A32: VMLSL.S32 Qd, Dn+1, Dm[lane]
    A64: SMLSL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsl_high_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlsl_high_laneq_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t v, const int lane)
    A32: VMLSL.U16 Qd, Dn+1, Dm[lane]
    A64: UMLSL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsl_high_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlsl_high_laneq_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t v, const int lane)
    A32: VMLSL.U32 Qd, Dn+1, Dm[lane]
    A64: UMLSL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsl_high_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlsl_high_s16 (int32x4_t a, int16x8_t b, int16x8_t c)
    A32: VMLSL.S16 Qd, Dn+1, Dm+1
    A64: SMLSL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmlsl_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlsl_high_s32 (int64x2_t a, int32x4_t b, int32x4_t c)
    A32: VMLSL.S32 Qd, Dn+1, Dm+1
    A64: SMLSL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmlsl_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlsl_high_s8 (int16x8_t a, int8x16_t b, int8x16_t c)
    A32: VMLSL.S8 Qd, Dn+1, Dm+1
    A64: SMLSL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmlsl_high_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlsl_high_u16 (uint32x4_t a, uint16x8_t b, uint16x8_t c)
    A32: VMLSL.U16 Qd, Dn+1, Dm+1
    A64: UMLSL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmlsl_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlsl_high_u32 (uint64x2_t a, uint32x4_t b, uint32x4_t c)
    A32: VMLSL.U32 Qd, Dn+1, Dm+1
    A64: UMLSL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmlsl_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_high_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlsl_high_u8 (uint16x8_t a, uint8x16_t b, uint8x16_t c)
    A32: VMLSL.U8 Qd, Dn+1, Dm+1
    A64: UMLSL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmlsl_high_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_high_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlsl_lane_s16 (int32x4_t a, int16x4_t b, int16x4_t v, const int lane)
    A32: VMLSL.S16 Qd, Dn, Dm[lane]
    A64: SMLSL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsl_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlsl_lane_s32 (int64x2_t a, int32x2_t b, int32x2_t v, const int lane)
    A32: VMLSL.S32 Qd, Dn, Dm[lane]
    A64: SMLSL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsl_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlsl_lane_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t v, const int lane)
    A32: VMLSL.U16 Qd, Dn, Dm[lane]
    A64: UMLSL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsl_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlsl_lane_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t v, const int lane)
    A32: VMLSL.U32 Qd, Dn, Dm[lane]
    A64: UMLSL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsl_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlsl_laneq_s16 (int32x4_t a, int16x4_t b, int16x8_t v, const int lane)
    A32: VMLSL.S16 Qd, Dn, Dm[lane]
    A64: SMLSL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsl_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlsl_laneq_s32 (int64x2_t a, int32x2_t b, int32x4_t v, const int lane)
    A32: VMLSL.S32 Qd, Dn, Dm[lane]
    A64: SMLSL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsl_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlsl_laneq_u16 (uint32x4_t a, uint16x4_t b, uint16x8_t v, const int lane)
    A32: VMLSL.U16 Qd, Dn, Dm[lane]
    A64: UMLSL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsl_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlsl_laneq_u32 (uint64x2_t a, uint32x2_t b, uint32x4_t v, const int lane)
    A32: VMLSL.U32 Qd, Dn, Dm[lane]
    A64: UMLSL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsl_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlsl_s16 (int32x4_t a, int16x4_t b, int16x4_t c)
    A32: VMLSL.S16 Qd, Dn, Dm
    A64: SMLSL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmlsl_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmlsl_s32 (int64x2_t a, int32x2_t b, int32x2_t c)
    A32: VMLSL.S32 Qd, Dn, Dm
    A64: SMLSL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmlsl_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlsl_s8 (int16x8_t a, int8x8_t b, int8x8_t c)
    A32: VMLSL.S8 Qd, Dn, Dm
    A64: SMLSL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmlsl_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlsl_u16 (uint32x4_t a, uint16x4_t b, uint16x4_t c)
    A32: VMLSL.U16 Qd, Dn, Dm
    A64: UMLSL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmlsl_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmlsl_u32 (uint64x2_t a, uint32x2_t b, uint32x2_t c)
    A32: VMLSL.U32 Qd, Dn, Dm
    A64: UMLSL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmlsl_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsl_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlsl_u8 (uint16x8_t a, uint8x8_t b, uint8x8_t c)
    A32: VMLSL.U8 Qd, Dn, Dm
    A64: UMLSL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmlsl_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsl_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlsq_lane_s16 (int16x8_t a, int16x8_t b, int16x4_t v, const int lane)
    A32: VMLS.I16 Qd, Qn, Dm[lane]
    A64: MLS Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsq_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlsq_lane_s32 (int32x4_t a, int32x4_t b, int32x2_t v, const int lane)
    A32: VMLS.I32 Qd, Qn, Dm[lane]
    A64: MLS Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsq_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlsq_lane_u16 (uint16x8_t a, uint16x8_t b, uint16x4_t v, const int lane)
    A32: VMLS.I16 Qd, Qn, Dm[lane]
    A64: MLS Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsq_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlsq_lane_u32 (uint32x4_t a, uint32x4_t b, uint32x2_t v, const int lane)
    A32: VMLS.I32 Qd, Qn, Dm[lane]
    A64: MLS Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsq_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlsq_laneq_s16 (int16x8_t a, int16x8_t b, int16x8_t v, const int lane)
    A32: VMLS.I16 Qd, Qn, Dm[lane]
    A64: MLS Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsq_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlsq_laneq_s32 (int32x4_t a, int32x4_t b, int32x4_t v, const int lane)
    A32: VMLS.I32 Qd, Qn, Dm[lane]
    A64: MLS Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsq_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlsq_laneq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t v, const int lane)
    A32: VMLS.I16 Qd, Qn, Dm[lane]
    A64: MLS Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmlsq_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlsq_laneq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t v, const int lane)
    A32: VMLS.I32 Qd, Qn, Dm[lane]
    A64: MLS Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmlsq_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlsq_n_s16 (int16x8_t a, int16x8_t b, int16_t c)
    A32: VMLS.I16 Qd, Qn, Dm[0]
    A64: MLS Vd.8H, Vn.8H, Vm.H[0]
    
    
    Instruction Documentation: [vmlsq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlsq_n_s32 (int32x4_t a, int32x4_t b, int32_t c)
    A32: VMLS.I32 Qd, Qn, Dm[0]
    A64: MLS Vd.4S, Vn.4S, Vm.S[0]
    
    
    Instruction Documentation: [vmlsq_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlsq_n_u16 (uint16x8_t a, uint16x8_t b, uint16_t c)
    A32: VMLS.I16 Qd, Qn, Dm[0]
    A64: MLS Vd.8H, Vn.8H, Vm.H[0]
    
    
    Instruction Documentation: [vmlsq_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlsq_n_u32 (uint32x4_t a, uint32x4_t b, uint32_t c)
    A32: VMLS.I32 Qd, Qn, Dm[0]
    A64: MLS Vd.4S, Vn.4S, Vm.S[0]
    
    
    Instruction Documentation: [vmlsq_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmlsq_s16 (int16x8_t a, int16x8_t b, int16x8_t c)
    A32: VMLS.I16 Qd, Qn, Qm
    A64: MLS Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmlsq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmlsq_s32 (int32x4_t a, int32x4_t b, int32x4_t c)
    A32: VMLS.I32 Qd, Qn, Qm
    A64: MLS Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmlsq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vmlsq_s8 (int8x16_t a, int8x16_t b, int8x16_t c)
    A32: VMLS.I8 Qd, Qn, Qm
    A64: MLS Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmlsq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmlsq_u16 (uint16x8_t a, uint16x8_t b, uint16x8_t c)
    A32: VMLS.I16 Qd, Qn, Qm
    A64: MLS Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmlsq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmlsq_u32 (uint32x4_t a, uint32x4_t b, uint32x4_t c)
    A32: VMLS.I32 Qd, Qn, Qm
    A64: MLS Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmlsq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmlsq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vmlsq_u8 (uint8x16_t a, uint8x16_t b, uint8x16_t c)
    A32: VMLS.I8 Qd, Qn, Qm
    A64: MLS Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmlsq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmlsq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmovl_high_s16 (int16x8_t a)
    A32: VMOVL.S16 Qd, Dm+1
    A64: SXTL2 Vd.4S, Vn.8H
    
    
    Instruction Documentation: [vmovl_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmovl_high_s32 (int32x4_t a)
    A32: VMOVL.S32 Qd, Dm+1
    A64: SXTL2 Vd.2D, Vn.4S
    
    
    Instruction Documentation: [vmovl_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_high_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmovl_high_s8 (int8x16_t a)
    A32: VMOVL.S8 Qd, Dm+1
    A64: SXTL2 Vd.8H, Vn.16B
    
    
    Instruction Documentation: [vmovl_high_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmovl_high_u16 (uint16x8_t a)
    A32: VMOVL.U16 Qd, Dm+1
    A64: UXTL2 Vd.4S, Vn.8H
    
    
    Instruction Documentation: [vmovl_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmovl_high_u32 (uint32x4_t a)
    A32: VMOVL.U32 Qd, Dm+1
    A64: UXTL2 Vd.2D, Vn.4S
    
    
    Instruction Documentation: [vmovl_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_high_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmovl_high_u8 (uint8x16_t a)
    A32: VMOVL.U8 Qd, Dm+1
    A64: UXTL2 Vd.8H, Vn.16B
    
    
    Instruction Documentation: [vmovl_high_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_high_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmovl_s16 (int16x4_t a)
    A32: VMOVL.S16 Qd, Dm
    A64: SXTL Vd.4S, Vn.4H
    
    
    Instruction Documentation: [vmovl_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmovl_s32 (int32x2_t a)
    A32: VMOVL.S32 Qd, Dm
    A64: SXTL Vd.2D, Vn.2S
    
    
    Instruction Documentation: [vmovl_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmovl_s8 (int8x8_t a)
    A32: VMOVL.S8 Qd, Dm
    A64: SXTL Vd.8H, Vn.8B
    
    
    Instruction Documentation: [vmovl_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmovl_u16 (uint16x4_t a)
    A32: VMOVL.U16 Qd, Dm
    A64: UXTL Vd.4S, Vn.4H
    
    
    Instruction Documentation: [vmovl_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmovl_u32 (uint32x2_t a)
    A32: VMOVL.U32 Qd, Dm
    A64: UXTL Vd.2D, Vn.2S
    
    
    Instruction Documentation: [vmovl_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovl_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmovl_u8 (uint8x8_t a)
    A32: VMOVL.U8 Qd, Dm
    A64: UXTL Vd.8H, Vn.8B
    
    
    Instruction Documentation: [vmovl_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovl_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vmovn_high_s16 (int8x8_t r, int16x8_t a)
    A32: VMOVN.I16 Dd+1, Qm
    A64: XTN2 Vd.16B, Vn.8H
    
    
    Instruction Documentation: [vmovn_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmovn_high_s32 (int16x4_t r, int32x4_t a)
    A32: VMOVN.I32 Dd+1, Qm
    A64: XTN2 Vd.8H, Vn.4S
    
    
    Instruction Documentation: [vmovn_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_high_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmovn_high_s64 (int32x2_t r, int64x2_t a)
    A32: VMOVN.I64 Dd+1, Qm
    A64: XTN2 Vd.4S, Vn.2D
    
    
    Instruction Documentation: [vmovn_high_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vmovn_high_u16 (uint8x8_t r, uint16x8_t a)
    A32: VMOVN.I16 Dd+1, Qm
    A64: XTN2 Vd.16B, Vn.8H
    
    
    Instruction Documentation: [vmovn_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmovn_high_u32 (uint16x4_t r, uint32x4_t a)
    A32: VMOVN.I32 Dd+1, Qm
    A64: XTN2 Vd.8H, Vn.4S
    
    
    Instruction Documentation: [vmovn_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_high_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmovn_high_u64 (uint32x2_t r, uint64x2_t a)
    A32: VMOVN.I64 Dd+1, Qm
    A64: XTN2 Vd.4S, Vn.2D
    
    
    Instruction Documentation: [vmovn_high_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_high_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vmovn_s16 (int16x8_t a)
    A32: VMOVN.I16 Dd, Qm
    A64: XTN Vd.8B, Vn.8H
    
    
    Instruction Documentation: [vmovn_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmovn_s32 (int32x4_t a)
    A32: VMOVN.I32 Dd, Qm
    A64: XTN Vd.4H, Vn.4S
    
    
    Instruction Documentation: [vmovn_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmovn_s64 (int64x2_t a)
    A32: VMOVN.I64 Dd, Qm
    A64: XTN Vd.2S, Vn.2D
    
    
    Instruction Documentation: [vmovn_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vmovn_u16 (uint16x8_t a)
    A32: VMOVN.I16 Dd, Qm
    A64: XTN Vd.8B, Vn.8H
    
    
    Instruction Documentation: [vmovn_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmovn_u32 (uint32x4_t a)
    A32: VMOVN.I32 Dd, Qm
    A64: XTN Vd.4H, Vn.4S
    
    
    Instruction Documentation: [vmovn_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmovn_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmovn_u64 (uint64x2_t a)
    A32: VMOVN.I64 Dd, Qm
    A64: XTN Vd.2S, Vn.2D
    
    
    Instruction Documentation: [vmovn_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmovn_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vmul_f32 (float32x2_t a, float32x2_t b)
    A32: VMUL.F32 Dd, Dn, Dm
    A64: FMUL Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmul_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vmul_f64 (float64x1_t a, float64x1_t b)
    A32: VMUL.F64 Dd, Dn, Dm
    A64: FMUL Dd, Dn, Dm
    
    
    Instruction Documentation: [vmul_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vmul_lane_f32 (float32x2_t a, float32x2_t v, const int lane)
    A32: VMUL.F32 Dd, Dn, Dm[lane]
    A64: FMUL Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmul_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmul_lane_s16 (int16x4_t a, int16x4_t v, const int lane)
    A32: VMUL.I16 Dd, Dn, Dm[lane]
    A64: MUL Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmul_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmul_lane_s32 (int32x2_t a, int32x2_t v, const int lane)
    A32: VMUL.I32 Dd, Dn, Dm[lane]
    A64: MUL Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmul_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmul_lane_u16 (uint16x4_t a, uint16x4_t v, const int lane)
    A32: VMUL.I16 Dd, Dn, Dm[lane]
    A64: MUL Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmul_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmul_lane_u32 (uint32x2_t a, uint32x2_t v, const int lane)
    A32: VMUL.I32 Dd, Dn, Dm[lane]
    A64: MUL Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmul_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vmul_laneq_f32 (float32x2_t a, float32x4_t v, const int lane)
    A32: VMUL.F32 Dd, Dn, Dm[lane]
    A64: FMUL Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmul_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmul_laneq_s16 (int16x4_t a, int16x8_t v, const int lane)
    A32: VMUL.I16 Dd, Dn, Dm[lane]
    A64: MUL Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmul_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmul_laneq_s32 (int32x2_t a, int32x4_t v, const int lane)
    A32: VMUL.I32 Dd, Dn, Dm[lane]
    A64: MUL Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmul_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmul_laneq_u16 (uint16x4_t a, uint16x8_t v, const int lane)
    A32: VMUL.I16 Dd, Dn, Dm[lane]
    A64: MUL Vd.4H, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmul_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmul_laneq_u32 (uint32x2_t a, uint32x4_t v, const int lane)
    A32: VMUL.I32 Dd, Dn, Dm[lane]
    A64: MUL Vd.2S, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmul_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_n_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vmul_n_f32 (float32x2_t a, float32_t b)
    A32: VMUL.F32 Dd, Dn, Dm[0]
    A64: FMUL Vd.2S, Vn.2S, Vm.S[0]
    
    
    Instruction Documentation: [vmul_n_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmul_n_s16 (int16x4_t a, int16_t b)
    A32: VMUL.I16 Dd, Dn, Dm[0]
    A64: MUL Vd.4H, Vn.4H, Vm.H[0]
    
    
    Instruction Documentation: [vmul_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmul_n_s32 (int32x2_t a, int32_t b)
    A32: VMUL.I32 Dd, Dn, Dm[0]
    A64: MUL Vd.2S, Vn.2S, Vm.S[0]
    
    
    Instruction Documentation: [vmul_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmul_n_u16 (uint16x4_t a, uint16_t b)
    A32: VMUL.I16 Dd, Dn, Dm[0]
    A64: MUL Vd.4H, Vn.4H, Vm.H[0]
    
    
    Instruction Documentation: [vmul_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmul_n_u32 (uint32x2_t a, uint32_t b)
    A32: VMUL.I32 Dd, Dn, Dm[0]
    A64: MUL Vd.2S, Vn.2S, Vm.S[0]
    
    
    Instruction Documentation: [vmul_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_p8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"poly8x8_t vmul_p8 (poly8x8_t a, poly8x8_t b)
    A32: VMUL.P8 Dd, Dn, Dm
    A64: PMUL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmul_p8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_p8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmul_s16 (int16x4_t a, int16x4_t b)
    A32: VMUL.I16 Dd, Dn, Dm
    A64: MUL Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmul_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmul_s32 (int32x2_t a, int32x2_t b)
    A32: VMUL.I32 Dd, Dn, Dm
    A64: MUL Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmul_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vmul_s8 (int8x8_t a, int8x8_t b)
    A32: VMUL.I8 Dd, Dn, Dm
    A64: MUL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmul_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmul_u16 (uint16x4_t a, uint16x4_t b)
    A32: VMUL.I16 Dd, Dn, Dm
    A64: MUL Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmul_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmul_u32 (uint32x2_t a, uint32x2_t b)
    A32: VMUL.I32 Dd, Dn, Dm
    A64: MUL Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmul_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmul_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vmul_u8 (uint8x8_t a, uint8x8_t b)
    A32: VMUL.I8 Dd, Dn, Dm
    A64: MUL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmul_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmul_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmull_high_lane_s16 (int16x8_t a, int16x4_t v, const int lane)
    A32: VMULL.S16 Qd, Dn+1, Dm[lane]
    A64: SMULL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmull_high_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmull_high_lane_s32 (int32x4_t a, int32x2_t v, const int lane)
    A32: VMULL.S32 Qd, Dn+1, Dm[lane]
    A64: SMULL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmull_high_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmull_high_lane_u16 (uint16x8_t a, uint16x4_t v, const int lane)
    A32: VMULL.U16 Qd, Dn+1, Dm[lane]
    A64: UMULL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmull_high_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmull_high_lane_u32 (uint32x4_t a, uint32x2_t v, const int lane)
    A32: VMULL.U32 Qd, Dn+1, Dm[lane]
    A64: UMULL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmull_high_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmull_high_laneq_s16 (int16x8_t a, int16x8_t v, const int lane)
    A32: VMULL.S16 Qd, Dn+1, Dm[lane]
    A64: SMULL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmull_high_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmull_high_laneq_s32 (int32x4_t a, int32x4_t v, const int lane)
    A32: VMULL.S32 Qd, Dn+1, Dm[lane]
    A64: SMULL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmull_high_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmull_high_laneq_u16 (uint16x8_t a, uint16x8_t v, const int lane)
    A32: VMULL.U16 Qd, Dn+1, Dm[lane]
    A64: UMULL2 Vd.4S, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmull_high_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmull_high_laneq_u32 (uint32x4_t a, uint32x4_t v, const int lane)
    A32: VMULL.U32 Qd, Dn+1, Dm[lane]
    A64: UMULL2 Vd.2D, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmull_high_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_p8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"poly16x8_t vmull_high_p8 (poly8x16_t a, poly8x16_t b)
    A32: VMULL.P8 Qd, Dn+1, Dm+1
    A64: PMULL2 Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmull_high_p8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmull_high_s16 (int16x8_t a, int16x8_t b)
    A32: VMULL.S16 Qd, Dn+1, Dm+1
    A64: SMULL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmull_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmull_high_s32 (int32x4_t a, int32x4_t b)
    A32: VMULL.S32 Qd, Dn+1, Dm+1
    A64: SMULL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmull_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmull_high_s8 (int8x16_t a, int8x16_t b)
    A32: VMULL.S8 Qd, Dn+1, Dm+1
    A64: SMULL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmull_high_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmull_high_u16 (uint16x8_t a, uint16x8_t b)
    A32: VMULL.U16 Qd, Dn+1, Dm+1
    A64: UMULL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmull_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmull_high_u32 (uint32x4_t a, uint32x4_t b)
    A32: VMULL.U32 Qd, Dn+1, Dm+1
    A64: UMULL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmull_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmull_high_u8 (uint8x16_t a, uint8x16_t b)
    A32: VMULL.U8 Qd, Dn+1, Dm+1
    A64: UMULL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmull_high_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmull_lane_s16 (int16x4_t a, int16x4_t v, const int lane)
    A32: VMULL.S16 Qd, Dn, Dm[lane]
    A64: SMULL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmull_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmull_lane_s32 (int32x2_t a, int32x2_t v, const int lane)
    A32: VMULL.S32 Qd, Dn, Dm[lane]
    A64: SMULL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmull_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmull_lane_u16 (uint16x4_t a, uint16x4_t v, const int lane)
    A32: VMULL.U16 Qd, Dn, Dm[lane]
    A64: UMULL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmull_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmull_lane_u32 (uint32x2_t a, uint32x2_t v, const int lane)
    A32: VMULL.U32 Qd, Dn, Dm[lane]
    A64: UMULL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmull_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmull_laneq_s16 (int16x4_t a, int16x8_t v, const int lane)
    A32: VMULL.S16 Qd, Dn, Dm[lane]
    A64: SMULL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmull_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmull_laneq_s32 (int32x2_t a, int32x4_t v, const int lane)
    A32: VMULL.S32 Qd, Dn, Dm[lane]
    A64: SMULL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmull_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmull_laneq_u16 (uint16x4_t a, uint16x8_t v, const int lane)
    A32: VMULL.U16 Qd, Dn, Dm[lane]
    A64: UMULL Vd.4S, Vn.4H, Vm.H[lane]
    
    
    Instruction Documentation: [vmull_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmull_laneq_u32 (uint32x2_t a, uint32x4_t v, const int lane)
    A32: VMULL.U32 Qd, Dn, Dm[lane]
    A64: UMULL Vd.2D, Vn.2S, Vm.S[lane]
    
    
    Instruction Documentation: [vmull_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_p8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"poly16x8_t vmull_p8 (poly8x8_t a, poly8x8_t b)
    A32: VMULL.P8 Qd, Dn, Dm
    A64: PMULL Vd.16B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmull_p8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmull_s16 (int16x4_t a, int16x4_t b)
    A32: VMULL.S16 Qd, Dn, Dm
    A64: SMULL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmull_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmull_s32 (int32x2_t a, int32x2_t b)
    A32: VMULL.S32 Qd, Dn, Dm
    A64: SMULL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmull_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmull_s8 (int8x8_t a, int8x8_t b)
    A32: VMULL.S8 Qd, Dn, Dm
    A64: SMULL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmull_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmull_u16 (uint16x4_t a, uint16x4_t b)
    A32: VMULL.U16 Qd, Dn, Dm
    A64: UMULL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vmull_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmull_u32 (uint32x2_t a, uint32x2_t b)
    A32: VMULL.U32 Qd, Dn, Dm
    A64: UMULL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vmull_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmull_u8 (uint8x8_t a, uint8x8_t b)
    A32: VMULL.U8 Qd, Dn, Dm
    A64: UMULL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vmull_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vmulq_f32 (float32x4_t a, float32x4_t b)
    A32: VMUL.F32 Qd, Qn, Qm
    A64: FMUL Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmulq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vmulq_lane_f32 (float32x4_t a, float32x2_t v, const int lane)
    A32: VMUL.F32 Qd, Qn, Dm[lane]
    A64: FMUL Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmulq_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmulq_lane_s16 (int16x8_t a, int16x4_t v, const int lane)
    A32: VMUL.I16 Qd, Qn, Dm[lane]
    A64: MUL Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmulq_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmulq_lane_s32 (int32x4_t a, int32x2_t v, const int lane)
    A32: VMUL.I32 Qd, Qn, Dm[lane]
    A64: MUL Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmulq_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmulq_lane_u16 (uint16x8_t a, uint16x4_t v, const int lane)
    A32: VMUL.I16 Qd, Qn, Dm[lane]
    A64: MUL Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmulq_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmulq_lane_u32 (uint32x4_t a, uint32x2_t v, const int lane)
    A32: VMUL.I32 Qd, Qn, Dm[lane]
    A64: MUL Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmulq_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vmulq_laneq_f32 (float32x4_t a, float32x4_t v, const int lane)
    A32: VMUL.F32 Qd, Qn, Dm[lane]
    A64: FMUL Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmulq_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_laneq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmulq_laneq_s16 (int16x8_t a, int16x8_t v, const int lane)
    A32: VMUL.I16 Qd, Qn, Dm[lane]
    A64: MUL Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmulq_laneq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_laneq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmulq_laneq_s32 (int32x4_t a, int32x4_t v, const int lane)
    A32: VMUL.I32 Qd, Qn, Dm[lane]
    A64: MUL Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmulq_laneq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_laneq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmulq_laneq_u16 (uint16x8_t a, uint16x8_t v, const int lane)
    A32: VMUL.I16 Qd, Qn, Dm[lane]
    A64: MUL Vd.8H, Vn.8H, Vm.H[lane]
    
    
    Instruction Documentation: [vmulq_laneq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_laneq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmulq_laneq_u32 (uint32x4_t a, uint32x4_t v, const int lane)
    A32: VMUL.I32 Qd, Qn, Dm[lane]
    A64: MUL Vd.4S, Vn.4S, Vm.S[lane]
    
    
    Instruction Documentation: [vmulq_laneq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_laneq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_n_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vmulq_n_f32 (float32x4_t a, float32_t b)
    A32: VMUL.F32 Qd, Qn, Dm[0]
    A64: FMUL Vd.4S, Vn.4S, Vm.S[0]
    
    
    Instruction Documentation: [vmulq_n_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmulq_n_s16 (int16x8_t a, int16_t b)
    A32: VMUL.I16 Qd, Qn, Dm[0]
    A64: MUL Vd.8H, Vn.8H, Vm.H[0]
    
    
    Instruction Documentation: [vmulq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmulq_n_s32 (int32x4_t a, int32_t b)
    A32: VMUL.I32 Qd, Qn, Dm[0]
    A64: MUL Vd.4S, Vn.4S, Vm.S[0]
    
    
    Instruction Documentation: [vmulq_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmulq_n_u16 (uint16x8_t a, uint16_t b)
    A32: VMUL.I16 Qd, Qn, Dm[0]
    A64: MUL Vd.8H, Vn.8H, Vm.H[0]
    
    
    Instruction Documentation: [vmulq_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmulq_n_u32 (uint32x4_t a, uint32_t b)
    A32: VMUL.I32 Qd, Qn, Dm[0]
    A64: MUL Vd.4S, Vn.4S, Vm.S[0]
    
    
    Instruction Documentation: [vmulq_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_p8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"poly8x16_t vmulq_p8 (poly8x16_t a, poly8x16_t b)
    A32: VMUL.P8 Qd, Qn, Qm
    A64: PMUL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmulq_p8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_p8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmulq_s16 (int16x8_t a, int16x8_t b)
    A32: VMUL.I16 Qd, Qn, Qm
    A64: MUL Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmulq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmulq_s32 (int32x4_t a, int32x4_t b)
    A32: VMUL.I32 Qd, Qn, Qm
    A64: MUL Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmulq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vmulq_s8 (int8x16_t a, int8x16_t b)
    A32: VMUL.I8 Qd, Qn, Qm
    A64: MUL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmulq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmulq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VMUL.I16 Qd, Qn, Qm
    A64: MUL Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vmulq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmulq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VMUL.I32 Qd, Qn, Qm
    A64: MUL Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vmulq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmulq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vmulq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VMUL.I8 Qd, Qn, Qm
    A64: MUL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vmulq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmulq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmuls_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vmuls_f32 (float32_t a, float32_t b)
    A32: VMUL.F32 Sd, Sn, Sm
    A64: FMUL Sd, Sn, Sm The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vmuls_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmuls_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vmuls_lane_f32 (float32_t a, float32x2_t v, const int lane)
    A32: VMUL.F32 Sd, Sn, Dm[lane]
    A64: FMUL Sd, Sn, Vm.S[lane]
    
    
    Instruction Documentation: [vmuls_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmuls_laneq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vmuls_laneq_f32 (float32_t a, float32x4_t v, const int lane)
    A32: VMUL.F32 Sd, Sn, Dm[lane]
    A64: FMUL Sd, Sn, Vm.S[lane]
    
    
    Instruction Documentation: [vmuls_laneq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmuls_laneq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvn_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vmvn_f32 (float32x2_t a)
    A32: VMVN Dd, Dm
    A64: MVN Vd.8B, Vn.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vmvn_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvn_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vmvn_f64 (float64x1_t a)
    A32: VMVN Dd, Dm
    A64: MVN Vd.8B, Vn.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vmvn_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvn_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vmvn_s16 (int16x4_t a)
    A32: VMVN Dd, Dm
    A64: MVN Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vmvn_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvn_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vmvn_s32 (int32x2_t a)
    A32: VMVN Dd, Dm
    A64: MVN Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vmvn_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvn_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vmvn_s64 (int64x1_t a)
    A32: VMVN Dd, Dm
    A64: MVN Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vmvn_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvn_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vmvn_s8 (int8x8_t a)
    A32: VMVN Dd, Dm
    A64: MVN Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vmvn_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvn_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vmvn_u16 (uint16x4_t a)
    A32: VMVN Dd, Dm
    A64: MVN Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vmvn_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvn_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vmvn_u32 (uint32x2_t a)
    A32: VMVN Dd, Dm
    A64: MVN Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vmvn_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvn_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vmvn_u64 (uint64x1_t a)
    A32: VMVN Dd, Dm
    A64: MVN Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vmvn_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvn_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vmvn_u8 (uint8x8_t a)
    A32: VMVN Dd, Dm
    A64: MVN Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vmvn_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvn_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvnq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vmvnq_f32 (float32x4_t a)
    A32: VMVN Qd, Qm
    A64: MVN Vd.16B, Vn.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vmvnq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvnq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vmvnq_f64 (float64x2_t a)
    A32: VMVN Qd, Qm
    A64: MVN Vd.16B, Vn.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vmvnq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvnq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vmvnq_s16 (int16x8_t a)
    A32: VMVN Qd, Qm
    A64: MVN Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vmvnq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvnq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vmvnq_s32 (int32x4_t a)
    A32: VMVN Qd, Qm
    A64: MVN Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vmvnq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvnq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vmvnq_s64 (int64x2_t a)
    A32: VMVN Qd, Qm
    A64: MVN Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vmvnq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvnq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vmvnq_s8 (int8x16_t a)
    A32: VMVN Qd, Qm
    A64: MVN Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vmvnq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvnq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vmvnq_u16 (uint16x8_t a)
    A32: VMVN Qd, Qm
    A64: MVN Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vmvnq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvnq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vmvnq_u32 (uint32x4_t a)
    A32: VMVN Qd, Qm
    A64: MVN Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vmvnq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvnq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vmvnq_u64 (uint64x2_t a)
    A32: VMVN Qd, Qm
    A64: MVN Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vmvnq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmvnq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vmvnq_u8 (uint8x16_t a)
    A32: VMVN Qd, Qm
    A64: MVN Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vmvnq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmvnq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vneg_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vneg_f32 (float32x2_t a)
    A32: VNEG.F32 Dd, Dm
    A64: FNEG Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vneg_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vneg_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vneg_f64 (float64x1_t a)
    A32: VNEG.F64 Dd, Dm
    A64: FNEG Dd, Dn
    
    
    Instruction Documentation: [vneg_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vneg_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vneg_s16 (int16x4_t a)
    A32: VNEG.S16 Dd, Dm
    A64: NEG Vd.4H, Vn.4H
    
    
    Instruction Documentation: [vneg_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vneg_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vneg_s32 (int32x2_t a)
    A32: VNEG.S32 Dd, Dm
    A64: NEG Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vneg_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vneg_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vneg_s8 (int8x8_t a)
    A32: VNEG.S8 Dd, Dm
    A64: NEG Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vneg_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vneg_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vnegq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vnegq_f32 (float32x4_t a)
    A32: VNEG.F32 Qd, Qm
    A64: FNEG Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vnegq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vnegq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vnegq_s16 (int16x8_t a)
    A32: VNEG.S16 Qd, Qm
    A64: NEG Vd.8H, Vn.8H
    
    
    Instruction Documentation: [vnegq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vnegq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vnegq_s32 (int32x4_t a)
    A32: VNEG.S32 Qd, Qm
    A64: NEG Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vnegq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vnegq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vnegq_s8 (int8x16_t a)
    A32: VNEG.S8 Qd, Qm
    A64: NEG Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vnegq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vnegs_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vnegs_f32 (float32_t a)
    A32: VNEG.F32 Sd, Sm
    A64: FNEG Sd, Sn The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vnegs_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vnegs_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorn_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vorn_f32 (float32x2_t a, float32x2_t b)
    A32: VORN Dd, Dn, Dm
    A64: ORN Vd.8B, Vn.8B, Vm.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vorn_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorn_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vorn_f64 (float64x1_t a, float64x1_t b)
    A32: VORN Dd, Dn, Dm
    A64: ORN Vd.8B, Vn.8B, Vm.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vorn_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorn_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vorn_s16 (int16x4_t a, int16x4_t b)
    A32: VORN Dd, Dn, Dm
    A64: ORN Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorn_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorn_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vorn_s32 (int32x2_t a, int32x2_t b)
    A32: VORN Dd, Dn, Dm
    A64: ORN Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorn_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorn_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vorn_s64 (int64x1_t a, int64x1_t b)
    A32: VORN Dd, Dn, Dm
    A64: ORN Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorn_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorn_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vorn_s8 (int8x8_t a, int8x8_t b)
    A32: VORN Dd, Dn, Dm
    A64: ORN Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorn_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorn_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vorn_u16 (uint16x4_t a, uint16x4_t b)
    A32: VORN Dd, Dn, Dm
    A64: ORN Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorn_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorn_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vorn_u32 (uint32x2_t a, uint32x2_t b)
    A32: VORN Dd, Dn, Dm
    A64: ORN Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorn_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorn_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vorn_u64 (uint64x1_t a, uint64x1_t b)
    A32: VORN Dd, Dn, Dm
    A64: ORN Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorn_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorn_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vorn_u8 (uint8x8_t a, uint8x8_t b)
    A32: VORN Dd, Dn, Dm
    A64: ORN Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorn_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorn_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vornq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vornq_f32 (float32x4_t a, float32x4_t b)
    A32: VORN Qd, Qn, Qm
    A64: ORN Vd.16B, Vn.16B, Vm.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vornq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vornq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vornq_f64 (float64x2_t a, float64x2_t b)
    A32: VORN Qd, Qn, Qm
    A64: ORN Vd.16B, Vn.16B, Vm.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vornq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vornq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vornq_s16 (int16x8_t a, int16x8_t b)
    A32: VORN Qd, Qn, Qm
    A64: ORN Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vornq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vornq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vornq_s32 (int32x4_t a, int32x4_t b)
    A32: VORN Qd, Qn, Qm
    A64: ORN Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vornq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vornq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vornq_s64 (int64x2_t a, int64x2_t b)
    A32: VORN Qd, Qn, Qm
    A64: ORN Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vornq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vornq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vornq_s8 (int8x16_t a, int8x16_t b)
    A32: VORN Qd, Qn, Qm
    A64: ORN Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vornq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vornq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vornq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VORN Qd, Qn, Qm
    A64: ORN Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vornq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vornq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vornq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VORN Qd, Qn, Qm
    A64: ORN Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vornq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vornq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vornq_u64 (uint64x2_t a, uint64x2_t b)
    A32: VORN Qd, Qn, Qm
    A64: ORN Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vornq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vornq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vornq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VORN Qd, Qn, Qm
    A64: ORN Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vornq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vornq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorr_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vorr_f32 (float32x2_t a, float32x2_t b)
    A32: VORR Dd, Dn, Dm
    A64: ORR Vd.8B, Vn.8B, Vm.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vorr_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorr_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vorr_f64 (float64x1_t a, float64x1_t b)
    A32: VORR Dd, Dn, Dm
    A64: ORR Vd.8B, Vn.8B, Vm.8B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vorr_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorr_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vorr_s16 (int16x4_t a, int16x4_t b)
    A32: VORR Dd, Dn, Dm
    A64: ORR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorr_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorr_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vorr_s32 (int32x2_t a, int32x2_t b)
    A32: VORR Dd, Dn, Dm
    A64: ORR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorr_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorr_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vorr_s64 (int64x1_t a, int64x1_t b)
    A32: VORR Dd, Dn, Dm
    A64: ORR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorr_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorr_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vorr_s8 (int8x8_t a, int8x8_t b)
    A32: VORR Dd, Dn, Dm
    A64: ORR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorr_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorr_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vorr_u16 (uint16x4_t a, uint16x4_t b)
    A32: VORR Dd, Dn, Dm
    A64: ORR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorr_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorr_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vorr_u32 (uint32x2_t a, uint32x2_t b)
    A32: VORR Dd, Dn, Dm
    A64: ORR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorr_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorr_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vorr_u64 (uint64x1_t a, uint64x1_t b)
    A32: VORR Dd, Dn, Dm
    A64: ORR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorr_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorr_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vorr_u8 (uint8x8_t a, uint8x8_t b)
    A32: VORR Dd, Dn, Dm
    A64: ORR Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vorr_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorr_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorrq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vorrq_f32 (float32x4_t a, float32x4_t b)
    A32: VORR Qd, Qn, Qm
    A64: ORR Vd.16B, Vn.16B, Vm.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vorrq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorrq_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vorrq_f64 (float64x2_t a, float64x2_t b)
    A32: VORR Qd, Qn, Qm
    A64: ORR Vd.16B, Vn.16B, Vm.16B The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vorrq_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorrq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vorrq_s16 (int16x8_t a, int16x8_t b)
    A32: VORR Qd, Qn, Qm
    A64: ORR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vorrq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorrq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vorrq_s32 (int32x4_t a, int32x4_t b)
    A32: VORR Qd, Qn, Qm
    A64: ORR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vorrq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorrq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vorrq_s64 (int64x2_t a, int64x2_t b)
    A32: VORR Qd, Qn, Qm
    A64: ORR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vorrq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorrq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vorrq_s8 (int8x16_t a, int8x16_t b)
    A32: VORR Qd, Qn, Qm
    A64: ORR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vorrq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorrq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vorrq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VORR Qd, Qn, Qm
    A64: ORR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vorrq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorrq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vorrq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VORR Qd, Qn, Qm
    A64: ORR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vorrq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorrq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vorrq_u64 (uint64x2_t a, uint64x2_t b)
    A32: VORR Qd, Qn, Qm
    A64: ORR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vorrq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vorrq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vorrq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VORR Qd, Qn, Qm
    A64: ORR Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vorrq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vorrq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadal_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vpadal_s16 (int32x2_t a, int16x4_t b)
    A32: VPADAL.S16 Dd, Dm
    A64: SADALP Vd.2S, Vn.4H
    
    
    Instruction Documentation: [vpadal_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadal_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vpadal_s32 (int64x1_t a, int32x2_t b)
    A32: VPADAL.S32 Dd, Dm
    A64: SADALP Vd.1D, Vn.2S
    
    
    Instruction Documentation: [vpadal_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadal_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vpadal_s8 (int16x4_t a, int8x8_t b)
    A32: VPADAL.S8 Dd, Dm
    A64: SADALP Vd.4H, Vn.8B
    
    
    Instruction Documentation: [vpadal_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadal_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vpadal_u16 (uint32x2_t a, uint16x4_t b)
    A32: VPADAL.U16 Dd, Dm
    A64: UADALP Vd.2S, Vn.4H
    
    
    Instruction Documentation: [vpadal_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadal_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vpadal_u32 (uint64x1_t a, uint32x2_t b)
    A32: VPADAL.U32 Dd, Dm
    A64: UADALP Vd.1D, Vn.2S
    
    
    Instruction Documentation: [vpadal_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadal_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vpadal_u8 (uint16x4_t a, uint8x8_t b)
    A32: VPADAL.U8 Dd, Dm
    A64: UADALP Vd.4H, Vn.8B
    
    
    Instruction Documentation: [vpadal_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadal_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadalq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vpadalq_s16 (int32x4_t a, int16x8_t b)
    A32: VPADAL.S16 Qd, Qm
    A64: SADALP Vd.4S, Vn.8H
    
    
    Instruction Documentation: [vpadalq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadalq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vpadalq_s32 (int64x2_t a, int32x4_t b)
    A32: VPADAL.S32 Qd, Qm
    A64: SADALP Vd.2D, Vn.4S
    
    
    Instruction Documentation: [vpadalq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadalq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vpadalq_s8 (int16x8_t a, int8x16_t b)
    A32: VPADAL.S8 Qd, Qm
    A64: SADALP Vd.8H, Vn.16B
    
    
    Instruction Documentation: [vpadalq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadalq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vpadalq_u16 (uint32x4_t a, uint16x8_t b)
    A32: VPADAL.U16 Qd, Qm
    A64: UADALP Vd.4S, Vn.8H
    
    
    Instruction Documentation: [vpadalq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadalq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vpadalq_u32 (uint64x2_t a, uint32x4_t b)
    A32: VPADAL.U32 Qd, Qm
    A64: UADALP Vd.2D, Vn.4S
    
    
    Instruction Documentation: [vpadalq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadalq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vpadalq_u8 (uint16x8_t a, uint8x16_t b)
    A32: VPADAL.U8 Qd, Qm
    A64: UADALP Vd.8H, Vn.16B
    
    
    Instruction Documentation: [vpadalq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadalq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadd_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vpadd_f32 (float32x2_t a, float32x2_t b)
    A32: VPADD.F32 Dd, Dn, Dm
    A64: FADDP Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vpadd_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadd_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vpadd_s16 (int16x4_t a, int16x4_t b)
    A32: VPADD.I16 Dd, Dn, Dm
    A64: ADDP Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vpadd_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadd_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vpadd_s32 (int32x2_t a, int32x2_t b)
    A32: VPADD.I32 Dd, Dn, Dm
    A64: ADDP Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vpadd_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadd_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vpadd_s8 (int8x8_t a, int8x8_t b)
    A32: VPADD.I8 Dd, Dn, Dm
    A64: ADDP Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vpadd_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadd_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vpadd_u16 (uint16x4_t a, uint16x4_t b)
    A32: VPADD.I16 Dd, Dn, Dm
    A64: ADDP Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vpadd_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadd_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vpadd_u32 (uint32x2_t a, uint32x2_t b)
    A32: VPADD.I32 Dd, Dn, Dm
    A64: ADDP Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vpadd_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpadd_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vpadd_u8 (uint8x8_t a, uint8x8_t b)
    A32: VPADD.I8 Dd, Dn, Dm
    A64: ADDP Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vpadd_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpadd_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddl_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vpaddl_s16 (int16x4_t a)
    A32: VPADDL.S16 Dd, Dm
    A64: SADDLP Vd.2S, Vn.4H
    
    
    Instruction Documentation: [vpaddl_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddl_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vpaddl_s32 (int32x2_t a)
    A32: VPADDL.S32 Dd, Dm
    A64: SADDLP Dd, Vn.2S
    
    
    Instruction Documentation: [vpaddl_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddl_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vpaddl_s8 (int8x8_t a)
    A32: VPADDL.S8 Dd, Dm
    A64: SADDLP Vd.4H, Vn.8B
    
    
    Instruction Documentation: [vpaddl_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddl_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vpaddl_u16 (uint16x4_t a)
    A32: VPADDL.U16 Dd, Dm
    A64: UADDLP Vd.2S, Vn.4H
    
    
    Instruction Documentation: [vpaddl_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddl_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vpaddl_u32 (uint32x2_t a)
    A32: VPADDL.U32 Dd, Dm
    A64: UADDLP Dd, Vn.2S
    
    
    Instruction Documentation: [vpaddl_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddl_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vpaddl_u8 (uint8x8_t a)
    A32: VPADDL.U8 Dd, Dm
    A64: UADDLP Vd.4H, Vn.8B
    
    
    Instruction Documentation: [vpaddl_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddl_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddlq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vpaddlq_s16 (int16x8_t a)
    A32: VPADDL.S16 Qd, Qm
    A64: SADDLP Vd.4S, Vn.8H
    
    
    Instruction Documentation: [vpaddlq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddlq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vpaddlq_s32 (int32x4_t a)
    A32: VPADDL.S32 Qd, Qm
    A64: SADDLP Vd.2D, Vn.4S
    
    
    Instruction Documentation: [vpaddlq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddlq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vpaddlq_s8 (int8x16_t a)
    A32: VPADDL.S8 Qd, Qm
    A64: SADDLP Vd.8H, Vn.16B
    
    
    Instruction Documentation: [vpaddlq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddlq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vpaddlq_u16 (uint16x8_t a)
    A32: VPADDL.U16 Qd, Qm
    A64: UADDLP Vd.4S, Vn.8H
    
    
    Instruction Documentation: [vpaddlq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddlq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vpaddlq_u32 (uint32x4_t a)
    A32: VPADDL.U32 Qd, Qm
    A64: UADDLP Vd.2D, Vn.4S
    
    
    Instruction Documentation: [vpaddlq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpaddlq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vpaddlq_u8 (uint8x16_t a)
    A32: VPADDL.U8 Qd, Qm
    A64: UADDLP Vd.8H, Vn.16B
    
    
    Instruction Documentation: [vpaddlq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpaddlq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmax_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vpmax_f32 (float32x2_t a, float32x2_t b)
    A32: VPMAX.F32 Dd, Dn, Dm
    A64: FMAXP Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vpmax_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmax_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vpmax_s16 (int16x4_t a, int16x4_t b)
    A32: VPMAX.S16 Dd, Dn, Dm
    A64: SMAXP Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vpmax_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmax_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vpmax_s32 (int32x2_t a, int32x2_t b)
    A32: VPMAX.S32 Dd, Dn, Dm
    A64: SMAXP Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vpmax_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmax_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vpmax_s8 (int8x8_t a, int8x8_t b)
    A32: VPMAX.S8 Dd, Dn, Dm
    A64: SMAXP Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vpmax_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmax_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vpmax_u16 (uint16x4_t a, uint16x4_t b)
    A32: VPMAX.U16 Dd, Dn, Dm
    A64: UMAXP Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vpmax_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmax_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vpmax_u32 (uint32x2_t a, uint32x2_t b)
    A32: VPMAX.U32 Dd, Dn, Dm
    A64: UMAXP Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vpmax_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmax_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vpmax_u8 (uint8x8_t a, uint8x8_t b)
    A32: VPMAX.U8 Dd, Dn, Dm
    A64: UMAXP Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vpmax_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmax_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmin_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vpmin_f32 (float32x2_t a, float32x2_t b)
    A32: VPMIN.F32 Dd, Dn, Dm
    A64: FMINP Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vpmin_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmin_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vpmin_s16 (int16x4_t a, int16x4_t b)
    A32: VPMIN.S16 Dd, Dn, Dm
    A64: SMINP Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vpmin_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmin_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vpmin_s32 (int32x2_t a, int32x2_t b)
    A32: VPMIN.S32 Dd, Dn, Dm
    A64: SMINP Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vpmin_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmin_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vpmin_s8 (int8x8_t a, int8x8_t b)
    A32: VPMIN.S8 Dd, Dn, Dm
    A64: SMINP Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vpmin_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmin_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vpmin_u16 (uint16x4_t a, uint16x4_t b)
    A32: VPMIN.U16 Dd, Dn, Dm
    A64: UMINP Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vpmin_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmin_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vpmin_u32 (uint32x2_t a, uint32x2_t b)
    A32: VPMIN.U32 Dd, Dn, Dm
    A64: UMINP Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vpmin_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vpmin_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vpmin_u8 (uint8x8_t a, uint8x8_t b)
    A32: VPMIN.U8 Dd, Dn, Dm
    A64: UMINP Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vpmin_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vpmin_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqabs_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vqabs_s16 (int16x4_t a)
    A32: VQABS.S16 Dd, Dm
    A64: SQABS Vd.4H, Vn.4H
    
    
    Instruction Documentation: [vqabs_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqabs_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vqabs_s32 (int32x2_t a)
    A32: VQABS.S32 Dd, Dm
    A64: SQABS Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vqabs_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqabs_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vqabs_s8 (int8x8_t a)
    A32: VQABS.S8 Dd, Dm
    A64: SQABS Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vqabs_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabs_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqabsq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vqabsq_s16 (int16x8_t a)
    A32: VQABS.S16 Qd, Qm
    A64: SQABS Vd.8H, Vn.8H
    
    
    Instruction Documentation: [vqabsq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqabsq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vqabsq_s32 (int32x4_t a)
    A32: VQABS.S32 Qd, Qm
    A64: SQABS Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vqabsq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqabsq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vqabsq_s8 (int8x16_t a)
    A32: VQABS.S8 Qd, Qm
    A64: SQABS Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vqabsq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqabsq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqadd_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vqadd_s16 (int16x4_t a, int16x4_t b)
    A32: VQADD.S16 Dd, Dn, Dm
    A64: SQADD Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vqadd_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqadd_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vqadd_s32 (int32x2_t a, int32x2_t b)
    A32: VQADD.S32 Dd, Dn, Dm
    A64: SQADD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vqadd_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqadd_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vqadd_s64 (int64x1_t a, int64x1_t b)
    A32: VQADD.S64 Dd, Dn, Dm
    A64: SQADD Dd, Dn, Dm
    
    
    Instruction Documentation: [vqadd_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqadd_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vqadd_s8 (int8x8_t a, int8x8_t b)
    A32: VQADD.S8 Dd, Dn, Dm
    A64: SQADD Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vqadd_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqadd_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vqadd_u16 (uint16x4_t a, uint16x4_t b)
    A32: VQADD.U16 Dd, Dn, Dm
    A64: UQADD Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vqadd_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqadd_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vqadd_u32 (uint32x2_t a, uint32x2_t b)
    A32: VQADD.U32 Dd, Dn, Dm
    A64: UQADD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vqadd_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqadd_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vqadd_u64 (uint64x1_t a, uint64x1_t b)
    A32: VQADD.U64 Dd, Dn, Dm
    A64: UQADD Dd, Dn, Dm
    
    
    Instruction Documentation: [vqadd_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqadd_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqadd_u8 (uint8x8_t a, uint8x8_t b)
    A32: VQADD.U8 Dd, Dn, Dm
    A64: UQADD Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vqadd_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqadd_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vqaddq_s16 (int16x8_t a, int16x8_t b)
    A32: VQADD.S16 Qd, Qn, Qm
    A64: SQADD Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vqaddq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vqaddq_s32 (int32x4_t a, int32x4_t b)
    A32: VQADD.S32 Qd, Qn, Qm
    A64: SQADD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vqaddq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vqaddq_s64 (int64x2_t a, int64x2_t b)
    A32: VQADD.S64 Qd, Qn, Qm
    A64: SQADD Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vqaddq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vqaddq_s8 (int8x16_t a, int8x16_t b)
    A32: VQADD.S8 Qd, Qn, Qm
    A64: SQADD Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vqaddq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vqaddq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VQADD.U16 Qd, Qn, Qm
    A64: UQADD Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vqaddq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vqaddq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VQADD.U32 Qd, Qn, Qm
    A64: UQADD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vqaddq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vqaddq_u64 (uint64x2_t a, uint64x2_t b)
    A32: VQADD.U64 Qd, Qn, Qm
    A64: UQADD Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vqaddq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqaddq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqaddq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VQADD.U8 Qd, Qn, Qm
    A64: UQADD Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vqaddq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqaddq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqneg_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vqneg_s16 (int16x4_t a)
    A32: VQNEG.S16 Dd, Dm
    A64: SQNEG Vd.4H, Vn.4H
    
    
    Instruction Documentation: [vqneg_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqneg_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vqneg_s32 (int32x2_t a)
    A32: VQNEG.S32 Dd, Dm
    A64: SQNEG Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vqneg_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqneg_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vqneg_s8 (int8x8_t a)
    A32: VQNEG.S8 Dd, Dm
    A64: SQNEG Vd.8B, Vn.8B
    
    
    Instruction Documentation: [vqneg_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqneg_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqnegq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vqnegq_s16 (int16x8_t a)
    A32: VQNEG.S16 Qd, Qm
    A64: SQNEG Vd.8H, Vn.8H
    
    
    Instruction Documentation: [vqnegq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqnegq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vqnegq_s32 (int32x4_t a)
    A32: VQNEG.S32 Qd, Qm
    A64: SQNEG Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vqnegq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqnegq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vqnegq_s8 (int8x16_t a)
    A32: VQNEG.S8 Qd, Qm
    A64: SQNEG Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vqnegq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqnegq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshl_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vqrshl_s16 (int16x4_t a, int16x4_t b)
    A32: VQRSHL.S16 Dd, Dn, Dm
    A64: SQRSHL Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vqrshl_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshl_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vqrshl_s32 (int32x2_t a, int32x2_t b)
    A32: VQRSHL.S32 Dd, Dn, Dm
    A64: SQRSHL Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vqrshl_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshl_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vqrshl_s64 (int64x1_t a, int64x1_t b)
    A32: VQRSHL.S64 Dd, Dn, Dm
    A64: SQRSHL Dd, Dn, Dm
    
    
    Instruction Documentation: [vqrshl_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshl_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vqrshl_s8 (int8x8_t a, int8x8_t b)
    A32: VQRSHL.S8 Dd, Dn, Dm
    A64: SQRSHL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vqrshl_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshl_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vqrshl_u16 (uint16x4_t a, int16x4_t b)
    A32: VQRSHL.U16 Dd, Dn, Dm
    A64: UQRSHL Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vqrshl_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshl_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vqrshl_u32 (uint32x2_t a, int32x2_t b)
    A32: VQRSHL.U32 Dd, Dn, Dm
    A64: UQRSHL Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vqrshl_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshl_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vqrshl_u64 (uint64x1_t a, int64x1_t b)
    A32: VQRSHL.U64 Dd, Dn, Dm
    A64: UQRSHL Dd, Dn, Dm
    
    
    Instruction Documentation: [vqrshl_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshl_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqrshl_u8 (uint8x8_t a, int8x8_t b)
    A32: VQRSHL.U8 Dd, Dn, Dm
    A64: UQRSHL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vqrshl_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshl_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vqrshlq_s16 (int16x8_t a, int16x8_t b)
    A32: VQRSHL.S16 Qd, Qn, Qm
    A64: SQRSHL Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vqrshlq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vqrshlq_s32 (int32x4_t a, int32x4_t b)
    A32: VQRSHL.S32 Qd, Qn, Qm
    A64: SQRSHL Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vqrshlq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vqrshlq_s64 (int64x2_t a, int64x2_t b)
    A32: VQRSHL.S64 Qd, Qn, Qm
    A64: SQRSHL Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vqrshlq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vqrshlq_s8 (int8x16_t a, int8x16_t b)
    A32: VQRSHL.S8 Qd, Qn, Qm
    A64: SQRSHL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vqrshlq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vqrshlq_u16 (uint16x8_t a, int16x8_t b)
    A32: VQRSHL.U16 Qd, Qn, Qm
    A64: UQRSHL Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vqrshlq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vqrshlq_u32 (uint32x4_t a, int32x4_t b)
    A32: VQRSHL.U32 Qd, Qn, Qm
    A64: UQRSHL Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vqrshlq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vqrshlq_u64 (uint64x2_t a, int64x2_t b)
    A32: VQRSHL.U64 Qd, Qn, Qm
    A64: UQRSHL Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vqrshlq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshlq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqrshlq_u8 (uint8x16_t a, int8x16_t b)
    A32: VQRSHL.U8 Qd, Qn, Qm
    A64: UQRSHL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vqrshlq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshlq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_high_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vqrshrn_high_n_s16 (int8x8_t r, int16x8_t a, const int n)
    A32: VQRSHRN.S16 Dd+1, Dn, #n
    A64: SQRSHRN2 Vd.16B, Vn.8H, #n
    
    
    Instruction Documentation: [vqrshrn_high_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_high_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vqrshrn_high_n_s32 (int16x4_t r, int32x4_t a, const int n)
    A32: VQRSHRN.S32 Dd+1, Dn, #n
    A64: SQRSHRN2 Vd.8H, Vn.4S, #n
    
    
    Instruction Documentation: [vqrshrn_high_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_high_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vqrshrn_high_n_s64 (int32x2_t r, int64x2_t a, const int n)
    A32: VQRSHRN.S64 Dd+1, Dn, #n
    A64: SQRSHRN2 Vd.4S, Vn.2D, #n
    
    
    Instruction Documentation: [vqrshrn_high_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_high_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqrshrn_high_n_u16 (uint8x8_t r, uint16x8_t a, const int n)
    A32: VQRSHRN.U16 Dd+1, Dn, #n
    A64: UQRSHRN2 Vd.16B, Vn.8H, #n
    
    
    Instruction Documentation: [vqrshrn_high_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_high_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vqrshrn_high_n_u32 (uint16x4_t r, uint32x4_t a, const int n)
    A32: VQRSHRN.U32 Dd+1, Dn, #n
    A64: UQRSHRN2 Vd.8H, Vn.4S, #n
    
    
    Instruction Documentation: [vqrshrn_high_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_high_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vqrshrn_high_n_u64 (uint32x2_t r, uint64x2_t a, const int n)
    A32: VQRSHRN.U64 Dd+1, Dn, #n
    A64: UQRSHRN2 Vd.4S, Vn.2D, #n
    
    
    Instruction Documentation: [vqrshrn_high_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_high_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vqrshrn_n_s16 (int16x8_t a, const int n)
    A32: VQRSHRN.S16 Dd, Qm, #n
    A64: SQRSHRN Vd.8B, Vn.8H, #n
    
    
    Instruction Documentation: [vqrshrn_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vqrshrn_n_s32 (int32x4_t a, const int n)
    A32: VQRSHRN.S32 Dd, Qm, #n
    A64: SQRSHRN Vd.4H, Vn.4S, #n
    
    
    Instruction Documentation: [vqrshrn_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vqrshrn_n_s64 (int64x2_t a, const int n)
    A32: VQRSHRN.S64 Dd, Qm, #n
    A64: SQRSHRN Vd.2S, Vn.2D, #n
    
    
    Instruction Documentation: [vqrshrn_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqrshrn_n_u16 (uint16x8_t a, const int n)
    A32: VQRSHRN.U16 Dd, Qm, #n
    A64: UQRSHRN Vd.8B, Vn.8H, #n
    
    
    Instruction Documentation: [vqrshrn_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vqrshrn_n_u32 (uint32x4_t a, const int n)
    A32: VQRSHRN.U32 Dd, Qm, #n
    A64: UQRSHRN Vd.4H, Vn.4S, #n
    
    
    Instruction Documentation: [vqrshrn_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrn_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vqrshrn_n_u64 (uint64x2_t a, const int n)
    A32: VQRSHRN.U64 Dd, Qm, #n
    A64: UQRSHRN Vd.2S, Vn.2D, #n
    
    
    Instruction Documentation: [vqrshrn_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrn_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrun_high_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqrshrun_high_n_s16 (uint8x8_t r, int16x8_t a, const int n)
    A32: VQRSHRUN.S16 Dd+1, Dn, #n
    A64: SQRSHRUN2 Vd.16B, Vn.8H, #n
    
    
    Instruction Documentation: [vqrshrun_high_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrun_high_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vqrshrun_high_n_s32 (uint16x4_t r, int32x4_t a, const int n)
    A32: VQRSHRUN.S32 Dd+1, Dn, #n
    A64: SQRSHRUN2 Vd.8H, Vn.4S, #n
    
    
    Instruction Documentation: [vqrshrun_high_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrun_high_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vqrshrun_high_n_s64 (uint32x2_t r, int64x2_t a, const int n)
    A32: VQRSHRUN.S64 Dd+1, Dn, #n
    A64: SQRSHRUN2 Vd.4S, Vn.2D, #n
    
    
    Instruction Documentation: [vqrshrun_high_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_high_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrun_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqrshrun_n_s16 (int16x8_t a, const int n)
    A32: VQRSHRUN.S16 Dd, Qm, #n
    A64: SQRSHRUN Vd.8B, Vn.8H, #n
    
    
    Instruction Documentation: [vqrshrun_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrun_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vqrshrun_n_s32 (int32x4_t a, const int n)
    A32: VQRSHRUN.S32 Dd, Qm, #n
    A64: SQRSHRUN Vd.4H, Vn.4S, #n
    
    
    Instruction Documentation: [vqrshrun_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqrshrun_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vqrshrun_n_s64 (int64x2_t a, const int n)
    A32: VQRSHRUN.S64 Dd, Qm, #n
    A64: SQRSHRUN Vd.2S, Vn.2D, #n
    
    
    Instruction Documentation: [vqrshrun_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqrshrun_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vqshl_n_s16 (int16x4_t a, const int n)
    A32: VQSHL.S16 Dd, Dm, #n
    A64: SQSHL Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vqshl_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vqshl_n_s32 (int32x2_t a, const int n)
    A32: VQSHL.S32 Dd, Dm, #n
    A64: SQSHL Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vqshl_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vqshl_n_s64 (int64x1_t a, const int n)
    A32: VQSHL.S64 Dd, Dm, #n
    A64: SQSHL Dd, Dn, #n
    
    
    Instruction Documentation: [vqshl_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vqshl_n_s8 (int8x8_t a, const int n)
    A32: VQSHL.S8 Dd, Dm, #n
    A64: SQSHL Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vqshl_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vqshl_n_u16 (uint16x4_t a, const int n)
    A32: VQSHL.U16 Dd, Dm, #n
    A64: UQSHL Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vqshl_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vqshl_n_u32 (uint32x2_t a, const int n)
    A32: VQSHL.U32 Dd, Dm, #n
    A64: UQSHL Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vqshl_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vqshl_n_u64 (uint64x1_t a, const int n)
    A32: VQSHL.U64 Dd, Dm, #n
    A64: UQSHL Dd, Dn, #n
    
    
    Instruction Documentation: [vqshl_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqshl_n_u8 (uint8x8_t a, const int n)
    A32: VQSHL.U8 Dd, Dm, #n
    A64: UQSHL Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vqshl_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vqshl_s16 (int16x4_t a, int16x4_t b)
    A32: VQSHL.S16 Dd, Dn, Dm
    A64: SQSHL Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vqshl_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vqshl_s32 (int32x2_t a, int32x2_t b)
    A32: VQSHL.S32 Dd, Dn, Dm
    A64: SQSHL Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vqshl_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vqshl_s64 (int64x1_t a, int64x1_t b)
    A32: VQSHL.S64 Dd, Dn, Dm
    A64: SQSHL Dd, Dn, Dm
    
    
    Instruction Documentation: [vqshl_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vqshl_s8 (int8x8_t a, int8x8_t b)
    A32: VQSHL.S8 Dd, Dn, Dm
    A64: SQSHL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vqshl_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vqshl_u16 (uint16x4_t a, int16x4_t b)
    A32: VQSHL.U16 Dd, Dn, Dm
    A64: UQSHL Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vqshl_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vqshl_u32 (uint32x2_t a, int32x2_t b)
    A32: VQSHL.U32 Dd, Dn, Dm
    A64: UQSHL Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vqshl_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vqshl_u64 (uint64x1_t a, int64x1_t b)
    A32: VQSHL.U64 Dd, Dn, Dm
    A64: UQSHL Dd, Dn, Dm
    
    
    Instruction Documentation: [vqshl_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshl_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqshl_u8 (uint8x8_t a, int8x8_t b)
    A32: VQSHL.U8 Dd, Dn, Dm
    A64: UQSHL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vqshl_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshl_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vqshlq_n_s16 (int16x8_t a, const int n)
    A32: VQSHL.S16 Qd, Qm, #n
    A64: SQSHL Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vqshlq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vqshlq_n_s32 (int32x4_t a, const int n)
    A32: VQSHL.S32 Qd, Qm, #n
    A64: SQSHL Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vqshlq_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vqshlq_n_s64 (int64x2_t a, const int n)
    A32: VQSHL.S64 Qd, Qm, #n
    A64: SQSHL Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vqshlq_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vqshlq_n_s8 (int8x16_t a, const int n)
    A32: VQSHL.S8 Qd, Qm, #n
    A64: SQSHL Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vqshlq_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vqshlq_n_u16 (uint16x8_t a, const int n)
    A32: VQSHL.U16 Qd, Qm, #n
    A64: UQSHL Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vqshlq_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vqshlq_n_u32 (uint32x4_t a, const int n)
    A32: VQSHL.U32 Qd, Qm, #n
    A64: UQSHL Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vqshlq_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vqshlq_n_u64 (uint64x2_t a, const int n)
    A32: VQSHL.U64 Qd, Qm, #n
    A64: UQSHL Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vqshlq_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqshlq_n_u8 (uint8x16_t a, const int n)
    A32: VQSHL.U8 Qd, Qm, #n
    A64: UQSHL Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vqshlq_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vqshlq_s16 (int16x8_t a, int16x8_t b)
    A32: VQSHL.S16 Qd, Qn, Qm
    A64: SQSHL Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vqshlq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vqshlq_s32 (int32x4_t a, int32x4_t b)
    A32: VQSHL.S32 Qd, Qn, Qm
    A64: SQSHL Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vqshlq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vqshlq_s64 (int64x2_t a, int64x2_t b)
    A32: VQSHL.S64 Qd, Qn, Qm
    A64: SQSHL Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vqshlq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vqshlq_s8 (int8x16_t a, int8x16_t b)
    A32: VQSHL.S8 Qd, Qn, Qm
    A64: SQSHL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vqshlq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vqshlq_u16 (uint16x8_t a, int16x8_t b)
    A32: VQSHL.U16 Qd, Qn, Qm
    A64: UQSHL Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vqshlq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vqshlq_u32 (uint32x4_t a, int32x4_t b)
    A32: VQSHL.U32 Qd, Qn, Qm
    A64: UQSHL Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vqshlq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vqshlq_u64 (uint64x2_t a, int64x2_t b)
    A32: VQSHL.U64 Qd, Qn, Qm
    A64: UQSHL Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vqshlq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqshlq_u8 (uint8x16_t a, int8x16_t b)
    A32: VQSHL.U8 Qd, Qn, Qm
    A64: UQSHL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vqshlq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlu_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vqshlu_n_s16 (int16x4_t a, const int n)
    A32: VQSHLU.S16 Dd, Dm, #n
    A64: SQSHLU Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vqshlu_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlu_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vqshlu_n_s32 (int32x2_t a, const int n)
    A32: VQSHLU.S32 Dd, Dm, #n
    A64: SQSHLU Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vqshlu_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlu_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vqshlu_n_s64 (int64x1_t a, const int n)
    A32: VQSHLU.S64 Dd, Dm, #n
    A64: SQSHLU Dd, Dn, #n
    
    
    Instruction Documentation: [vqshlu_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshlu_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqshlu_n_s8 (int8x8_t a, const int n)
    A32: VQSHLU.S8 Dd, Dm, #n
    A64: SQSHLU Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vqshlu_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshlu_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshluq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vqshluq_n_s16 (int16x8_t a, const int n)
    A32: VQSHLU.S16 Qd, Qm, #n
    A64: SQSHLU Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vqshluq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshluq_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vqshluq_n_s32 (int32x4_t a, const int n)
    A32: VQSHLU.S32 Qd, Qm, #n
    A64: SQSHLU Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vqshluq_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshluq_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vqshluq_n_s64 (int64x2_t a, const int n)
    A32: VQSHLU.S64 Qd, Qm, #n
    A64: SQSHLU Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vqshluq_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshluq_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqshluq_n_s8 (int8x16_t a, const int n)
    A32: VQSHLU.S8 Qd, Qm, #n
    A64: SQSHLU Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vqshluq_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshluq_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_high_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vqshrn_high_n_s16 (int8x8_t r, int16x8_t a, const int n)
    A32: VQSHRN.S16 Dd+1, Qm, #n
    A64: SQSHRN2 Vd.16B, Vn.8H, #n
    
    
    Instruction Documentation: [vqshrn_high_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_high_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vqshrn_high_n_s32 (int16x4_t r, int32x4_t a, const int n)
    A32: VQSHRN.S32 Dd+1, Qm, #n
    A64: SQSHRN2 Vd.8H, Vn.4S, #n
    
    
    Instruction Documentation: [vqshrn_high_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_high_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vqshrn_high_n_s64 (int32x2_t r, int64x2_t a, const int n)
    A32: VQSHRN.S64 Dd+1, Qm, #n
    A64: SQSHRN2 Vd.4S, Vn.2D, #n
    
    
    Instruction Documentation: [vqshrn_high_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_high_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqshrn_high_n_u16 (uint8x8_t r, uint16x8_t a, const int n)
    A32: VQSHRN.U16 Dd+1, Qm, #n
    A64: UQSHRN2 Vd.16B, Vn.8H, #n
    
    
    Instruction Documentation: [vqshrn_high_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_high_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vqshrn_high_n_u32 (uint16x4_t r, uint32x4_t a, const int n)
    A32: VQSHRN.U32 Dd+1, Qm, #n
    A64: UQSHRN2 Vd.8H, Vn.4S, #n
    
    
    Instruction Documentation: [vqshrn_high_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_high_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vqshrn_high_n_u64 (uint32x2_t r, uint64x2_t a, const int n)
    A32: VQSHRN.U64 Dd+1, Qm, #n
    A64: UQSHRN2 Vd.4S, Vn.2D, #n
    
    
    Instruction Documentation: [vqshrn_high_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_high_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vqshrn_n_s16 (int16x8_t a, const int n)
    A32: VQSHRN.S16 Dd, Qm, #n
    A64: SQSHRN Vd.8B, Vn.8H, #n
    
    
    Instruction Documentation: [vqshrn_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vqshrn_n_s32 (int32x4_t a, const int n)
    A32: VQSHRN.S32 Dd, Qm, #n
    A64: SQSHRN Vd.4H, Vn.4S, #n
    
    
    Instruction Documentation: [vqshrn_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vqshrn_n_s64 (int64x2_t a, const int n)
    A32: VQSHRN.S64 Dd, Qm, #n
    A64: SQSHRN Vd.2S, Vn.2D, #n
    
    
    Instruction Documentation: [vqshrn_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqshrn_n_u16 (uint16x8_t a, const int n)
    A32: VQSHRN.U16 Dd, Qm, #n
    A64: UQSHRN Vd.8B, Vn.8H, #n
    
    
    Instruction Documentation: [vqshrn_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vqshrn_n_u32 (uint32x4_t a, const int n)
    A32: VQSHRN.U32 Dd, Qm, #n
    A64: UQSHRN Vd.4H, Vn.4S, #n
    
    
    Instruction Documentation: [vqshrn_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrn_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vqshrn_n_u64 (uint64x2_t a, const int n)
    A32: VQSHRN.U64 Dd, Qm, #n
    A64: UQSHRN Vd.2S, Vn.2D, #n
    
    
    Instruction Documentation: [vqshrn_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrn_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrun_high_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqshrun_high_n_s16 (uint8x8_t r, int16x8_t a, const int n)
    A32: VQSHRUN.S16 Dd+1, Dn, #n
    A64: SQSHRUN2 Vd.16B, Vn.8H, #n
    
    
    Instruction Documentation: [vqshrun_high_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrun_high_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vqshrun_high_n_s32 (uint16x4_t r, int32x4_t a, const int n)
    A32: VQSHRUN.S32 Dd+1, Dn, #n
    A64: SQSHRUN2 Vd.8H, Vn.4S, #n
    
    
    Instruction Documentation: [vqshrun_high_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrun_high_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vqshrun_high_n_s64 (uint32x2_t r, int64x2_t a, const int n)
    A32: VQSHRUN.S64 Dd+1, Dn, #n
    A64: SQSHRUN2 Vd.4S, Vn.2D, #n
    
    
    Instruction Documentation: [vqshrun_high_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_high_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrun_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqshrun_n_s16 (int16x8_t a, const int n)
    A32: VQSHRUN.S16 Dd, Qm, #n
    A64: SQSHRUN Vd.8B, Vn.8H, #n
    
    
    Instruction Documentation: [vqshrun_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrun_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vqshrun_n_s32 (int32x4_t a, const int n)
    A32: VQSHRUN.S32 Dd, Qm, #n
    A64: SQSHRUN Vd.4H, Vn.4S, #n
    
    
    Instruction Documentation: [vqshrun_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqshrun_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vqshrun_n_s64 (int64x2_t a, const int n)
    A32: VQSHRUN.S64 Dd, Qm, #n
    A64: SQSHRUN Vd.2S, Vn.2D, #n
    
    
    Instruction Documentation: [vqshrun_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqshrun_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsub_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vqsub_s16 (int16x4_t a, int16x4_t b)
    A32: VQSUB.S16 Dd, Dn, Dm
    A64: SQSUB Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vqsub_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsub_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vqsub_s32 (int32x2_t a, int32x2_t b)
    A32: VQSUB.S32 Dd, Dn, Dm
    A64: SQSUB Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vqsub_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsub_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vqsub_s64 (int64x1_t a, int64x1_t b)
    A32: VQSUB.S64 Dd, Dn, Dm
    A64: SQSUB Dd, Dn, Dm
    
    
    Instruction Documentation: [vqsub_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsub_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vqsub_s8 (int8x8_t a, int8x8_t b)
    A32: VQSUB.S8 Dd, Dn, Dm
    A64: SQSUB Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vqsub_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsub_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vqsub_u16 (uint16x4_t a, uint16x4_t b)
    A32: VQSUB.U16 Dd, Dn, Dm
    A64: UQSUB Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vqsub_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsub_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vqsub_u32 (uint32x2_t a, uint32x2_t b)
    A32: VQSUB.U32 Dd, Dn, Dm
    A64: UQSUB Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vqsub_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsub_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vqsub_u64 (uint64x1_t a, uint64x1_t b)
    A32: VQSUB.U64 Dd, Dn, Dm
    A64: UQSUB Dd, Dn, Dm
    
    
    Instruction Documentation: [vqsub_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsub_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqsub_u8 (uint8x8_t a, uint8x8_t b)
    A32: VQSUB.U8 Dd, Dn, Dm
    A64: UQSUB Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vqsub_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsub_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vqsubq_s16 (int16x8_t a, int16x8_t b)
    A32: VQSUB.S16 Qd, Qn, Qm
    A64: SQSUB Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vqsubq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vqsubq_s32 (int32x4_t a, int32x4_t b)
    A32: VQSUB.S32 Qd, Qn, Qm
    A64: SQSUB Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vqsubq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vqsubq_s64 (int64x2_t a, int64x2_t b)
    A32: VQSUB.S64 Qd, Qn, Qm
    A64: SQSUB Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vqsubq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vqsubq_s8 (int8x16_t a, int8x16_t b)
    A32: VQSUB.S8 Qd, Qn, Qm
    A64: SQSUB Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vqsubq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vqsubq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VQSUB.U16 Qd, Qn, Qm
    A64: UQSUB Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vqsubq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vqsubq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VQSUB.U32 Qd, Qn, Qm
    A64: UQSUB Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vqsubq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vqsubq_u64 (uint64x2_t a, uint64x2_t b)
    A32: VQSUB.U64 Qd, Qn, Qm
    A64: UQSUB Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vqsubq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqsubq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vqsubq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VQSUB.U8 Qd, Qn, Qm
    A64: UQSUB Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vqsubq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqsubq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqvtbl1_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vqvtbl1_s8(int8x16_t t, uint8x8_t idx)
    A32: VTBL Dd, {Dn, Dn+1}, Dm
    A64: TBL Vd.8B, {Vn.16B}, Vm.8B
    
    
    Instruction Documentation: [vqvtbl1_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqvtbl1_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqvtbl1_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqvtbl1_u8(uint8x16_t t, uint8x8_t idx)
    A32: VTBL Dd, {Dn, Dn+1}, Dm
    A64: TBL Vd.8B, {Vn.16B}, Vm.8B
    
    
    Instruction Documentation: [vqvtbl1_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqvtbl1_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqvtbx1_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vqvtbx1_s8(int8x8_t r, int8x16_t t, uint8x8_t idx)
    A32: VTBX Dd, {Dn, Dn+1}, Dm
    A64: TBX Vd.8B, {Vn.16B}, Vm.8B
    
    
    Instruction Documentation: [vqvtbx1_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqvtbx1_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vqvtbx1_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vqvtbx1_u8(uint8x8_t r, uint8x16_t t, uint8x8_t idx)
    A32: VTBX Dd, {Dn, Dn+1}, Dm
    A64: TBX Vd.8B, {Vn.16B}, Vm.8B
    
    
    Instruction Documentation: [vqvtbx1_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vqvtbx1_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vraddhn_high_s16 (int8x8_t r, int16x8_t a, int16x8_t b)
    A32: VRADDHN.I16 Dd+1, Qn, Qm
    A64: RADDHN2 Vd.16B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vraddhn_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vraddhn_high_s32 (int16x4_t r, int32x4_t a, int32x4_t b)
    A32: VRADDHN.I32 Dd+1, Qn, Qm
    A64: RADDHN2 Vd.8H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vraddhn_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_high_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vraddhn_high_s64 (int32x2_t r, int64x2_t a, int64x2_t b)
    A32: VRADDHN.I64 Dd+1, Qn, Qm
    A64: RADDHN2 Vd.4S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vraddhn_high_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vraddhn_high_u16 (uint8x8_t r, uint16x8_t a, uint16x8_t b)
    A32: VRADDHN.I16 Dd+1, Qn, Qm
    A64: RADDHN2 Vd.16B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vraddhn_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vraddhn_high_u32 (uint16x4_t r, uint32x4_t a, uint32x4_t b)
    A32: VRADDHN.I32 Dd+1, Qn, Qm
    A64: RADDHN2 Vd.8H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vraddhn_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_high_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vraddhn_high_u64 (uint32x2_t r, uint64x2_t a, uint64x2_t b)
    A32: VRADDHN.I64 Dd+1, Qn, Qm
    A64: RADDHN2 Vd.4S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vraddhn_high_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_high_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vraddhn_s16 (int16x8_t a, int16x8_t b)
    A32: VRADDHN.I16 Dd, Qn, Qm
    A64: RADDHN Vd.8B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vraddhn_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vraddhn_s32 (int32x4_t a, int32x4_t b)
    A32: VRADDHN.I32 Dd, Qn, Qm
    A64: RADDHN Vd.4H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vraddhn_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vraddhn_s64 (int64x2_t a, int64x2_t b)
    A32: VRADDHN.I64 Dd, Qn, Qm
    A64: RADDHN Vd.2S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vraddhn_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vraddhn_u16 (uint16x8_t a, uint16x8_t b)
    A32: VRADDHN.I16 Dd, Qn, Qm
    A64: RADDHN Vd.8B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vraddhn_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vraddhn_u32 (uint32x4_t a, uint32x4_t b)
    A32: VRADDHN.I32 Dd, Qn, Qm
    A64: RADDHN Vd.4H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vraddhn_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vraddhn_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vraddhn_u64 (uint64x2_t a, uint64x2_t b)
    A32: VRADDHN.I64 Dd, Qn, Qm
    A64: RADDHN Vd.2S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vraddhn_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vraddhn_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpe_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vrecpe_f32 (float32x2_t a)
    A32: VRECPE.F32 Dd, Dm
    A64: FRECPE Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vrecpe_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpe_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vrecpe_u32 (uint32x2_t a)
    A32: VRECPE.U32 Dd, Dm
    A64: URECPE Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vrecpe_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpe_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpeq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vrecpeq_f32 (float32x4_t a)
    A32: VRECPE.F32 Qd, Qm
    A64: FRECPE Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vrecpeq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpeq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vrecpeq_u32 (uint32x4_t a)
    A32: VRECPE.U32 Qd, Qm
    A64: URECPE Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vrecpeq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpeq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecps_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vrecps_f32 (float32x2_t a, float32x2_t b)
    A32: VRECPS.F32 Dd, Dn, Dm
    A64: FRECPS Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vrecps_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecps_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrecpsq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vrecpsq_f32 (float32x4_t a, float32x4_t b)
    A32: VRECPS.F32 Qd, Qn, Qm
    A64: FRECPS Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vrecpsq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrecpsq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhadd_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vrhadd_s16 (int16x4_t a, int16x4_t b)
    A32: VRHADD.S16 Dd, Dn, Dm
    A64: SRHADD Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vrhadd_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhadd_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vrhadd_s32 (int32x2_t a, int32x2_t b)
    A32: VRHADD.S32 Dd, Dn, Dm
    A64: SRHADD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vrhadd_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhadd_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vrhadd_s8 (int8x8_t a, int8x8_t b)
    A32: VRHADD.S8 Dd, Dn, Dm
    A64: SRHADD Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vrhadd_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhadd_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vrhadd_u16 (uint16x4_t a, uint16x4_t b)
    A32: VRHADD.U16 Dd, Dn, Dm
    A64: URHADD Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vrhadd_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhadd_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vrhadd_u32 (uint32x2_t a, uint32x2_t b)
    A32: VRHADD.U32 Dd, Dn, Dm
    A64: URHADD Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vrhadd_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhadd_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vrhadd_u8 (uint8x8_t a, uint8x8_t b)
    A32: VRHADD.U8 Dd, Dn, Dm
    A64: URHADD Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vrhadd_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhadd_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhaddq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vrhaddq_s16 (int16x8_t a, int16x8_t b)
    A32: VRHADD.S16 Qd, Qn, Qm
    A64: SRHADD Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vrhaddq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhaddq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vrhaddq_s32 (int32x4_t a, int32x4_t b)
    A32: VRHADD.S32 Qd, Qn, Qm
    A64: SRHADD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vrhaddq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhaddq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vrhaddq_s8 (int8x16_t a, int8x16_t b)
    A32: VRHADD.S8 Qd, Qn, Qm
    A64: SRHADD Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vrhaddq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhaddq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vrhaddq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VRHADD.U16 Qd, Qn, Qm
    A64: URHADD Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vrhaddq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhaddq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vrhaddq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VRHADD.U32 Qd, Qn, Qm
    A64: URHADD Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vrhaddq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrhaddq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vrhaddq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VRHADD.U8 Qd, Qn, Qm
    A64: URHADD Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vrhaddq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrhaddq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrnd_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vrnd_f32 (float32x2_t a)
    A32: VRINTZ.F32 Dd, Dm
    A64: FRINTZ Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vrnd_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrnd_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vrnd_f64 (float64x1_t a)
    A32: VRINTZ.F64 Dd, Dm
    A64: FRINTZ Dd, Dn
    
    
    Instruction Documentation: [vrnd_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnd_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrnda_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vrnda_f32 (float32x2_t a)
    A32: VRINTA.F32 Dd, Dm
    A64: FRINTA Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vrnda_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrnda_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vrnda_f64 (float64x1_t a)
    A32: VRINTA.F64 Dd, Dm
    A64: FRINTA Dd, Dn
    
    
    Instruction Documentation: [vrnda_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnda_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndaq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vrndaq_f32 (float32x4_t a)
    A32: VRINTA.F32 Qd, Qm
    A64: FRINTA Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vrndaq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndaq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndas_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vrndas_f32 (float32_t a)
    A32: VRINTA.F32 Sd, Sm
    A64: FRINTA Sd, Sn The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vrndas_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndas_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndm_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vrndm_f32 (float32x2_t a)
    A32: VRINTM.F32 Dd, Dm
    A64: FRINTM Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vrndm_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndm_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vrndm_f64 (float64x1_t a)
    A32: VRINTM.F64 Dd, Dm
    A64: FRINTM Dd, Dn
    
    
    Instruction Documentation: [vrndm_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndm_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndmq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vrndmq_f32 (float32x4_t a)
    A32: VRINTM.F32 Qd, Qm
    A64: FRINTM Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vrndmq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndmq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndms_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vrndms_f32 (float32_t a)
    A32: VRINTM.F32 Sd, Sm
    A64: FRINTM Sd, Sn The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vrndms_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndms_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndn_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vrndn_f32 (float32x2_t a)
    A32: VRINTN.F32 Dd, Dm
    A64: FRINTN Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vrndn_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndn_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vrndn_f64 (float64x1_t a)
    A32: VRINTN.F64 Dd, Dm
    A64: FRINTN Dd, Dn
    
    
    Instruction Documentation: [vrndn_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndn_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndnq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vrndnq_f32 (float32x4_t a)
    A32: VRINTN.F32 Qd, Qm
    A64: FRINTN Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vrndnq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndnq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndns_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vrndns_f32 (float32_t a)
    A32: VRINTN.F32 Sd, Sm
    A64: FRINTN Sd, Sn The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vrndns_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndns_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndp_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vrndp_f32 (float32x2_t a)
    A32: VRINTP.F32 Dd, Dm
    A64: FRINTP Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vrndp_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndp_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vrndp_f64 (float64x1_t a)
    A32: VRINTP.F64 Dd, Dm
    A64: FRINTP Dd, Dn
    
    
    Instruction Documentation: [vrndp_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndp_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndpq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vrndpq_f32 (float32x4_t a)
    A32: VRINTP.F32 Qd, Qm
    A64: FRINTP Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vrndpq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndpq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndps_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vrndps_f32 (float32_t a)
    A32: VRINTP.F32 Sd, Sm
    A64: FRINTP Sd, Sn The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vrndps_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndps_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrndq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vrndq_f32 (float32x4_t a)
    A32: VRINTZ.F32 Qd, Qm
    A64: FRINTZ Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vrndq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrndq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrnds_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vrnds_f32 (float32_t a)
    A32: VRINTZ.F32 Sd, Sm
    A64: FRINTZ Sd, Sn The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vrnds_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrnds_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshl_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vrshl_s16 (int16x4_t a, int16x4_t b)
    A32: VRSHL.S16 Dd, Dn, Dm
    A64: SRSHL Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vrshl_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshl_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vrshl_s32 (int32x2_t a, int32x2_t b)
    A32: VRSHL.S32 Dd, Dn, Dm
    A64: SRSHL Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vrshl_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshl_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vrshl_s64 (int64x1_t a, int64x1_t b)
    A32: VRSHL.S64 Dd, Dn, Dm
    A64: SRSHL Dd, Dn, Dm
    
    
    Instruction Documentation: [vrshl_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshl_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vrshl_s8 (int8x8_t a, int8x8_t b)
    A32: VRSHL.S8 Dd, Dn, Dm
    A64: SRSHL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vrshl_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshl_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vrshl_u16 (uint16x4_t a, int16x4_t b)
    A32: VRSHL.U16 Dd, Dn, Dm
    A64: URSHL Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vrshl_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshl_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vrshl_u32 (uint32x2_t a, int32x2_t b)
    A32: VRSHL.U32 Dd, Dn, Dm
    A64: URSHL Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vrshl_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshl_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vrshl_u64 (uint64x1_t a, int64x1_t b)
    A32: VRSHL.U64 Dd, Dn, Dm
    A64: URSHL Dd, Dn, Dm
    
    
    Instruction Documentation: [vrshl_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshl_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vrshl_u8 (uint8x8_t a, int8x8_t b)
    A32: VRSHL.U8 Dd, Dn, Dm
    A64: URSHL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vrshl_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshl_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshlq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vrshlq_s16 (int16x8_t a, int16x8_t b)
    A32: VRSHL.S16 Qd, Qn, Qm
    A64: SRSHL Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vrshlq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshlq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vrshlq_s32 (int32x4_t a, int32x4_t b)
    A32: VRSHL.S32 Qd, Qn, Qm
    A64: SRSHL Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vrshlq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshlq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vrshlq_s64 (int64x2_t a, int64x2_t b)
    A32: VRSHL.S64 Qd, Qn, Qm
    A64: SRSHL Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vrshlq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshlq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vrshlq_s8 (int8x16_t a, int8x16_t b)
    A32: VRSHL.S8 Qd, Qn, Qm
    A64: SRSHL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vrshlq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshlq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vrshlq_u16 (uint16x8_t a, int16x8_t b)
    A32: VRSHL.U16 Qd, Qn, Qm
    A64: URSHL Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vrshlq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshlq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vrshlq_u32 (uint32x4_t a, int32x4_t b)
    A32: VRSHL.U32 Qd, Qn, Qm
    A64: URSHL Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vrshlq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshlq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vrshlq_u64 (uint64x2_t a, int64x2_t b)
    A32: VRSHL.U64 Qd, Qn, Qm
    A64: URSHL Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vrshlq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshlq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vrshlq_u8 (uint8x16_t a, int8x16_t b)
    A32: VRSHL.U8 Qd, Qn, Qm
    A64: URSHL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vrshlq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshlq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshr_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vrshr_n_s16 (int16x4_t a, const int n)
    A32: VRSHR.S16 Dd, Dm, #n
    A64: SRSHR Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vrshr_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshr_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vrshr_n_s32 (int32x2_t a, const int n)
    A32: VRSHR.S32 Dd, Dm, #n
    A64: SRSHR Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vrshr_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshr_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vrshr_n_s64 (int64x1_t a, const int n)
    A32: VRSHR.S64 Dd, Dm, #n
    A64: SRSHR Dd, Dn, #n
    
    
    Instruction Documentation: [vrshr_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshr_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vrshr_n_s8 (int8x8_t a, const int n)
    A32: VRSHR.S8 Dd, Dm, #n
    A64: SRSHR Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vrshr_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshr_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vrshr_n_u16 (uint16x4_t a, const int n)
    A32: VRSHR.U16 Dd, Dm, #n
    A64: URSHR Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vrshr_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshr_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vrshr_n_u32 (uint32x2_t a, const int n)
    A32: VRSHR.U32 Dd, Dm, #n
    A64: URSHR Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vrshr_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshr_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vrshr_n_u64 (uint64x1_t a, const int n)
    A32: VRSHR.U64 Dd, Dm, #n
    A64: URSHR Dd, Dn, #n
    
    
    Instruction Documentation: [vrshr_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshr_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vrshr_n_u8 (uint8x8_t a, const int n)
    A32: VRSHR.U8 Dd, Dm, #n
    A64: URSHR Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vrshr_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshr_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_high_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vrshrn_high_n_s16 (int8x8_t r, int16x8_t a, const int n)
    A32: VRSHRN.I16 Dd+1, Qm, #n
    A64: RSHRN2 Vd.16B, Vn.8H, #n
    
    
    Instruction Documentation: [vrshrn_high_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_high_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vrshrn_high_n_s32 (int16x4_t r, int32x4_t a, const int n)
    A32: VRSHRN.I32 Dd+1, Qm, #n
    A64: RSHRN2 Vd.8H, Vn.4S, #n
    
    
    Instruction Documentation: [vrshrn_high_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_high_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vrshrn_high_n_s64 (int32x2_t r, int64x2_t a, const int n)
    A32: VRSHRN.I64 Dd+1, Qm, #n
    A64: RSHRN2 Vd.4S, Vn.2D, #n
    
    
    Instruction Documentation: [vrshrn_high_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_high_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vrshrn_high_n_u16 (uint8x8_t r, uint16x8_t a, const int n)
    A32: VRSHRN.I16 Dd+1, Qm, #n
    A64: RSHRN2 Vd.16B, Vn.8H, #n
    
    
    Instruction Documentation: [vrshrn_high_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_high_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vrshrn_high_n_u32 (uint16x4_t r, uint32x4_t a, const int n)
    A32: VRSHRN.I32 Dd+1, Qm, #n
    A64: RSHRN2 Vd.8H, Vn.4S, #n
    
    
    Instruction Documentation: [vrshrn_high_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_high_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vrshrn_high_n_u64 (uint32x2_t r, uint64x2_t a, const int n)
    A32: VRSHRN.I64 Dd+1, Qm, #n
    A64: RSHRN2 Vd.4S, Vn.2D, #n
    
    
    Instruction Documentation: [vrshrn_high_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_high_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vrshrn_n_s16 (int16x8_t a, const int n)
    A32: VRSHRN.I16 Dd, Qm, #n
    A64: RSHRN Vd.8B, Vn.8H, #n
    
    
    Instruction Documentation: [vrshrn_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vrshrn_n_s32 (int32x4_t a, const int n)
    A32: VRSHRN.I32 Dd, Qm, #n
    A64: RSHRN Vd.4H, Vn.4S, #n
    
    
    Instruction Documentation: [vrshrn_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vrshrn_n_s64 (int64x2_t a, const int n)
    A32: VRSHRN.I64 Dd, Qm, #n
    A64: RSHRN Vd.2S, Vn.2D, #n
    
    
    Instruction Documentation: [vrshrn_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vrshrn_n_u16 (uint16x8_t a, const int n)
    A32: VRSHRN.I16 Dd, Qm, #n
    A64: RSHRN Vd.8B, Vn.8H, #n
    
    
    Instruction Documentation: [vrshrn_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vrshrn_n_u32 (uint32x4_t a, const int n)
    A32: VRSHRN.I32 Dd, Qm, #n
    A64: RSHRN Vd.4H, Vn.4S, #n
    
    
    Instruction Documentation: [vrshrn_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrn_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vrshrn_n_u64 (uint64x2_t a, const int n)
    A32: VRSHRN.I64 Dd, Qm, #n
    A64: RSHRN Vd.2S, Vn.2D, #n
    
    
    Instruction Documentation: [vrshrn_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrn_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vrshrq_n_s16 (int16x8_t a, const int n)
    A32: VRSHR.S16 Qd, Qm, #n
    A64: SRSHR Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vrshrq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrq_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vrshrq_n_s32 (int32x4_t a, const int n)
    A32: VRSHR.S32 Qd, Qm, #n
    A64: SRSHR Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vrshrq_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrq_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vrshrq_n_s64 (int64x2_t a, const int n)
    A32: VRSHR.S64 Qd, Qm, #n
    A64: SRSHR Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vrshrq_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrq_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vrshrq_n_s8 (int8x16_t a, const int n)
    A32: VRSHR.S8 Qd, Qm, #n
    A64: SRSHR Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vrshrq_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrq_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vrshrq_n_u16 (uint16x8_t a, const int n)
    A32: VRSHR.U16 Qd, Qm, #n
    A64: URSHR Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vrshrq_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrq_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vrshrq_n_u32 (uint32x4_t a, const int n)
    A32: VRSHR.U32 Qd, Qm, #n
    A64: URSHR Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vrshrq_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrq_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vrshrq_n_u64 (uint64x2_t a, const int n)
    A32: VRSHR.U64 Qd, Qm, #n
    A64: URSHR Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vrshrq_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrshrq_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vrshrq_n_u8 (uint8x16_t a, const int n)
    A32: VRSHR.U8 Qd, Qm, #n
    A64: URSHR Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vrshrq_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrshrq_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrte_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vrsqrte_f32 (float32x2_t a)
    A32: VRSQRTE.F32 Dd, Dm
    A64: FRSQRTE Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vrsqrte_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrte_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vrsqrte_u32 (uint32x2_t a)
    A32: VRSQRTE.U32 Dd, Dm
    A64: URSQRTE Vd.2S, Vn.2S
    
    
    Instruction Documentation: [vrsqrte_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrte_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrteq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vrsqrteq_f32 (float32x4_t a)
    A32: VRSQRTE.F32 Qd, Qm
    A64: FRSQRTE Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vrsqrteq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrteq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vrsqrteq_u32 (uint32x4_t a)
    A32: VRSQRTE.U32 Qd, Qm
    A64: URSQRTE Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vrsqrteq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrteq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrts_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vrsqrts_f32 (float32x2_t a, float32x2_t b)
    A32: VRSQRTS.F32 Dd, Dn, Dm
    A64: FRSQRTS Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vrsqrts_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrts_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsqrtsq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vrsqrtsq_f32 (float32x4_t a, float32x4_t b)
    A32: VRSQRTS.F32 Qd, Qn, Qm
    A64: FRSQRTS Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vrsqrtsq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsqrtsq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsra_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vrsra_n_s16 (int16x4_t a, int16x4_t b, const int n)
    A32: VRSRA.S16 Dd, Dm, #n
    A64: SRSRA Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vrsra_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsra_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vrsra_n_s32 (int32x2_t a, int32x2_t b, const int n)
    A32: VRSRA.S32 Dd, Dm, #n
    A64: SRSRA Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vrsra_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsra_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vrsra_n_s64 (int64x1_t a, int64x1_t b, const int n)
    A32: VRSRA.S64 Dd, Dm, #n
    A64: SRSRA Dd, Dn, #n
    
    
    Instruction Documentation: [vrsra_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsra_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vrsra_n_s8 (int8x8_t a, int8x8_t b, const int n)
    A32: VRSRA.S8 Dd, Dm, #n
    A64: SRSRA Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vrsra_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsra_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vrsra_n_u16 (uint16x4_t a, uint16x4_t b, const int n)
    A32: VRSRA.U16 Dd, Dm, #n
    A64: URSRA Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vrsra_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsra_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vrsra_n_u32 (uint32x2_t a, uint32x2_t b, const int n)
    A32: VRSRA.U32 Dd, Dm, #n
    A64: URSRA Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vrsra_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsra_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vrsra_n_u64 (uint64x1_t a, uint64x1_t b, const int n)
    A32: VRSRA.U64 Dd, Dm, #n
    A64: URSRA Dd, Dn, #n
    
    
    Instruction Documentation: [vrsra_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsra_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vrsra_n_u8 (uint8x8_t a, uint8x8_t b, const int n)
    A32: VRSRA.U8 Dd, Dm, #n
    A64: URSRA Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vrsra_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsra_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsraq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vrsraq_n_s16 (int16x8_t a, int16x8_t b, const int n)
    A32: VRSRA.S16 Qd, Qm, #n
    A64: SRSRA Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vrsraq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsraq_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vrsraq_n_s32 (int32x4_t a, int32x4_t b, const int n)
    A32: VRSRA.S32 Qd, Qm, #n
    A64: SRSRA Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vrsraq_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsraq_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vrsraq_n_s64 (int64x2_t a, int64x2_t b, const int n)
    A32: VRSRA.S64 Qd, Qm, #n
    A64: SRSRA Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vrsraq_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsraq_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vrsraq_n_s8 (int8x16_t a, int8x16_t b, const int n)
    A32: VRSRA.S8 Qd, Qm, #n
    A64: SRSRA Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vrsraq_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsraq_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vrsraq_n_u16 (uint16x8_t a, uint16x8_t b, const int n)
    A32: VRSRA.U16 Qd, Qm, #n
    A64: URSRA Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vrsraq_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsraq_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vrsraq_n_u32 (uint32x4_t a, uint32x4_t b, const int n)
    A32: VRSRA.U32 Qd, Qm, #n
    A64: URSRA Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vrsraq_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsraq_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vrsraq_n_u64 (uint64x2_t a, uint64x2_t b, const int n)
    A32: VRSRA.U64 Qd, Qm, #n
    A64: URSRA Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vrsraq_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsraq_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vrsraq_n_u8 (uint8x16_t a, uint8x16_t b, const int n)
    A32: VRSRA.U8 Qd, Qm, #n
    A64: URSRA Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vrsraq_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsraq_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vrsubhn_high_s16 (int8x8_t r, int16x8_t a, int16x8_t b)
    A32: VRSUBHN.I16 Dd+1, Qn, Qm
    A64: RSUBHN2 Vd.16B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vrsubhn_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vrsubhn_high_s32 (int16x4_t r, int32x4_t a, int32x4_t b)
    A32: VRSUBHN.I32 Dd+1, Qn, Qm
    A64: RSUBHN2 Vd.8H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vrsubhn_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_high_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vrsubhn_high_s64 (int32x2_t r, int64x2_t a, int64x2_t b)
    A32: VRSUBHN.I64 Dd+1, Qn, Qm
    A64: RSUBHN2 Vd.4S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vrsubhn_high_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vrsubhn_high_u16 (uint8x8_t r, uint16x8_t a, uint16x8_t b)
    A32: VRSUBHN.I16 Dd+1, Qn, Qm
    A64: RSUBHN2 Vd.16B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vrsubhn_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vrsubhn_high_u32 (uint16x4_t r, uint32x4_t a, uint32x4_t b)
    A32: VRSUBHN.I32 Dd+1, Qn, Qm
    A64: RSUBHN2 Vd.8H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vrsubhn_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_high_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vrsubhn_high_u64 (uint32x2_t r, uint64x2_t a, uint64x2_t b)
    A32: VRSUBHN.I64 Dd+1, Qn, Qm
    A64: RSUBHN2 Vd.4S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vrsubhn_high_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_high_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vrsubhn_s16 (int16x8_t a, int16x8_t b)
    A32: VRSUBHN.I16 Dd, Qn, Qm
    A64: RSUBHN Vd.8B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vrsubhn_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vrsubhn_s32 (int32x4_t a, int32x4_t b)
    A32: VRSUBHN.I32 Dd, Qn, Qm
    A64: RSUBHN Vd.4H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vrsubhn_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vrsubhn_s64 (int64x2_t a, int64x2_t b)
    A32: VRSUBHN.I64 Dd, Qn, Qm
    A64: RSUBHN Vd.2S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vrsubhn_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vrsubhn_u16 (uint16x8_t a, uint16x8_t b)
    A32: VRSUBHN.I16 Dd, Qn, Qm
    A64: RSUBHN Vd.8B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vrsubhn_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vrsubhn_u32 (uint32x4_t a, uint32x4_t b)
    A32: VRSUBHN.I32 Dd, Qn, Qm
    A64: RSUBHN Vd.4H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vrsubhn_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vrsubhn_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vrsubhn_u64 (uint64x2_t a, uint64x2_t b)
    A32: VRSUBHN.I64 Dd, Qn, Qm
    A64: RSUBHN Vd.2S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vrsubhn_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vrsubhn_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vset_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vset_lane_f32 (float32_t a, float32x2_t v, const int lane)
    A32: VMOV.F32 Sd, Sm
    A64: INS Vd.S[lane], Vn.S[0]
    
    
    Instruction Documentation: [vset_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vset_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vset_lane_s16 (int16_t a, int16x4_t v, const int lane)
    A32: VMOV.16 Dd[lane], Rt
    A64: INS Vd.H[lane], Wn
    
    
    Instruction Documentation: [vset_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vset_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vset_lane_s32 (int32_t a, int32x2_t v, const int lane)
    A32: VMOV.32 Dd[lane], Rt
    A64: INS Vd.S[lane], Wn
    
    
    Instruction Documentation: [vset_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vset_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vset_lane_s8 (int8_t a, int8x8_t v, const int lane)
    A32: VMOV.8 Dd[lane], Rt
    A64: INS Vd.B[lane], Wn
    
    
    Instruction Documentation: [vset_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vset_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vset_lane_u16 (uint16_t a, uint16x4_t v, const int lane)
    A32: VMOV.16 Dd[lane], Rt
    A64: INS Vd.H[lane], Wn
    
    
    Instruction Documentation: [vset_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vset_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vset_lane_u32 (uint32_t a, uint32x2_t v, const int lane)
    A32: VMOV.32 Dd[lane], Rt
    A64: INS Vd.S[lane], Wn
    
    
    Instruction Documentation: [vset_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vset_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vset_lane_u8 (uint8_t a, uint8x8_t v, const int lane)
    A32: VMOV.8 Dd[lane], Rt
    A64: INS Vd.B[lane], Wn
    
    
    Instruction Documentation: [vset_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vset_lane_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsetq_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vsetq_lane_f32 (float32_t a, float32x4_t v, const int lane)
    A32: VMOV.F32 Sd, Sm
    A64: INS Vd.S[lane], Vn.S[0]
    
    
    Instruction Documentation: [vsetq_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsetq_lane_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x2_t vsetq_lane_f64 (float64_t a, float64x2_t v, const int lane)
    A32: VMOV.F64 Dd, Dm
    A64: INS Vd.D[lane], Vn.D[0]
    
    
    Instruction Documentation: [vsetq_lane_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsetq_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vsetq_lane_s16 (int16_t a, int16x8_t v, const int lane)
    A32: VMOV.16 Dd[lane], Rt
    A64: INS Vd.H[lane], Wn
    
    
    Instruction Documentation: [vsetq_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsetq_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vsetq_lane_s32 (int32_t a, int32x4_t v, const int lane)
    A32: VMOV.32 Dd[lane], Rt
    A64: INS Vd.S[lane], Wn
    
    
    Instruction Documentation: [vsetq_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsetq_lane_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vsetq_lane_s64 (int64_t a, int64x2_t v, const int lane)
    A32: VMOV.64 Dd, Rt, Rt2
    A64: INS Vd.D[lane], Xn
    
    
    Instruction Documentation: [vsetq_lane_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsetq_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vsetq_lane_s8 (int8_t a, int8x16_t v, const int lane)
    A32: VMOV.8 Dd[lane], Rt
    A64: INS Vd.B[lane], Wn
    
    
    Instruction Documentation: [vsetq_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsetq_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vsetq_lane_u16 (uint16_t a, uint16x8_t v, const int lane)
    A32: VMOV.16 Dd[lane], Rt
    A64: INS Vd.H[lane], Wn
    
    
    Instruction Documentation: [vsetq_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsetq_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vsetq_lane_u32 (uint32_t a, uint32x4_t v, const int lane)
    A32: VMOV.32 Dd[lane], Rt
    A64: INS Vd.S[lane], Wn
    
    
    Instruction Documentation: [vsetq_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsetq_lane_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vsetq_lane_u64 (uint64_t a, uint64x2_t v, const int lane)
    A32: VMOV.64 Dd, Rt, Rt2
    A64: INS Vd.D[lane], Xn
    
    
    Instruction Documentation: [vsetq_lane_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsetq_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vsetq_lane_u8 (uint8_t a, uint8x16_t v, const int lane)
    A32: VMOV.8 Dd[lane], Rt
    A64: INS Vd.B[lane], Wn
    
    
    Instruction Documentation: [vsetq_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsetq_lane_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vshl_n_s16 (int16x4_t a, const int n)
    A32: VSHL.I16 Dd, Dm, #n
    A64: SHL Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vshl_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vshl_n_s32 (int32x2_t a, const int n)
    A32: VSHL.I32 Dd, Dm, #n
    A64: SHL Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vshl_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vshl_n_s64 (int64x1_t a, const int n)
    A32: VSHL.I64 Dd, Dm, #n
    A64: SHL Dd, Dn, #n
    
    
    Instruction Documentation: [vshl_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vshl_n_s8 (int8x8_t a, const int n)
    A32: VSHL.I8 Dd, Dm, #n
    A64: SHL Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vshl_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vshl_n_u16 (uint16x4_t a, const int n)
    A32: VSHL.I16 Dd, Dm, #n
    A64: SHL Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vshl_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vshl_n_u32 (uint32x2_t a, const int n)
    A32: VSHL.I32 Dd, Dm, #n
    A64: SHL Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vshl_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vshl_n_u64 (uint64x1_t a, const int n)
    A32: VSHL.I64 Dd, Dm, #n
    A64: SHL Dd, Dn, #n
    
    
    Instruction Documentation: [vshl_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vshl_n_u8 (uint8x8_t a, const int n)
    A32: VSHL.I8 Dd, Dm, #n
    A64: SHL Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vshl_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vshl_s16 (int16x4_t a, int16x4_t b)
    A32: VSHL.S16 Dd, Dn, Dm
    A64: SSHL Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vshl_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vshl_s32 (int32x2_t a, int32x2_t b)
    A32: VSHL.S32 Dd, Dn, Dm
    A64: SSHL Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vshl_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vshl_s64 (int64x1_t a, int64x1_t b)
    A32: VSHL.S64 Dd, Dn, Dm
    A64: SSHL Dd, Dn, Dm
    
    
    Instruction Documentation: [vshl_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vshl_s8 (int8x8_t a, int8x8_t b)
    A32: VSHL.S8 Dd, Dn, Dm
    A64: SSHL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vshl_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vshl_u16 (uint16x4_t a, int16x4_t b)
    A32: VSHL.U16 Dd, Dn, Dm
    A64: USHL Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vshl_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vshl_u32 (uint32x2_t a, int32x2_t b)
    A32: VSHL.U32 Dd, Dn, Dm
    A64: USHL Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vshl_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vshl_u64 (uint64x1_t a, int64x1_t b)
    A32: VSHL.U64 Dd, Dn, Dm
    A64: USHL Dd, Dn, Dm
    
    
    Instruction Documentation: [vshl_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshl_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vshl_u8 (uint8x8_t a, int8x8_t b)
    A32: VSHL.U8 Dd, Dn, Dm
    A64: USHL Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vshl_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshl_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_high_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vshll_high_n_s16 (int16x8_t a, const int n)
    A32: VSHLL.S16 Qd, Dm+1, #n
    A64: SSHLL2 Vd.4S, Vn.8H, #n
    
    
    Instruction Documentation: [vshll_high_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_high_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vshll_high_n_s32 (int32x4_t a, const int n)
    A32: VSHLL.S32 Qd, Dm+1, #n
    A64: SSHLL2 Vd.2D, Vn.4S, #n
    
    
    Instruction Documentation: [vshll_high_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_high_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vshll_high_n_s8 (int8x16_t a, const int n)
    A32: VSHLL.S8 Qd, Dm+1, #n
    A64: SSHLL2 Vd.8H, Vn.16B, #n
    
    
    Instruction Documentation: [vshll_high_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_high_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vshll_high_n_u16 (uint16x8_t a, const int n)
    A32: VSHLL.U16 Qd, Dm+1, #n
    A64: USHLL2 Vd.4S, Vn.8H, #n
    
    
    Instruction Documentation: [vshll_high_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_high_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vshll_high_n_u32 (uint32x4_t a, const int n)
    A32: VSHLL.U32 Qd, Dm+1, #n
    A64: USHLL2 Vd.2D, Vn.4S, #n
    
    
    Instruction Documentation: [vshll_high_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_high_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vshll_high_n_u8 (uint8x16_t a, const int n)
    A32: VSHLL.U8 Qd, Dm+1, #n
    A64: USHLL2 Vd.8H, Vn.16B, #n
    
    
    Instruction Documentation: [vshll_high_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_high_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vshll_n_s16 (int16x4_t a, const int n)
    A32: VSHLL.S16 Qd, Dm, #n
    A64: SSHLL Vd.4S, Vn.4H, #n
    
    
    Instruction Documentation: [vshll_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vshll_n_s32 (int32x2_t a, const int n)
    A32: VSHLL.S32 Qd, Dm, #n
    A64: SSHLL Vd.2D, Vn.2S, #n
    
    
    Instruction Documentation: [vshll_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vshll_n_s8 (int8x8_t a, const int n)
    A32: VSHLL.S8 Qd, Dm, #n
    A64: SSHLL Vd.8H, Vn.8B, #n
    
    
    Instruction Documentation: [vshll_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vshll_n_u16 (uint16x4_t a, const int n)
    A32: VSHLL.U16 Qd, Dm, #n
    A64: USHLL Vd.4S, Vn.4H, #n
    
    
    Instruction Documentation: [vshll_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vshll_n_u32 (uint32x2_t a, const int n)
    A32: VSHLL.U32 Qd, Dm, #n
    A64: USHLL Vd.2D, Vn.2S, #n
    
    
    Instruction Documentation: [vshll_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshll_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vshll_n_u8 (uint8x8_t a, const int n)
    A32: VSHLL.U8 Qd, Dm, #n
    A64: USHLL Vd.8H, Vn.8B, #n
    
    
    Instruction Documentation: [vshll_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshll_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vshlq_n_s16 (int16x8_t a, const int n)
    A32: VSHL.I16 Qd, Qm, #n
    A64: SHL Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vshlq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vshlq_n_s64 (int64x2_t a, const int n)
    A32: VSHL.I64 Qd, Qm, #n
    A64: SHL Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vshlq_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vshlq_n_s8 (int8x16_t a, const int n)
    A32: VSHL.I8 Qd, Qm, #n
    A64: SHL Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vshlq_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vshlq_n_u16 (uint16x8_t a, const int n)
    A32: VSHL.I16 Qd, Qm, #n
    A64: SHL Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vshlq_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vshlq_n_u32 (uint32x4_t a, const int n)
    A32: VSHL.I32 Qd, Qm, #n
    A64: SHL Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vshlq_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vshlq_n_u64 (uint64x2_t a, const int n)
    A32: VSHL.I64 Qd, Qm, #n
    A64: SHL Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vshlq_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vshlq_n_u8 (uint8x16_t a, const int n)
    A32: VSHL.I8 Qd, Qm, #n
    A64: SHL Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vshlq_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vshlq_s16 (int16x8_t a, int16x8_t b)
    A32: VSHL.S16 Qd, Qn, Qm
    A64: SSHL Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vshlq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vshlq_s32 (int32x4_t a, int32x4_t b)
    A32: VSHL.S32 Qd, Qn, Qm
    A64: SSHL Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vshlq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vshlq_s64 (int64x2_t a, int64x2_t b)
    A32: VSHL.S64 Qd, Qn, Qm
    A64: SSHL Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vshlq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vshlq_s8 (int8x16_t a, int8x16_t b)
    A32: VSHL.S8 Qd, Qn, Qm
    A64: SSHL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vshlq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vshlq_u16 (uint16x8_t a, int16x8_t b)
    A32: VSHL.U16 Qd, Qn, Qm
    A64: USHL Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vshlq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vshlq_u32 (uint32x4_t a, int32x4_t b)
    A32: VSHL.U32 Qd, Qn, Qm
    A64: USHL Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vshlq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vshlq_u64 (uint64x2_t a, int64x2_t b)
    A32: VSHL.U64 Qd, Qn, Qm
    A64: USHL Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vshlq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshlq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vshlq_u8 (uint8x16_t a, int8x16_t b)
    A32: VSHL.U8 Qd, Qn, Qm
    A64: USHL Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vshlq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshlq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshr_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vshr_n_s16 (int16x4_t a, const int n)
    A32: VSHR.S16 Dd, Dm, #n
    A64: SSHR Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vshr_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshr_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vshr_n_s32 (int32x2_t a, const int n)
    A32: VSHR.S32 Dd, Dm, #n
    A64: SSHR Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vshr_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshr_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vshr_n_s64 (int64x1_t a, const int n)
    A32: VSHR.S64 Dd, Dm, #n
    A64: SSHR Dd, Dn, #n
    
    
    Instruction Documentation: [vshr_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshr_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vshr_n_s8 (int8x8_t a, const int n)
    A32: VSHR.S8 Dd, Dm, #n
    A64: SSHR Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vshr_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshr_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vshr_n_u16 (uint16x4_t a, const int n)
    A32: VSHR.U16 Dd, Dm, #n
    A64: USHR Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vshr_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshr_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vshr_n_u32 (uint32x2_t a, const int n)
    A32: VSHR.U32 Dd, Dm, #n
    A64: USHR Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vshr_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshr_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vshr_n_u64 (uint64x1_t a, const int n)
    A32: VSHR.U64 Dd, Dm, #n
    A64: USHR Dd, Dn, #n
    
    
    Instruction Documentation: [vshr_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshr_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vshr_n_u8 (uint8x8_t a, const int n)
    A32: VSHR.U8 Dd, Dm, #n
    A64: USHR Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vshr_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshr_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_high_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vshrn_high_n_s16 (int8x8_t r, int16x8_t a, const int n)
    A32: VSHRN.I16 Dd+1, Qm, #n
    A64: SHRN2 Vd.16B, Vn.8H, #n
    
    
    Instruction Documentation: [vshrn_high_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_high_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vshrn_high_n_s32 (int16x4_t r, int32x4_t a, const int n)
    A32: VSHRN.I32 Dd+1, Qm, #n
    A64: SHRN2 Vd.8H, Vn.4S, #n
    
    
    Instruction Documentation: [vshrn_high_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_high_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vshrn_high_n_s64 (int32x2_t r, int64x2_t a, const int n)
    A32: VSHRN.I64 Dd+1, Qm, #n
    A64: SHRN2 Vd.4S, Vn.2D, #n
    
    
    Instruction Documentation: [vshrn_high_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_high_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vshrn_high_n_u16 (uint8x8_t r, uint16x8_t a, const int n)
    A32: VSHRN.I16 Dd+1, Qm, #n
    A64: SHRN2 Vd.16B, Vn.8H, #n
    
    
    Instruction Documentation: [vshrn_high_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_high_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vshrn_high_n_u32 (uint16x4_t r, uint32x4_t a, const int n)
    A32: VSHRN.I32 Dd+1, Qm, #n
    A64: SHRN2 Vd.8H, Vn.4S, #n
    
    
    Instruction Documentation: [vshrn_high_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_high_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vshrn_high_n_u64 (uint32x2_t r, uint64x2_t a, const int n)
    A32: VSHRN.I64 Dd+1, Qm, #n
    A64: SHRN2 Vd.4S, Vn.2D, #n
    
    
    Instruction Documentation: [vshrn_high_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_high_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vshrn_n_s16 (int16x8_t a, const int n)
    A32: VSHRN.I16 Dd, Qm, #n
    A64: SHRN Vd.8B, Vn.8H, #n
    
    
    Instruction Documentation: [vshrn_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vshrn_n_s32 (int32x4_t a, const int n)
    A32: VSHRN.I32 Dd, Qm, #n
    A64: SHRN Vd.4H, Vn.4S, #n
    
    
    Instruction Documentation: [vshrn_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vshrn_n_s64 (int64x2_t a, const int n)
    A32: VSHRN.I64 Dd, Qm, #n
    A64: SHRN Vd.2S, Vn.2D, #n
    
    
    Instruction Documentation: [vshrn_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vshrn_n_u16 (uint16x8_t a, const int n)
    A32: VSHRN.I16 Dd, Qm, #n
    A64: SHRN Vd.8B, Vn.8H, #n
    
    
    Instruction Documentation: [vshrn_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vshrn_n_u32 (uint32x4_t a, const int n)
    A32: VSHRN.I32 Dd, Qm, #n
    A64: SHRN Vd.4H, Vn.4S, #n
    
    
    Instruction Documentation: [vshrn_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrn_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vshrn_n_u64 (uint64x2_t a, const int n)
    A32: VSHRN.I64 Dd, Qm, #n
    A64: SHRN Vd.2S, Vn.2D, #n
    
    
    Instruction Documentation: [vshrn_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrn_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vshrq_n_s16 (int16x8_t a, const int n)
    A32: VSHR.S16 Qd, Qm, #n
    A64: SSHR Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vshrq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrq_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vshrq_n_s32 (int32x4_t a, const int n)
    A32: VSHR.S32 Qd, Qm, #n
    A64: SSHR Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vshrq_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrq_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vshrq_n_s64 (int64x2_t a, const int n)
    A32: VSHR.S64 Qd, Qm, #n
    A64: SSHR Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vshrq_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrq_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vshrq_n_s8 (int8x16_t a, const int n)
    A32: VSHR.S8 Qd, Qm, #n
    A64: SSHR Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vshrq_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrq_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vshrq_n_u16 (uint16x8_t a, const int n)
    A32: VSHR.U16 Qd, Qm, #n
    A64: USHR Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vshrq_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrq_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vshrq_n_u32 (uint32x4_t a, const int n)
    A32: VSHR.U32 Qd, Qm, #n
    A64: USHR Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vshrq_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrq_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vshrq_n_u64 (uint64x2_t a, const int n)
    A32: VSHR.U64 Qd, Qm, #n
    A64: USHR Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vshrq_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vshrq_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vshrq_n_u8 (uint8x16_t a, const int n)
    A32: VSHR.U8 Qd, Qm, #n
    A64: USHR Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vshrq_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vshrq_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqrt_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vsqrt_f64 (float64x1_t a)
    A32: VSQRT.F64 Dd, Dm
    A64: FSQRT Dd, Dn
    
    
    Instruction Documentation: [vsqrt_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrt_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsqrts_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vsqrts_f32 (float32_t a)
    A32: VSQRT.F32 Sd, Sm
    A64: FSQRT Sd, Sn The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vsqrts_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsqrts_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsra_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vsra_n_s16 (int16x4_t a, int16x4_t b, const int n)
    A32: VSRA.S16 Dd, Dm, #n
    A64: SSRA Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vsra_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsra_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vsra_n_s32 (int32x2_t a, int32x2_t b, const int n)
    A32: VSRA.S32 Dd, Dm, #n
    A64: SSRA Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vsra_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsra_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vsra_n_s64 (int64x1_t a, int64x1_t b, const int n)
    A32: VSRA.S64 Dd, Dm, #n
    A64: SSRA Dd, Dn, #n
    
    
    Instruction Documentation: [vsra_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsra_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vsra_n_s8 (int8x8_t a, int8x8_t b, const int n)
    A32: VSRA.S8 Dd, Dm, #n
    A64: SSRA Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vsra_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsra_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vsra_n_u16 (uint16x4_t a, uint16x4_t b, const int n)
    A32: VSRA.U16 Dd, Dm, #n
    A64: USRA Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vsra_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsra_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vsra_n_u32 (uint32x2_t a, uint32x2_t b, const int n)
    A32: VSRA.U32 Dd, Dm, #n
    A64: USRA Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vsra_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsra_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vsra_n_u64 (uint64x1_t a, uint64x1_t b, const int n)
    A32: VSRA.U64 Dd, Dm, #n
    A64: USRA Dd, Dn, #n
    
    
    Instruction Documentation: [vsra_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsra_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vsra_n_u8 (uint8x8_t a, uint8x8_t b, const int n)
    A32: VSRA.U8 Dd, Dm, #n
    A64: USRA Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vsra_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsra_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsraq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vsraq_n_s16 (int16x8_t a, int16x8_t b, const int n)
    A32: VSRA.S16 Qd, Qm, #n
    A64: SSRA Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vsraq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsraq_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vsraq_n_s32 (int32x4_t a, int32x4_t b, const int n)
    A32: VSRA.S32 Qd, Qm, #n
    A64: SSRA Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vsraq_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsraq_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vsraq_n_s64 (int64x2_t a, int64x2_t b, const int n)
    A32: VSRA.S64 Qd, Qm, #n
    A64: SSRA Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vsraq_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsraq_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vsraq_n_s8 (int8x16_t a, int8x16_t b, const int n)
    A32: VSRA.S8 Qd, Qm, #n
    A64: SSRA Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vsraq_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsraq_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vsraq_n_u16 (uint16x8_t a, uint16x8_t b, const int n)
    A32: VSRA.U16 Qd, Qm, #n
    A64: USRA Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vsraq_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsraq_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vsraq_n_u32 (uint32x4_t a, uint32x4_t b, const int n)
    A32: VSRA.U32 Qd, Qm, #n
    A64: USRA Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vsraq_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsraq_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vsraq_n_u64 (uint64x2_t a, uint64x2_t b, const int n)
    A32: VSRA.U64 Qd, Qm, #n
    A64: USRA Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vsraq_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsraq_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vsraq_n_u8 (uint8x16_t a, uint8x16_t b, const int n)
    A32: VSRA.U8 Qd, Qm, #n
    A64: USRA Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vsraq_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsraq_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsri_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vsri_n_s16(int16x4_t a, int16x4_t b, __builtin_constant_p(n))
    A32: VSRI.16 Dd, Dm, #n
    A64: SRI Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vsri_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsri_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vsri_n_s32(int32x2_t a, int32x2_t b, __builtin_constant_p(n))
    A32: VSRI.32 Dd, Dm, #n
    A64: SRI Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vsri_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsri_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vsri_n_s8(int8x8_t a, int8x8_t b, __builtin_constant_p(n))
    A32: VSRI.8 Dd, Dm, #n
    A64: SRI Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vsri_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsri_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vsri_n_u16(uint16x4_t a, uint16x4_t b, __builtin_constant_p(n))
    A32: VSRI.16 Dd, Dm, #n
    A64: SRI Vd.4H, Vn.4H, #n
    
    
    Instruction Documentation: [vsri_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsri_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vsri_n_u32(uint32x2_t a, uint32x2_t b, __builtin_constant_p(n))
    A32: VSRI.32 Dd, Dm, #n
    A64: SRI Vd.2S, Vn.2S, #n
    
    
    Instruction Documentation: [vsri_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsri_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vsri_n_u8(uint8x8_t a, uint8x8_t b, __builtin_constant_p(n))
    A32: VSRI.8 Dd, Dm, #n
    A64: SRI Vd.8B, Vn.8B, #n
    
    
    Instruction Documentation: [vsri_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsri_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsriq_n_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vsriq_n_s16(int16x8_t a, int16x8_t b, __builtin_constant_p(n))
    A32: VSRI.16 Qd, Qm, #n
    A64: SRI Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vsriq_n_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsriq_n_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vsriq_n_s32(int32x4_t a, int32x4_t b, __builtin_constant_p(n))
    A32: VSRI.32 Qd, Qm, #n
    A64: SRI Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vsriq_n_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsriq_n_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vsriq_n_s64(int64x2_t a, int64x2_t b, __builtin_constant_p(n))
    A32: VSRI.64 Qd, Qm, #n
    A64: SRI Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vsriq_n_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsriq_n_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vsriq_n_s8(int8x16_t a, int8x16_t b, __builtin_constant_p(n))
    A32: VSRI.8 Qd, Qm, #n
    A64: SRI Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vsriq_n_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsriq_n_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vsriq_n_u16(uint16x8_t a, uint16x8_t b, __builtin_constant_p(n))
    A32: VSRI.16 Qd, Qm, #n
    A64: SRI Vd.8H, Vn.8H, #n
    
    
    Instruction Documentation: [vsriq_n_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsriq_n_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vsriq_n_u32(uint32x4_t a, uint32x4_t b, __builtin_constant_p(n))
    A32: VSRI.32 Qd, Qm, #n
    A64: SRI Vd.4S, Vn.4S, #n
    
    
    Instruction Documentation: [vsriq_n_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsriq_n_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vsriq_n_u64(uint64x2_t a, uint64x2_t b, __builtin_constant_p(n))
    A32: VSRI.64 Qd, Qm, #n
    A64: SRI Vd.2D, Vn.2D, #n
    
    
    Instruction Documentation: [vsriq_n_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsriq_n_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vsriq_n_u8(uint8x16_t a, uint8x16_t b, __builtin_constant_p(n))
    A32: VSRI.8 Qd, Qm, #n
    A64: SRI Vd.16B, Vn.16B, #n
    
    
    Instruction Documentation: [vsriq_n_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsriq_n_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vst1_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_f32 (float32_t * ptr, float32x2_t val)
    A32: VST1.32 { Dd }, [Rn]
    A64: ST1 { Vt.2S }, [Xn]
    
    
    Instruction Documentation: [vst1_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_f64 (float64_t * ptr, float64x1_t val)
    A32: VST1.64 { Dd }, [Rn]
    A64: ST1 { Vt.1D }, [Xn]
    
    
    Instruction Documentation: [vst1_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_f64)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_lane_f32 (float32_t * ptr, float32x2_t val, const int lane)
    A32: VST1.32 { Dd[index] }, [Rn]
    A64: ST1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vst1_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_f32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_lane_s16 (int16_t * ptr, int16x4_t val, const int lane)
    A32: VST1.16 { Dd[index] }, [Rn]
    A64: ST1 { Vt.H }[index], [Xn]
    
    
    Instruction Documentation: [vst1_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s16)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_lane_s32 (int32_t * ptr, int32x2_t val, const int lane)
    A32: VST1.32 { Dd[index] }, [Rn]
    A64: ST1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vst1_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_lane_s8 (int8_t * ptr, int8x8_t val, const int lane)
    A32: VST1.8 { Dd[index] }, [Rn]
    A64: ST1 { Vt.B }[index], [Xn]
    
    
    Instruction Documentation: [vst1_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_s8)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_lane_u16 (uint16_t * ptr, uint16x4_t val, const int lane)
    A32: VST1.16 { Dd[index] }, [Rn]
    A64: ST1 { Vt.H }[index], [Xn]
    
    
    Instruction Documentation: [vst1_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u16)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_lane_u32 (uint32_t * ptr, uint32x2_t val, const int lane)
    A32: VST1.32 { Dd[index] }, [Rn]
    A64: ST1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vst1_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_lane_u8 (uint8_t * ptr, uint8x8_t val, const int lane)
    A32: VST1.8 { Dd[index] }, [Rn]
    A64: ST1 { Vt.B }[index], [Xn]
    
    
    Instruction Documentation: [vst1_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_lane_u8)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_s16 (int16_t * ptr, int16x4_t val)
    A32: VST1.16 { Dd }, [Rn]
    A64: ST1 {Vt.4H }, [Xn]
    
    
    Instruction Documentation: [vst1_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s16)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_s32 (int32_t * ptr, int32x2_t val)
    A32: VST1.32 { Dd }, [Rn]
    A64: ST1 { Vt.2S }, [Xn]
    
    
    Instruction Documentation: [vst1_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_s64 (int64_t * ptr, int64x1_t val)
    A32: VST1.64 { Dd }, [Rn]
    A64: ST1 { Vt.1D }, [Xn]
    
    
    Instruction Documentation: [vst1_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s64)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_s8 (int8_t * ptr, int8x8_t val)
    A32: VST1.8 { Dd }, [Rn]
    A64: ST1 { Vt.8B }, [Xn]
    
    
    Instruction Documentation: [vst1_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_s8)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_u16 (uint16_t * ptr, uint16x4_t val)
    A32: VST1.16 { Dd }, [Rn]
    A64: ST1 { Vt.4H }, [Xn]
    
    
    Instruction Documentation: [vst1_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u16)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_u32 (uint32_t * ptr, uint32x2_t val)
    A32: VST1.32 { Dd }, [Rn]
    A64: ST1 { Vt.2S }, [Xn]
    
    
    Instruction Documentation: [vst1_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_u64 (uint64_t * ptr, uint64x1_t val)
    A32: VST1.64 { Dd }, [Rn]
    A64: ST1 { Vt.1D }, [Xn]
    
    
    Instruction Documentation: [vst1_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u64)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1_u8 (uint8_t * ptr, uint8x8_t val)
    A32: VST1.8 { Dd }, [Rn]
    A64: ST1 { Vt.8B }, [Xn]
    
    
    Instruction Documentation: [vst1_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1_u8)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_f32 (float32_t * ptr, float32x4_t val)
    A32: VST1.32 { Dd, Dd+1 }, [Rn]
    A64: ST1 { Vt.4S }, [Xn]
    
    
    Instruction Documentation: [vst1q_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_f64 (float64_t * ptr, float64x2_t val)
    A32: VST1.64 { Dd, Dd+1 }, [Rn]
    A64: ST1 { Vt.2D }, [Xn]
    
    
    Instruction Documentation: [vst1q_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_f64)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_lane_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_lane_f32 (float32_t * ptr, float32x4_t val, const int lane)
    A32: VST1.32 { Dd[index] }, [Rn]
    A64: ST1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vst1q_lane_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_lane_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_lane_f64 (float64_t * ptr, float64x2_t val, const int lane)
    A32: VSTR.64 Dd, [Rn]
    A64: ST1 { Vt.D }[index], [Xn]
    
    
    Instruction Documentation: [vst1q_lane_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_f64)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_lane_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_lane_s16 (int16_t * ptr, int16x8_t val, const int lane)
    A32: VST1.16 { Dd[index] }, [Rn]
    A64: ST1 { Vt.H }[index], [Xn]
    
    
    Instruction Documentation: [vst1q_lane_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s16)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_lane_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_lane_s32 (int32_t * ptr, int32x4_t val, const int lane)
    A32: VST1.32 { Dd[index] }, [Rn]
    A64: ST1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vst1q_lane_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_lane_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_lane_s64 (int64_t * ptr, int64x2_t val, const int lane)
    A32: VSTR.64 Dd, [Rn]
    A64: ST1 { Vt.D }[index], [Xn]
    
    
    Instruction Documentation: [vst1q_lane_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s64)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_lane_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_lane_s8 (int8_t * ptr, int8x16_t val, const int lane)
    A32: VST1.8 { Dd[index] }, [Rn]
    A64: ST1 { Vt.B }[index], [Xn]
    
    
    Instruction Documentation: [vst1q_lane_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_s8)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_lane_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_lane_u16 (uint16_t * ptr, uint16x8_t val, const int lane)
    A32: VST1.16 { Dd[index] }, [Rn]
    A64: ST1 { Vt.H }[index], [Xn]
    
    
    Instruction Documentation: [vst1q_lane_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u16)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_lane_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_lane_u32 (uint32_t * ptr, uint32x4_t val, const int lane)
    A32: VST1.32 { Dd[index] }, [Rn]
    A64: ST1 { Vt.S }[index], [Xn]
    
    
    Instruction Documentation: [vst1q_lane_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_lane_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_lane_u64 (uint64_t * ptr, uint64x2_t val, const int lane)
    A32: VSTR.64 Dd, [Rn]
    A64: ST1 { Vt.D }[index], [Xn]
    
    
    Instruction Documentation: [vst1q_lane_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u64)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_lane_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_lane_u8 (uint8_t * ptr, uint8x16_t val, const int lane)
    A32: VST1.8 { Dd[index] }, [Rn]
    A64: ST1 { Vt.B }[index], [Xn]
    
    
    Instruction Documentation: [vst1q_lane_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_lane_u8)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_s16 (int16_t * ptr, int16x8_t val)
    A32: VST1.16 { Dd, Dd+1 }, [Rn]
    A64: ST1 { Vt.8H }, [Xn]
    
    
    Instruction Documentation: [vst1q_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s16)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_s32 (int32_t * ptr, int32x4_t val)
    A32: VST1.32 { Dd, Dd+1 }, [Rn]
    A64: ST1 { Vt.4S }, [Xn]
    
    
    Instruction Documentation: [vst1q_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_s64 (int64_t * ptr, int64x2_t val)
    A32: VST1.64 { Dd, Dd+1 }, [Rn]
    A64: ST1 { Vt.2D }, [Xn]
    
    
    Instruction Documentation: [vst1q_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s64)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_s8 (int8_t * ptr, int8x16_t val)
    A32: VST1.8 { Dd, Dd+1 }, [Rn]
    A64: ST1 { Vt.16B }, [Xn]
    
    
    Instruction Documentation: [vst1q_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_s8)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_u16 (uint16_t * ptr, uint16x8_t val)
    A32: VST1.16 { Dd, Dd+1 }, [Rn]
    A64: ST1 { Vt.8H }, [Xn]
    
    
    Instruction Documentation: [vst1q_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u16)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_u32 (uint32_t * ptr, uint32x4_t val)
    A32: VST1.32 { Dd, Dd+1 }, [Rn]
    A64: ST1 { Vt.4S }, [Xn]
    
    
    Instruction Documentation: [vst1q_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u32)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_u64 (uint64_t * ptr, uint64x2_t val)
    A32: VST1.64 { Dd, Dd+1 }, [Rn]
    A64: ST1 { Vt.2D }, [Xn]
    
    
    Instruction Documentation: [vst1q_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u64)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vst1q_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"void vst1q_u8 (uint8_t * ptr, uint8x16_t val)
    A32: VST1.8 { Dd, Dd+1 }, [Rn]
    A64: ST1 { Vt.16B }, [Xn]
    
    
    Instruction Documentation: [vst1q_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vst1q_u8)";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["vsub_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x2_t vsub_f32 (float32x2_t a, float32x2_t b)
    A32: VSUB.F32 Dd, Dn, Dm
    A64: FSUB Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vsub_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsub_f64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float64x1_t vsub_f64 (float64x1_t a, float64x1_t b)
    A32: VSUB.F64 Dd, Dn, Dm
    A64: FSUB Dd, Dn, Dm
    
    
    Instruction Documentation: [vsub_f64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_f64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsub_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vsub_s16 (int16x4_t a, int16x4_t b)
    A32: VSUB.I16 Dd, Dn, Dm
    A64: SUB Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vsub_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsub_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vsub_s32 (int32x2_t a, int32x2_t b)
    A32: VSUB.I32 Dd, Dn, Dm
    A64: SUB Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vsub_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsub_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x1_t vsub_s64 (int64x1_t a, int64x1_t b)
    A32: VSUB.I64 Dd, Dn, Dm
    A64: SUB Dd, Dn, Dm
    
    
    Instruction Documentation: [vsub_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsub_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vsub_s8 (int8x8_t a, int8x8_t b)
    A32: VSUB.I8 Dd, Dn, Dm
    A64: SUB Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vsub_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsub_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vsub_u16 (uint16x4_t a, uint16x4_t b)
    A32: VSUB.I16 Dd, Dn, Dm
    A64: SUB Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vsub_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsub_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vsub_u32 (uint32x2_t a, uint32x2_t b)
    A32: VSUB.I32 Dd, Dn, Dm
    A64: SUB Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vsub_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsub_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x1_t vsub_u64 (uint64x1_t a, uint64x1_t b)
    A32: VSUB.I64 Dd, Dn, Dm
    A64: SUB Dd, Dn, Dm
    
    
    Instruction Documentation: [vsub_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsub_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vsub_u8 (uint8x8_t a, uint8x8_t b)
    A32: VSUB.I8 Dd, Dn, Dm
    A64: SUB Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vsub_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsub_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vsubhn_high_s16 (int8x8_t r, int16x8_t a, int16x8_t b)
    A32: VSUBHN.I16 Dd+1, Qn, Qm
    A64: SUBHN2 Vd.16B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vsubhn_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vsubhn_high_s32 (int16x4_t r, int32x4_t a, int32x4_t b)
    A32: VSUBHN.I32 Dd+1, Qn, Qm
    A64: SUBHN2 Vd.8H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vsubhn_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_high_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vsubhn_high_s64 (int32x2_t r, int64x2_t a, int64x2_t b)
    A32: VSUBHN.I64 Dd+1, Qn, Qm
    A64: SUBHN2 Vd.4S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vsubhn_high_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vsubhn_high_u16 (uint8x8_t r, uint16x8_t a, uint16x8_t b)
    A32: VSUBHN.I16 Dd+1, Qn, Qm
    A64: SUBHN2 Vd.16B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vsubhn_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vsubhn_high_u32 (uint16x4_t r, uint32x4_t a, uint32x4_t b)
    A32: VSUBHN.I32 Dd+1, Qn, Qm
    A64: SUBHN2 Vd.8H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vsubhn_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_high_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vsubhn_high_u64 (uint32x2_t r, uint64x2_t a, uint64x2_t b)
    A32: VSUBHN.I64 Dd+1, Qn, Qm
    A64: SUBHN2 Vd.4S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vsubhn_high_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_high_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x8_t vsubhn_s16 (int16x8_t a, int16x8_t b)
    A32: VSUBHN.I16 Dd, Qn, Qm
    A64: SUBHN Vd.8B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vsubhn_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x4_t vsubhn_s32 (int32x4_t a, int32x4_t b)
    A32: VSUBHN.I32 Dd, Qn, Qm
    A64: SUBHN Vd.4H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vsubhn_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x2_t vsubhn_s64 (int64x2_t a, int64x2_t b)
    A32: VSUBHN.I64 Dd, Qn, Qm
    A64: SUBHN Vd.2S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vsubhn_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vsubhn_u16 (uint16x8_t a, uint16x8_t b)
    A32: VSUBHN.I16 Dd, Qn, Qm
    A64: SUBHN Vd.8B, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vsubhn_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vsubhn_u32 (uint32x4_t a, uint32x4_t b)
    A32: VSUBHN.I32 Dd, Qn, Qm
    A64: SUBHN Vd.4H, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vsubhn_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubhn_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vsubhn_u64 (uint64x2_t a, uint64x2_t b)
    A32: VSUBHN.I64 Dd, Qn, Qm
    A64: SUBHN Vd.2S, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vsubhn_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubhn_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vsubl_high_s16 (int16x8_t a, int16x8_t b)
    A32: VSUBL.S16 Qd, Dn+1, Dm+1
    A64: SSUBL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vsubl_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vsubl_high_s32 (int32x4_t a, int32x4_t b)
    A32: VSUBL.S32 Qd, Dn+1, Dm+1
    A64: SSUBL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vsubl_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_high_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vsubl_high_s8 (int8x16_t a, int8x16_t b)
    A32: VSUBL.S8 Qd, Dn+1, Dm+1
    A64: SSUBL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vsubl_high_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vsubl_high_u16 (uint16x8_t a, uint16x8_t b)
    A32: VSUBL.U16 Qd, Dn+1, Dm+1
    A64: USUBL2 Vd.4S, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vsubl_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vsubl_high_u32 (uint32x4_t a, uint32x4_t b)
    A32: VSUBL.U32 Qd, Dn+1, Dm+1
    A64: USUBL2 Vd.2D, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vsubl_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_high_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vsubl_high_u8 (uint8x16_t a, uint8x16_t b)
    A32: VSUBL.U8 Qd, Dn+1, Dm+1
    A64: USUBL2 Vd.8H, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vsubl_high_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_high_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vsubl_s16 (int16x4_t a, int16x4_t b)
    A32: VSUBL.S16 Qd, Dn, Dm
    A64: SSUBL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vsubl_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vsubl_s32 (int32x2_t a, int32x2_t b)
    A32: VSUBL.S32 Qd, Dn, Dm
    A64: SSUBL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vsubl_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vsubl_s8 (int8x8_t a, int8x8_t b)
    A32: VSUBL.S8 Qd, Dn, Dm
    A64: SSUBL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vsubl_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vsubl_u16 (uint16x4_t a, uint16x4_t b)
    A32: VSUBL.U16 Qd, Dn, Dm
    A64: USUBL Vd.4S, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vsubl_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vsubl_u32 (uint32x2_t a, uint32x2_t b)
    A32: VSUBL.U32 Qd, Dn, Dm
    A64: USUBL Vd.2D, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vsubl_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubl_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vsubl_u8 (uint8x8_t a, uint8x8_t b)
    A32: VSUBL.U8 Qd, Dn, Dm
    A64: USUBL Vd.8H, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vsubl_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubl_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32x4_t vsubq_f32 (float32x4_t a, float32x4_t b)
    A32: VSUB.F32 Qd, Qn, Qm
    A64: FSUB Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vsubq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vsubq_s16 (int16x8_t a, int16x8_t b)
    A32: VSUB.I16 Qd, Qn, Qm
    A64: SUB Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vsubq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vsubq_s32 (int32x4_t a, int32x4_t b)
    A32: VSUB.I32 Qd, Qn, Qm
    A64: SUB Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vsubq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubq_s64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vsubq_s64 (int64x2_t a, int64x2_t b)
    A32: VSUB.I64 Qd, Qn, Qm
    A64: SUB Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vsubq_s64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int8x16_t vsubq_s8 (int8x16_t a, int8x16_t b)
    A32: VSUB.I8 Qd, Qn, Qm
    A64: SUB Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vsubq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vsubq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VSUB.I16 Qd, Qn, Qm
    A64: SUB Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vsubq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vsubq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VSUB.I32 Qd, Qn, Qm
    A64: SUB Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vsubq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubq_u64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vsubq_u64 (uint64x2_t a, uint64x2_t b)
    A32: VSUB.I64 Qd, Qn, Qm
    A64: SUB Vd.2D, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vsubq_u64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vsubq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VSUB.I8 Qd, Qn, Qm
    A64: SUB Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vsubq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubs_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"float32_t vsubs_f32 (float32_t a, float32_t b)
    A32: VSUB.F32 Sd, Sn, Sm
    A64: FSUB Sd, Sn, Sm The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vsubs_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubs_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_high_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vsubw_high_s16 (int32x4_t a, int16x8_t b)
    A32: VSUBW.S16 Qd, Qn, Dm+1
    A64: SSUBW2 Vd.4S, Vn.4S, Vm.8H
    
    
    Instruction Documentation: [vsubw_high_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_high_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vsubw_high_s32 (int64x2_t a, int32x4_t b)
    A32: VSUBW.S32 Qd, Qn, Dm+1
    A64: SSUBW2 Vd.2D, Vn.2D, Vm.4S
    
    
    Instruction Documentation: [vsubw_high_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_high_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vsubw_high_s8 (int16x8_t a, int8x16_t b)
    A32: VSUBW.S8 Qd, Qn, Dm+1
    A64: SSUBW2 Vd.8H, Vn.8H, Vm.16B
    
    
    Instruction Documentation: [vsubw_high_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_high_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vsubw_high_u16 (uint32x4_t a, uint16x8_t b)
    A32: VSUBW.U16 Qd, Qn, Dm+1
    A64: USUBW2 Vd.4S, Vn.4S, Vm.8H
    
    
    Instruction Documentation: [vsubw_high_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_high_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vsubw_high_u32 (uint64x2_t a, uint32x4_t b)
    A32: VSUBW.U32 Qd, Qn, Dm+1
    A64: USUBW2 Vd.2D, Vn.2D, Vm.4S
    
    
    Instruction Documentation: [vsubw_high_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_high_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vsubw_high_u8 (uint16x8_t a, uint8x16_t b)
    A32: VSUBW.U8 Qd, Qn, Dm+1
    A64: USUBW2 Vd.8H, Vn.8H, Vm.16B
    
    
    Instruction Documentation: [vsubw_high_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_high_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int32x4_t vsubw_s16 (int32x4_t a, int16x4_t b)
    A32: VSUBW.S16 Qd, Qn, Dm
    A64: SSUBW Vd.4S, Vn.4S, Vm.4H
    
    
    Instruction Documentation: [vsubw_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int64x2_t vsubw_s32 (int64x2_t a, int32x2_t b)
    A32: VSUBW.S32 Qd, Qn, Dm
    A64: SSUBW Vd.2D, Vn.2D, Vm.2S
    
    
    Instruction Documentation: [vsubw_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"int16x8_t vsubw_s8 (int16x8_t a, int8x8_t b)
    A32: VSUBW.S8 Qd, Qn, Dm
    A64: SSUBW Vd.8H, Vn.8H, Vm.8B
    
    
    Instruction Documentation: [vsubw_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vsubw_u16 (uint32x4_t a, uint16x4_t b)
    A32: VSUBW.U16 Qd, Qn, Dm
    A64: USUBW Vd.4S, Vn.4S, Vm.4H
    
    
    Instruction Documentation: [vsubw_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint64x2_t vsubw_u32 (uint64x2_t a, uint32x2_t b)
    A32: VSUBW.U32 Qd, Qn, Dm
    A64: USUBW Vd.2D, Vn.2D, Vm.2S
    
    
    Instruction Documentation: [vsubw_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsubw_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vsubw_u8 (uint16x8_t a, uint8x8_t b)
    A32: VSUBW.U8 Qd, Qn, Dm
    A64: USUBW Vd.8H, Vn.8H, Vm.8B
    
    
    Instruction Documentation: [vsubw_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsubw_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtst_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vtst_f32 (float32x2_t a, float32x2_t b)
    A32: VTST.32 Dd, Dn, Dm
    A64: CMTST Vd.2S, Vn.2S, Vm.2S The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vtst_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtst_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vtst_s16 (int16x4_t a, int16x4_t b)
    A32: VTST.16 Dd, Dn, Dm
    A64: CMTST Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vtst_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtst_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vtst_s32 (int32x2_t a, int32x2_t b)
    A32: VTST.32 Dd, Dn, Dm
    A64: CMTST Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vtst_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtst_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vtst_s8 (int8x8_t a, int8x8_t b)
    A32: VTST.8 Dd, Dn, Dm
    A64: CMTST Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vtst_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtst_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x4_t vtst_u16 (uint16x4_t a, uint16x4_t b)
    A32: VTST.16 Dd, Dn, Dm
    A64: CMTST Vd.4H, Vn.4H, Vm.4H
    
    
    Instruction Documentation: [vtst_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtst_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x2_t vtst_u32 (uint32x2_t a, uint32x2_t b)
    A32: VTST.32 Dd, Dn, Dm
    A64: CMTST Vd.2S, Vn.2S, Vm.2S
    
    
    Instruction Documentation: [vtst_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtst_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x8_t vtst_u8 (uint8x8_t a, uint8x8_t b)
    A32: VTST.8 Dd, Dn, Dm
    A64: CMTST Vd.8B, Vn.8B, Vm.8B
    
    
    Instruction Documentation: [vtst_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtst_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtstq_f32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vtstq_f32 (float32x4_t a, float32x4_t b)
    A32: VTST.32 Qd, Qn, Qm
    A64: CMTST Vd.4S, Vn.4S, Vm.4S The above native signature does not exist. We provide this additional overload for consistency with the other scalar APIs.
    
    
    Instruction Documentation: [vtstq_f32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_f32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtstq_s16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vtstq_s16 (int16x8_t a, int16x8_t b)
    A32: VTST.16 Qd, Qn, Qm
    A64: CMTST Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vtstq_s16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtstq_s32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vtstq_s32 (int32x4_t a, int32x4_t b)
    A32: VTST.32 Qd, Qn, Qm
    A64: CMTST Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vtstq_s32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtstq_s8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vtstq_s8 (int8x16_t a, int8x16_t b)
    A32: VTST.8 Qd, Qn, Qm
    A64: CMTST Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vtstq_s8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_s8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtstq_u16"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint16x8_t vtstq_u16 (uint16x8_t a, uint16x8_t b)
    A32: VTST.16 Qd, Qn, Qm
    A64: CMTST Vd.8H, Vn.8H, Vm.8H
    
    
    Instruction Documentation: [vtstq_u16](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u16)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtstq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint32x4_t vtstq_u32 (uint32x4_t a, uint32x4_t b)
    A32: VTST.32 Qd, Qn, Qm
    A64: CMTST Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vtstq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vtstq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / ADVSIMD";
                descriptor.Description = @"uint8x16_t vtstq_u8 (uint8x16_t a, uint8x16_t b)
    A32: VTST.8 Qd, Qn, Qm
    A64: CMTST Vd.16B, Vn.16B, Vm.16B
    
    
    Instruction Documentation: [vtstq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vtstq_u8)";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.Arm
{
    public partial class AesIntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("vaesdq_u8", (Func<object, object, object>)vaesdq_u8);
            RegisterFunction("vaeseq_u8", (Func<object, object, object>)vaeseq_u8);
            RegisterFunction("vaesimcq_u8", (Func<object, object>)vaesimcq_u8);
            RegisterFunction("vaesmcq_u8", (Func<object, object>)vaesmcq_u8);
            RegisterFunction("vmull_high_p64", (Func<object, object, object>)vmull_high_p64);
            RegisterFunction("vmull_p64", (Func<object, object, object>)vmull_p64);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["vaesdq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / AES";
                descriptor.Description = @"uint8x16_t vaesdq_u8 (uint8x16_t data, uint8x16_t key)
    A32: AESD.8 Qd, Qm
    A64: AESD Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vaesdq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesdq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaeseq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / AES";
                descriptor.Description = @"uint8x16_t vaeseq_u8 (uint8x16_t data, uint8x16_t key)
    A32: AESE.8 Qd, Qm
    A64: AESE Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vaeseq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaeseq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaesimcq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / AES";
                descriptor.Description = @"uint8x16_t vaesimcq_u8 (uint8x16_t data)
    A32: AESIMC.8 Qd, Qm
    A64: AESIMC Vd.16B, Vn.16B
    
    
    Instruction Documentation: [vaesimcq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesimcq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vaesmcq_u8"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / AES";
                descriptor.Description = @"uint8x16_t vaesmcq_u8 (uint8x16_t data)
    A32: AESMC.8 Qd, Qm
    A64: AESMC V>.16B, Vn.16B
    
    
    Instruction Documentation: [vaesmcq_u8](https://developer.arm.com/architectures/instruction-sets/intrinsics/vaesmcq_u8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_high_p64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / AES";
                descriptor.Description = @"poly128_t vmull_high_p64 (poly64x2_t a, poly64x2_t b)
    A32: VMULL.P8 Qd, Dn+1, Dm+1
    A64: PMULL2 Vd.1Q, Vn.2D, Vm.2D
    
    
    Instruction Documentation: [vmull_high_p64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_high_p64)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vmull_p64"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / AES";
                descriptor.Description = @"poly128_t vmull_p64 (poly64_t a, poly64_t b)
    A32: VMULL.P8 Qd, Dn, Dm
    A64: PMULL Vd.1Q, Vn.1D, Vm.1D
    
    
    Instruction Documentation: [vmull_p64](https://developer.arm.com/architectures/instruction-sets/intrinsics/vmull_p64)";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class AesIntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_aesdec_si128", (Func<object, object, object>)mm_aesdec_si128);
            RegisterFunction("mm_aesdeclast_si128", (Func<object, object, object>)mm_aesdeclast_si128);
            RegisterFunction("mm_aesenc_si128", (Func<object, object, object>)mm_aesenc_si128);
            RegisterFunction("mm_aesenclast_si128", (Func<object, object, object>)mm_aesenclast_si128);
            RegisterFunction("mm_aesimc_si128", (Func<object, object>)mm_aesimc_si128);
            RegisterFunction("mm_aeskeygenassist_si128", (Func<object, byte, object>)mm_aeskeygenassist_si128);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_aesdec_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AES";
                descriptor.Description = @"__m128i _mm_aesdec_si128 (__m128i a, __m128i RoundKey)
    AESDEC xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_aesdeclast_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AES";
                descriptor.Description = @"__m128i _mm_aesdeclast_si128 (__m128i a, __m128i RoundKey)
    AESDECLAST xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_aesenc_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AES";
                descriptor.Description = @"__m128i _mm_aesenc_si128 (__m128i a, __m128i RoundKey)
    AESENC xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_aesenclast_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AES";
                descriptor.Description = @"__m128i _mm_aesenclast_si128 (__m128i a, __m128i RoundKey)
    AESENCLAST xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_aesimc_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AES";
                descriptor.Description = @"__m128i _mm_aesimc_si128 (__m128i a)
    AESIMC xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_aeskeygenassist_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AES";
                descriptor.Description = @"__m128i _mm_aeskeygenassist_si128 (__m128i a, const int imm8)
    AESKEYGENASSIST xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules
{
    public partial class AllModule
    {
        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptor;
                descriptor.Category = "Modules (e.g `import Files`)";
                descriptor.Description = @"Import all modules.";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Avx2IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_blend_epi32", (Func<object, object, byte, object>)mm_blend_epi32);
            RegisterFunction("mm_broadcastb_epi8", (Func<object, object>)mm_broadcastb_epi8);
            RegisterFunction("mm_broadcastd_epi32", (Func<object, object>)mm_broadcastd_epi32);
            RegisterFunction("mm_broadcastq_epi64", (Func<object, object>)mm_broadcastq_epi64);
            RegisterFunction("mm_broadcastsd_pd", (Func<object, object>)mm_broadcastsd_pd);
            RegisterFunction("mm_broadcastss_ps", (Func<object, object>)mm_broadcastss_ps);
            RegisterFunction("mm_broadcastw_epi16", (Func<object, object>)mm_broadcastw_epi16);
            RegisterFunction("mm_i32gather_epi32", (Func<object, object, byte, object>)mm_i32gather_epi32);
            RegisterFunction("mm_i32gather_epi64", (Func<object, object, byte, object>)mm_i32gather_epi64);
            RegisterFunction("mm_i32gather_pd", (Func<object, object, byte, object>)mm_i32gather_pd);
            RegisterFunction("mm_i32gather_ps", (Func<object, object, byte, object>)mm_i32gather_ps);
            RegisterFunction("mm_i64gather_epi32", (Func<object, object, byte, object>)mm_i64gather_epi32);
            RegisterFunction("mm_i64gather_epi64", (Func<object, object, byte, object>)mm_i64gather_epi64);
            RegisterFunction("mm_i64gather_pd", (Func<object, object, byte, object>)mm_i64gather_pd);
            RegisterFunction("mm_i64gather_ps", (Func<object, object, byte, object>)mm_i64gather_ps);
            RegisterFunction("mm_mask_i32gather_epi32", (Func<object, object, object, object, byte, object>)mm_mask_i32gather_epi32);
            RegisterFunction("mm_mask_i32gather_epi64", (Func<object, object, object, object, byte, object>)mm_mask_i32gather_epi64);
            RegisterFunction("mm_mask_i32gather_pd", (Func<object, object, object, object, byte, object>)mm_mask_i32gather_pd);
            RegisterFunction("mm_mask_i32gather_ps", (Func<object, object, object, object, byte, object>)mm_mask_i32gather_ps);
            RegisterFunction("mm_mask_i64gather_epi32", (Func<object, object, object, object, byte, object>)mm_mask_i64gather_epi32);
            RegisterFunction("mm_mask_i64gather_epi64", (Func<object, object, object, object, byte, object>)mm_mask_i64gather_epi64);
            RegisterFunction("mm_mask_i64gather_pd", (Func<object, object, object, object, byte, object>)mm_mask_i64gather_pd);
            RegisterFunction("mm_mask_i64gather_ps", (Func<object, object, object, object, byte, object>)mm_mask_i64gather_ps);
            RegisterFunction("mm_maskload_epi32", (Func<object, object, object>)mm_maskload_epi32);
            RegisterFunction("mm_maskload_epi64", (Func<object, object, object>)mm_maskload_epi64);
            RegisterAction("mm_maskstore_epi32", (Action<object, object, object>)mm_maskstore_epi32);
            RegisterAction("mm_maskstore_epi64", (Action<object, object, object>)mm_maskstore_epi64);
            RegisterFunction("mm_sllv_epi32", (Func<object, object, object>)mm_sllv_epi32);
            RegisterFunction("mm_sllv_epi64", (Func<object, object, object>)mm_sllv_epi64);
            RegisterFunction("mm_srav_epi32", (Func<object, object, object>)mm_srav_epi32);
            RegisterFunction("mm_srlv_epi32", (Func<object, object, object>)mm_srlv_epi32);
            RegisterFunction("mm_srlv_epi64", (Func<object, object, object>)mm_srlv_epi64);
            RegisterFunction("mm256_abs_epi16", (Func<object, object>)mm256_abs_epi16);
            RegisterFunction("mm256_abs_epi32", (Func<object, object>)mm256_abs_epi32);
            RegisterFunction("mm256_abs_epi8", (Func<object, object>)mm256_abs_epi8);
            RegisterFunction("mm256_add_epi16", (Func<object, object, object>)mm256_add_epi16);
            RegisterFunction("mm256_add_epi32", (Func<object, object, object>)mm256_add_epi32);
            RegisterFunction("mm256_add_epi64", (Func<object, object, object>)mm256_add_epi64);
            RegisterFunction("mm256_add_epi8", (Func<object, object, object>)mm256_add_epi8);
            RegisterFunction("mm256_adds_epi16", (Func<object, object, object>)mm256_adds_epi16);
            RegisterFunction("mm256_adds_epi8", (Func<object, object, object>)mm256_adds_epi8);
            RegisterFunction("mm256_adds_epu16", (Func<object, object, object>)mm256_adds_epu16);
            RegisterFunction("mm256_adds_epu8", (Func<object, object, object>)mm256_adds_epu8);
            RegisterFunction("mm256_alignr_epi8", (Func<object, object, byte, object>)mm256_alignr_epi8);
            RegisterFunction("mm256_and_si256", (Func<object, object, object>)mm256_and_si256);
            RegisterFunction("mm256_andnot_si256", (Func<object, object, object>)mm256_andnot_si256);
            RegisterFunction("mm256_avg_epu16", (Func<object, object, object>)mm256_avg_epu16);
            RegisterFunction("mm256_avg_epu8", (Func<object, object, object>)mm256_avg_epu8);
            RegisterFunction("mm256_blend_epi16", (Func<object, object, byte, object>)mm256_blend_epi16);
            RegisterFunction("mm256_blend_epi32", (Func<object, object, byte, object>)mm256_blend_epi32);
            RegisterFunction("mm256_blendv_epi8", (Func<object, object, object, object>)mm256_blendv_epi8);
            RegisterFunction("mm256_broadcastb_epi8", (Func<object, object>)mm256_broadcastb_epi8);
            RegisterFunction("mm256_broadcastd_epi32", (Func<object, object>)mm256_broadcastd_epi32);
            RegisterFunction("mm256_broadcastq_epi64", (Func<object, object>)mm256_broadcastq_epi64);
            RegisterFunction("mm256_broadcastsd_pd", (Func<object, object>)mm256_broadcastsd_pd);
            RegisterFunction("mm256_broadcastsi128_si256", (Func<object, object>)mm256_broadcastsi128_si256);
            RegisterFunction("mm256_broadcastss_ps", (Func<object, object>)mm256_broadcastss_ps);
            RegisterFunction("mm256_broadcastw_epi16", (Func<object, object>)mm256_broadcastw_epi16);
            RegisterFunction("mm256_bslli_epi128", (Func<object, byte, object>)mm256_bslli_epi128);
            RegisterFunction("mm256_bsrli_epi128", (Func<object, byte, object>)mm256_bsrli_epi128);
            RegisterFunction("mm256_cmpeq_epi16", (Func<object, object, object>)mm256_cmpeq_epi16);
            RegisterFunction("mm256_cmpeq_epi32", (Func<object, object, object>)mm256_cmpeq_epi32);
            RegisterFunction("mm256_cmpeq_epi64", (Func<object, object, object>)mm256_cmpeq_epi64);
            RegisterFunction("mm256_cmpeq_epi8", (Func<object, object, object>)mm256_cmpeq_epi8);
            RegisterFunction("mm256_cmpgt_epi16", (Func<object, object, object>)mm256_cmpgt_epi16);
            RegisterFunction("mm256_cmpgt_epi32", (Func<object, object, object>)mm256_cmpgt_epi32);
            RegisterFunction("mm256_cmpgt_epi64", (Func<object, object, object>)mm256_cmpgt_epi64);
            RegisterFunction("mm256_cmpgt_epi8", (Func<object, object, object>)mm256_cmpgt_epi8);
            RegisterFunction("mm256_cvtepi16_epi32", (Func<object, object>)mm256_cvtepi16_epi32);
            RegisterFunction("mm256_cvtepi16_epi64", (Func<object, object>)mm256_cvtepi16_epi64);
            RegisterFunction("mm256_cvtepi32_epi64", (Func<object, object>)mm256_cvtepi32_epi64);
            RegisterFunction("mm256_cvtepi8_epi16", (Func<object, object>)mm256_cvtepi8_epi16);
            RegisterFunction("mm256_cvtepi8_epi32", (Func<object, object>)mm256_cvtepi8_epi32);
            RegisterFunction("mm256_cvtepi8_epi64", (Func<object, object>)mm256_cvtepi8_epi64);
            RegisterFunction("mm256_cvtepu16_epi32", (Func<object, object>)mm256_cvtepu16_epi32);
            RegisterFunction("mm256_cvtepu16_epi64", (Func<object, object>)mm256_cvtepu16_epi64);
            RegisterFunction("mm256_cvtepu32_epi64", (Func<object, object>)mm256_cvtepu32_epi64);
            RegisterFunction("mm256_cvtepu8_epi16", (Func<object, object>)mm256_cvtepu8_epi16);
            RegisterFunction("mm256_cvtepu8_epi32", (Func<object, object>)mm256_cvtepu8_epi32);
            RegisterFunction("mm256_cvtepu8_epi64", (Func<object, object>)mm256_cvtepu8_epi64);
            RegisterFunction("mm256_cvtsi256_si32", (Func<object, int>)mm256_cvtsi256_si32);
            RegisterFunction("mm256_extracti128_si256", (Func<object, byte, object>)mm256_extracti128_si256);
            RegisterFunction("mm256_hadd_epi16", (Func<object, object, object>)mm256_hadd_epi16);
            RegisterFunction("mm256_hadd_epi32", (Func<object, object, object>)mm256_hadd_epi32);
            RegisterFunction("mm256_hadds_epi16", (Func<object, object, object>)mm256_hadds_epi16);
            RegisterFunction("mm256_hsub_epi16", (Func<object, object, object>)mm256_hsub_epi16);
            RegisterFunction("mm256_hsub_epi32", (Func<object, object, object>)mm256_hsub_epi32);
            RegisterFunction("mm256_hsubs_epi16", (Func<object, object, object>)mm256_hsubs_epi16);
            RegisterFunction("mm256_i32gather_epi32", (Func<object, object, byte, object>)mm256_i32gather_epi32);
            RegisterFunction("mm256_i32gather_epi64", (Func<object, object, byte, object>)mm256_i32gather_epi64);
            RegisterFunction("mm256_i32gather_pd", (Func<object, object, byte, object>)mm256_i32gather_pd);
            RegisterFunction("mm256_i32gather_ps", (Func<object, object, byte, object>)mm256_i32gather_ps);
            RegisterFunction("mm256_i64gather_epi32", (Func<object, object, byte, object>)mm256_i64gather_epi32);
            RegisterFunction("mm256_i64gather_epi64", (Func<object, object, byte, object>)mm256_i64gather_epi64);
            RegisterFunction("mm256_i64gather_pd", (Func<object, object, byte, object>)mm256_i64gather_pd);
            RegisterFunction("mm256_i64gather_ps", (Func<object, object, byte, object>)mm256_i64gather_ps);
            RegisterFunction("mm256_inserti128_si256", (Func<object, object, byte, object>)mm256_inserti128_si256);
            RegisterFunction("mm256_madd_epi16", (Func<object, object, object>)mm256_madd_epi16);
            RegisterFunction("mm256_maddubs_epi16", (Func<object, object, object>)mm256_maddubs_epi16);
            RegisterFunction("mm256_mask_i32gather_epi32", (Func<object, object, object, object, byte, object>)mm256_mask_i32gather_epi32);
            RegisterFunction("mm256_mask_i32gather_epi64", (Func<object, object, object, object, byte, object>)mm256_mask_i32gather_epi64);
            RegisterFunction("mm256_mask_i32gather_pd", (Func<object, object, object, object, byte, object>)mm256_mask_i32gather_pd);
            RegisterFunction("mm256_mask_i32gather_ps", (Func<object, object, object, object, byte, object>)mm256_mask_i32gather_ps);
            RegisterFunction("mm256_mask_i64gather_epi32", (Func<object, object, object, object, byte, object>)mm256_mask_i64gather_epi32);
            RegisterFunction("mm256_mask_i64gather_epi64", (Func<object, object, object, object, byte, object>)mm256_mask_i64gather_epi64);
            RegisterFunction("mm256_mask_i64gather_pd", (Func<object, object, object, object, byte, object>)mm256_mask_i64gather_pd);
            RegisterFunction("mm256_mask_i64gather_ps", (Func<object, object, object, object, byte, object>)mm256_mask_i64gather_ps);
            RegisterFunction("mm256_maskload_epi32", (Func<object, object, object>)mm256_maskload_epi32);
            RegisterFunction("mm256_maskload_epi64", (Func<object, object, object>)mm256_maskload_epi64);
            RegisterAction("mm256_maskstore_epi32", (Action<object, object, object>)mm256_maskstore_epi32);
            RegisterAction("mm256_maskstore_epi64", (Action<object, object, object>)mm256_maskstore_epi64);
            RegisterFunction("mm256_max_epi16", (Func<object, object, object>)mm256_max_epi16);
            RegisterFunction("mm256_max_epi32", (Func<object, object, object>)mm256_max_epi32);
            RegisterFunction("mm256_max_epi8", (Func<object, object, object>)mm256_max_epi8);
            RegisterFunction("mm256_max_epu16", (Func<object, object, object>)mm256_max_epu16);
            RegisterFunction("mm256_max_epu32", (Func<object, object, object>)mm256_max_epu32);
            RegisterFunction("mm256_max_epu8", (Func<object, object, object>)mm256_max_epu8);
            RegisterFunction("mm256_min_epi16", (Func<object, object, object>)mm256_min_epi16);
            RegisterFunction("mm256_min_epi32", (Func<object, object, object>)mm256_min_epi32);
            RegisterFunction("mm256_min_epi8", (Func<object, object, object>)mm256_min_epi8);
            RegisterFunction("mm256_min_epu16", (Func<object, object, object>)mm256_min_epu16);
            RegisterFunction("mm256_min_epu32", (Func<object, object, object>)mm256_min_epu32);
            RegisterFunction("mm256_min_epu8", (Func<object, object, object>)mm256_min_epu8);
            RegisterFunction("mm256_movemask_epi8", (Func<object, int>)mm256_movemask_epi8);
            RegisterFunction("mm256_mpsadbw_epu8", (Func<object, object, byte, object>)mm256_mpsadbw_epu8);
            RegisterFunction("mm256_mul_epi32", (Func<object, object, object>)mm256_mul_epi32);
            RegisterFunction("mm256_mul_epu32", (Func<object, object, object>)mm256_mul_epu32);
            RegisterFunction("mm256_mulhi_epi16", (Func<object, object, object>)mm256_mulhi_epi16);
            RegisterFunction("mm256_mulhi_epu16", (Func<object, object, object>)mm256_mulhi_epu16);
            RegisterFunction("mm256_mulhrs_epi16", (Func<object, object, object>)mm256_mulhrs_epi16);
            RegisterFunction("mm256_mullo_epi16", (Func<object, object, object>)mm256_mullo_epi16);
            RegisterFunction("mm256_mullo_epi32", (Func<object, object, object>)mm256_mullo_epi32);
            RegisterFunction("mm256_or_si256", (Func<object, object, object>)mm256_or_si256);
            RegisterFunction("mm256_packs_epi16", (Func<object, object, object>)mm256_packs_epi16);
            RegisterFunction("mm256_packs_epi32", (Func<object, object, object>)mm256_packs_epi32);
            RegisterFunction("mm256_packus_epi16", (Func<object, object, object>)mm256_packus_epi16);
            RegisterFunction("mm256_packus_epi32", (Func<object, object, object>)mm256_packus_epi32);
            RegisterFunction("mm256_permute2x128_si256", (Func<object, object, byte, object>)mm256_permute2x128_si256);
            RegisterFunction("mm256_permute4x64_epi64", (Func<object, byte, object>)mm256_permute4x64_epi64);
            RegisterFunction("mm256_permute4x64_pd", (Func<object, byte, object>)mm256_permute4x64_pd);
            RegisterFunction("mm256_permutevar8x32_epi32", (Func<object, object, object>)mm256_permutevar8x32_epi32);
            RegisterFunction("mm256_permutevar8x32_ps", (Func<object, object, object>)mm256_permutevar8x32_ps);
            RegisterFunction("mm256_sad_epu8", (Func<object, object, object>)mm256_sad_epu8);
            RegisterFunction("mm256_shuffle_epi32", (Func<object, byte, object>)mm256_shuffle_epi32);
            RegisterFunction("mm256_shuffle_epi8", (Func<object, object, object>)mm256_shuffle_epi8);
            RegisterFunction("mm256_shufflehi_epi16", (Func<object, byte, object>)mm256_shufflehi_epi16);
            RegisterFunction("mm256_shufflelo_epi16", (Func<object, byte, object>)mm256_shufflelo_epi16);
            RegisterFunction("mm256_sign_epi16", (Func<object, object, object>)mm256_sign_epi16);
            RegisterFunction("mm256_sign_epi32", (Func<object, object, object>)mm256_sign_epi32);
            RegisterFunction("mm256_sign_epi8", (Func<object, object, object>)mm256_sign_epi8);
            RegisterFunction("mm256_sll_epi16", (Func<object, object, object>)mm256_sll_epi16);
            RegisterFunction("mm256_sll_epi32", (Func<object, object, object>)mm256_sll_epi32);
            RegisterFunction("mm256_sll_epi64", (Func<object, object, object>)mm256_sll_epi64);
            RegisterFunction("mm256_slli_epi16", (Func<object, byte, object>)mm256_slli_epi16);
            RegisterFunction("mm256_slli_epi32", (Func<object, byte, object>)mm256_slli_epi32);
            RegisterFunction("mm256_slli_epi64", (Func<object, byte, object>)mm256_slli_epi64);
            RegisterFunction("mm256_sllv_epi32", (Func<object, object, object>)mm256_sllv_epi32);
            RegisterFunction("mm256_sllv_epi64", (Func<object, object, object>)mm256_sllv_epi64);
            RegisterFunction("mm256_srai_epi16", (Func<object, byte, object>)mm256_srai_epi16);
            RegisterFunction("mm256_srai_epi32", (Func<object, byte, object>)mm256_srai_epi32);
            RegisterFunction("mm256_srav_epi32", (Func<object, object, object>)mm256_srav_epi32);
            RegisterFunction("mm256_srl_epi16", (Func<object, object, object>)mm256_srl_epi16);
            RegisterFunction("mm256_srl_epi32", (Func<object, object, object>)mm256_srl_epi32);
            RegisterFunction("mm256_srl_epi64", (Func<object, object, object>)mm256_srl_epi64);
            RegisterFunction("mm256_srli_epi16", (Func<object, byte, object>)mm256_srli_epi16);
            RegisterFunction("mm256_srli_epi32", (Func<object, byte, object>)mm256_srli_epi32);
            RegisterFunction("mm256_srli_epi64", (Func<object, byte, object>)mm256_srli_epi64);
            RegisterFunction("mm256_srlv_epi32", (Func<object, object, object>)mm256_srlv_epi32);
            RegisterFunction("mm256_srlv_epi64", (Func<object, object, object>)mm256_srlv_epi64);
            RegisterFunction("mm256_stream_load_si256", (Func<object, object>)mm256_stream_load_si256);
            RegisterFunction("mm256_sub_epi16", (Func<object, object, object>)mm256_sub_epi16);
            RegisterFunction("mm256_sub_epi32", (Func<object, object, object>)mm256_sub_epi32);
            RegisterFunction("mm256_sub_epi64", (Func<object, object, object>)mm256_sub_epi64);
            RegisterFunction("mm256_sub_epi8", (Func<object, object, object>)mm256_sub_epi8);
            RegisterFunction("mm256_subs_epi16", (Func<object, object, object>)mm256_subs_epi16);
            RegisterFunction("mm256_subs_epi8", (Func<object, object, object>)mm256_subs_epi8);
            RegisterFunction("mm256_subs_epu16", (Func<object, object, object>)mm256_subs_epu16);
            RegisterFunction("mm256_subs_epu8", (Func<object, object, object>)mm256_subs_epu8);
            RegisterFunction("mm256_unpackhi_epi16", (Func<object, object, object>)mm256_unpackhi_epi16);
            RegisterFunction("mm256_unpackhi_epi32", (Func<object, object, object>)mm256_unpackhi_epi32);
            RegisterFunction("mm256_unpackhi_epi64", (Func<object, object, object>)mm256_unpackhi_epi64);
            RegisterFunction("mm256_unpackhi_epi8", (Func<object, object, object>)mm256_unpackhi_epi8);
            RegisterFunction("mm256_unpacklo_epi16", (Func<object, object, object>)mm256_unpacklo_epi16);
            RegisterFunction("mm256_unpacklo_epi32", (Func<object, object, object>)mm256_unpacklo_epi32);
            RegisterFunction("mm256_unpacklo_epi64", (Func<object, object, object>)mm256_unpacklo_epi64);
            RegisterFunction("mm256_unpacklo_epi8", (Func<object, object, object>)mm256_unpacklo_epi8);
            RegisterFunction("mm256_xor_si256", (Func<object, object, object>)mm256_xor_si256);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_blend_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Blend packed 32-bit integers from ""a"" and ""b"" using control mask ""imm8"", and store the results in ""dst"".
    
    __m128i _mm_blend_epi32 (__m128i a, __m128i b, const int imm8)
    VPBLENDD xmm, xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_broadcastb_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low packed 8-bit integer from ""a"" to all elements of ""dst"".
    
    __m128i _mm_broadcastb_epi8 (__m128i a)
    VPBROADCASTB xmm, m8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_broadcastd_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low packed 32-bit integer from ""a"" to all elements of ""dst"".
    
    __m128i _mm_broadcastd_epi32 (__m128i a)
    VPBROADCASTD xmm, m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_broadcastq_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low packed 64-bit integer from ""a"" to all elements of ""dst"".
    
    __m128i _mm_broadcastq_epi64 (__m128i a)
    VPBROADCASTQ xmm, m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_broadcastsd_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low double-precision (64-bit) floating-point element from ""a"" to all elements of ""dst"".
    
    __m128d _mm_broadcastsd_pd (__m128d a)
    VMOVDDUP xmm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_broadcastss_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low single-precision (32-bit) floating-point element from ""a"" to all elements of ""dst"".
    
    __m128 _mm_broadcastss_ps (__m128 a)
    VBROADCASTSS xmm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_broadcastw_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low packed 16-bit integer from ""a"" to all elements of ""dst"".
    
    __m128i _mm_broadcastw_epi16 (__m128i a)
    VPBROADCASTW xmm, m16";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_i32gather_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m128i _mm_i32gather_epi32 (int const* base_addr, __m128i vindex, const int scale)
    VPGATHERDD xmm, vm32x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_i32gather_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m128i _mm_i32gather_epi64 (__int64 const* base_addr, __m128i vindex, const int scale)
    VPGATHERDQ xmm, vm32x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_i32gather_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m128d _mm_i32gather_pd (double const* base_addr, __m128i vindex, const int scale)
    VGATHERDPD xmm, vm32x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_i32gather_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m128 _mm_i32gather_ps (float const* base_addr, __m128i vindex, const int scale)
    VGATHERDPS xmm, vm32x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_i64gather_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m128i _mm_i64gather_epi32 (int const* base_addr, __m128i vindex, const int scale)
    VPGATHERQD xmm, vm64x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_i64gather_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m128i _mm_i64gather_epi64 (__int64 const* base_addr, __m128i vindex, const int scale)
    VPGATHERQQ xmm, vm64x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_i64gather_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m128d _mm_i64gather_pd (double const* base_addr, __m128i vindex, const int scale)
    VGATHERQPD xmm, vm64x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_i64gather_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m128 _mm_i64gather_ps (float const* base_addr, __m128i vindex, const int scale)
    VGATHERQPS xmm, vm64x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mask_i32gather_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m128i _mm_mask_i32gather_epi32 (__m128i src, int const* base_addr, __m128i vindex, __m128i mask, const int scale)
    VPGATHERDD xmm, vm32x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mask_i32gather_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m128i _mm_mask_i32gather_epi64 (__m128i src, __int64 const* base_addr, __m128i vindex, __m128i mask, const int scale)
    VPGATHERDQ xmm, vm32x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mask_i32gather_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m128d _mm_mask_i32gather_pd (__m128d src, double const* base_addr, __m128i vindex, __m128d mask, const int scale)
    VGATHERDPD xmm, vm32x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mask_i32gather_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m128 _mm_mask_i32gather_ps (__m128 src, float const* base_addr, __m128i vindex, __m128 mask, const int scale)
    VGATHERDPS xmm, vm32x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mask_i64gather_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m128i _mm_mask_i64gather_epi32 (__m128i src, int const* base_addr, __m128i vindex, __m128i mask, const int scale)
    VPGATHERQD xmm, vm64x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mask_i64gather_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m128i _mm_mask_i64gather_epi64 (__m128i src, __int64 const* base_addr, __m128i vindex, __m128i mask, const int scale)
    VPGATHERQQ xmm, vm64x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mask_i64gather_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m128d _mm_mask_i64gather_pd (__m128d src, double const* base_addr, __m128i vindex, __m128d mask, const int scale)
    VGATHERQPD xmm, vm64x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mask_i64gather_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m128 _mm_mask_i64gather_ps (__m128 src, float const* base_addr, __m128i vindex, __m128 mask, const int scale)
    VGATHERQPS xmm, vm64x, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_maskload_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Load packed 32-bit integers from memory into ""dst"" using ""mask"" (elements are zeroed out when the highest bit is not set in the corresponding element).
    
    __m128i _mm_maskload_epi32 (int const* mem_addr, __m128i mask)
    VPMASKMOVD xmm, xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_maskload_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Load packed 64-bit integers from memory into ""dst"" using ""mask"" (elements are zeroed out when the highest bit is not set in the corresponding element).
    
    __m128i _mm_maskload_epi64 (__int64 const* mem_addr, __m128i mask)
    VPMASKMOVQ xmm, xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_maskstore_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Store packed 32-bit integers from ""a"" into memory using ""mask"" (elements are not stored when the highest bit is not set in the corresponding element).
    
    void _mm_maskstore_epi32 (int* mem_addr, __m128i mask, __m128i a)
    VPMASKMOVD m128, xmm, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_maskstore_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Store packed 64-bit integers from ""a"" into memory using ""mask"" (elements are not stored when the highest bit is not set in the corresponding element).
    
    void _mm_maskstore_epi64 (__int64* mem_addr, __m128i mask, __m128i a)
    VPMASKMOVQ m128, xmm, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_sllv_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" left by the amount specified by the corresponding element in ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_sllv_epi32 (__m128i a, __m128i count)
    VPSLLVD xmm, ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sllv_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" left by the amount specified by the corresponding element in ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_sllv_epi64 (__m128i a, __m128i count)
    VPSLLVQ xmm, ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_srav_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" right by the amount specified by the corresponding element in ""count"" while shifting in sign bits, and store the results in ""dst"".
    
    __m128i _mm_srav_epi32 (__m128i a, __m128i count)
    VPSRAVD xmm, xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_srlv_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" right by the amount specified by the corresponding element in ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_srlv_epi32 (__m128i a, __m128i count)
    VPSRLVD xmm, xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_srlv_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" right by the amount specified by the corresponding element in ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_srlv_epi64 (__m128i a, __m128i count)
    VPSRLVQ xmm, xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_abs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compute the absolute value of packed 16-bit integers in ""a"", and store the unsigned results in ""dst"".
    
    __m256i _mm256_abs_epi16 (__m256i a)
    VPABSW ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_abs_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compute the absolute value of packed 32-bit integers in ""a"", and store the unsigned results in ""dst"".
    
    __m256i _mm256_abs_epi32 (__m256i a)
    VPABSD ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_abs_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compute the absolute value of packed 8-bit integers in ""a"", and store the unsigned results in ""dst"".
    
    __m256i _mm256_abs_epi8 (__m256i a)
    VPABSB ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_add_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Add packed 16-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_add_epi16 (__m256i a, __m256i b)
    VPADDW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_add_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Add packed 32-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_add_epi32 (__m256i a, __m256i b)
    VPADDD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_add_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Add packed 64-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_add_epi64 (__m256i a, __m256i b)
    VPADDQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_add_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Add packed 8-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_add_epi8 (__m256i a, __m256i b)
    VPADDB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_adds_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Add packed 16-bit integers in ""a"" and ""b"" using saturation, and store the results in ""dst"".
    
    __m256i _mm256_adds_epi16 (__m256i a, __m256i b)
    VPADDSW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_adds_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Add packed 8-bit integers in ""a"" and ""b"" using saturation, and store the results in ""dst"".
    
    __m256i _mm256_adds_epi8 (__m256i a, __m256i b)
    VPADDSB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_adds_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Add packed unsigned 16-bit integers in ""a"" and ""b"" using saturation, and store the results in ""dst"".
    
    __m256i _mm256_adds_epu16 (__m256i a, __m256i b)
    VPADDUSW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_adds_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Add packed unsigned 8-bit integers in ""a"" and ""b"" using saturation, and store the results in ""dst"".
    
    __m256i _mm256_adds_epu8 (__m256i a, __m256i b)
    VPADDUSB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_alignr_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Concatenate pairs of 16-byte blocks in ""a"" and ""b"" into a 32-byte temporary result, shift the result right by ""count"" bytes, and store the low 16 bytes in ""dst"".
    
    __m256i _mm256_alignr_epi8 (__m256i a, __m256i b, const int count)
    VPALIGNR ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_and_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compute the bitwise AND of 256 bits (representing integer data) in ""a"" and ""b"", and store the result in ""dst"".
    
    __m256i _mm256_and_si256 (__m256i a, __m256i b)
    VPAND ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_andnot_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compute the bitwise NOT of 256 bits (representing integer data) in ""a"" and then AND with ""b"", and store the result in ""dst"".
    
    __m256i _mm256_andnot_si256 (__m256i a, __m256i b)
    VPANDN ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_avg_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Average packed unsigned 16-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_avg_epu16 (__m256i a, __m256i b)
    VPAVGW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_avg_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Average packed unsigned 8-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_avg_epu8 (__m256i a, __m256i b)
    VPAVGB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_blend_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Blend packed 16-bit integers from ""a"" and ""b"" within 128-bit lanes using control mask ""imm8"", and store the results in ""dst"".
    
    __m256i _mm256_blend_epi16 (__m256i a, __m256i b, const int imm8)
    VPBLENDW ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_blend_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Blend packed 32-bit integers from ""a"" and ""b"" using control mask ""imm8"", and store the results in ""dst"".
    
    __m256i _mm256_blend_epi32 (__m256i a, __m256i b, const int imm8)
    VPBLENDD ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_blendv_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Blend packed 8-bit integers from ""a"" and ""b"" using ""mask"", and store the results in ""dst"".
    
    __m256i _mm256_blendv_epi8 (__m256i a, __m256i b, __m256i mask)
    VPBLENDVB ymm, ymm, ymm/m256, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_broadcastb_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low packed 8-bit integer from ""a"" to all elements of ""dst"".
    
    __m256i _mm256_broadcastb_epi8 (__m128i a)
    VPBROADCASTB ymm, m8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_broadcastd_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low packed 32-bit integer from ""a"" to all elements of ""dst"".
    
    __m256i _mm256_broadcastd_epi32 (__m128i a)
    VPBROADCASTD ymm, m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_broadcastq_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low packed 64-bit integer from ""a"" to all elements of ""dst"".
    
    __m256i _mm256_broadcastq_epi64 (__m128i a)
    VPBROADCASTQ ymm, m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_broadcastsd_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low double-precision (64-bit) floating-point element from ""a"" to all elements of ""dst"".
    
    __m256d _mm256_broadcastsd_pd (__m128d a)
    VBROADCASTSD ymm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_broadcastsi128_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast 128 bits of integer data from ""a"" to all 128-bit lanes in ""dst"".
    
    __m256i _mm256_broadcastsi128_si256 (__m128i a)
    VBROADCASTI128 ymm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_broadcastss_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low single-precision (32-bit) floating-point element from ""a"" to all elements of ""dst"".
    
    __m256 _mm256_broadcastss_ps (__m128 a)
    VBROADCASTSS ymm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_broadcastw_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Broadcast the low packed 16-bit integer from ""a"" to all elements of ""dst"".
    
    __m256i _mm256_broadcastw_epi16 (__m128i a)
    VPBROADCASTW ymm, m16";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_bslli_epi128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift 128-bit lanes in ""a"" left by ""imm8"" bytes while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_bslli_epi128 (__m256i a, const int imm8)
    VPSLLDQ ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_bsrli_epi128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift 128-bit lanes in ""a"" right by ""imm8"" bytes while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_bsrli_epi128 (__m256i a, const int imm8)
    VPSRLDQ ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpeq_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 16-bit integers in ""a"" and ""b"" for equality, and store the results in ""dst"".
    
    __m256i _mm256_cmpeq_epi16 (__m256i a, __m256i b)
    VPCMPEQW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpeq_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 32-bit integers in ""a"" and ""b"" for equality, and store the results in ""dst"".
    
    __m256i _mm256_cmpeq_epi32 (__m256i a, __m256i b)
    VPCMPEQD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpeq_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 64-bit integers in ""a"" and ""b"" for equality, and store the results in ""dst"".
    
    __m256i _mm256_cmpeq_epi64 (__m256i a, __m256i b)
    VPCMPEQQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpeq_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 8-bit integers in ""a"" and ""b"" for equality, and store the results in ""dst"".
    
    __m256i _mm256_cmpeq_epi8 (__m256i a, __m256i b)
    VPCMPEQB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpgt_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 16-bit integers in ""a"" and ""b"" for greater-than, and store the results in ""dst"".
    
    __m256i _mm256_cmpgt_epi16 (__m256i a, __m256i b)
    VPCMPGTW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpgt_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 32-bit integers in ""a"" and ""b"" for greater-than, and store the results in ""dst"".
    
    __m256i _mm256_cmpgt_epi32 (__m256i a, __m256i b)
    VPCMPGTD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpgt_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 64-bit integers in ""a"" and ""b"" for greater-than, and store the results in ""dst"".
    
    __m256i _mm256_cmpgt_epi64 (__m256i a, __m256i b)
    VPCMPGTQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpgt_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 8-bit integers in ""a"" and ""b"" for greater-than, and store the results in ""dst"".
    
    __m256i _mm256_cmpgt_epi8 (__m256i a, __m256i b)
    VPCMPGTB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepi16_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Sign extend packed 16-bit integers in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepi16_epi32 (__m128i a)
    VPMOVSXWD ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepi16_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Sign extend packed 16-bit integers in ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepi16_epi64 (__m128i a)
    VPMOVSXWQ ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepi32_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Sign extend packed 32-bit integers in ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepi32_epi64 (__m128i a)
    VPMOVSXDQ ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepi8_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Sign extend packed 8-bit integers in ""a"" to packed 16-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepi8_epi16 (__m128i a)
    VPMOVSXBW ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepi8_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Sign extend packed 8-bit integers in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepi8_epi32 (__m128i a)
    VPMOVSXBD ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepi8_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Sign extend packed 8-bit integers in the low 8 bytes of ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepi8_epi64 (__m128i a)
    VPMOVSXBQ ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepu16_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Zero extend packed unsigned 16-bit integers in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepu16_epi32 (__m128i a)
    VPMOVZXWD ymm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepu16_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Zero extend packed unsigned 16-bit integers in ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepu16_epi64 (__m128i a)
    VPMOVZXWQ ymm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepu32_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Zero extend packed unsigned 32-bit integers in ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepu32_epi64 (__m128i a)
    VPMOVZXDQ ymm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepu8_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Zero extend packed unsigned 8-bit integers in ""a"" to packed 16-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepu8_epi16 (__m128i a)
    VPMOVZXBW ymm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepu8_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Zero extend packed unsigned 8-bit integers in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepu8_epi32 (__m128i a)
    VPMOVZXBD ymm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepu8_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Zero extend packed unsigned 8-bit integers in the low 8 byte sof ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtepu8_epi64 (__m128i a)
    VPMOVZXBQ ymm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtsi256_si32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Copy the lower 32-bit integer in ""a"" to ""dst"".
    
    int _mm256_cvtsi256_si32 (__m256i a)
    MOVD reg/m32, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_extracti128_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Extract 128 bits (composed of integer data) from ""a"", selected with ""imm8"", and store the result in ""dst"".
    
    __m128i _mm256_extracti128_si256 (__m256i a, const int imm8)
    VEXTRACTI128 xmm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_hadd_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Horizontally add adjacent pairs of 16-bit integers in ""a"" and ""b"", and pack the signed 16-bit results in ""dst"".
    
    __m256i _mm256_hadd_epi16 (__m256i a, __m256i b)
    VPHADDW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_hadd_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Horizontally add adjacent pairs of 32-bit integers in ""a"" and ""b"", and pack the signed 32-bit results in ""dst"".
    
    __m256i _mm256_hadd_epi32 (__m256i a, __m256i b)
    VPHADDD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_hadds_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Horizontally add adjacent pairs of 16-bit integers in ""a"" and ""b"" using saturation, and pack the signed 16-bit results in ""dst"".
    
    __m256i _mm256_hadds_epi16 (__m256i a, __m256i b)
    VPHADDSW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_hsub_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Horizontally subtract adjacent pairs of 16-bit integers in ""a"" and ""b"", and pack the signed 16-bit results in ""dst"".
    
    __m256i _mm256_hsub_epi16 (__m256i a, __m256i b)
    VPHSUBW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_hsub_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Horizontally subtract adjacent pairs of 32-bit integers in ""a"" and ""b"", and pack the signed 32-bit results in ""dst"".
    
    __m256i _mm256_hsub_epi32 (__m256i a, __m256i b)
    VPHSUBD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_hsubs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Horizontally subtract adjacent pairs of 16-bit integers in ""a"" and ""b"" using saturation, and pack the signed 16-bit results in ""dst"".
    
    __m256i _mm256_hsubs_epi16 (__m256i a, __m256i b)
    VPHSUBSW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_i32gather_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m256i _mm256_i32gather_epi32 (int const* base_addr, __m256i vindex, const int scale)
    VPGATHERDD ymm, vm32y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_i32gather_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m256i _mm256_i32gather_epi64 (__int64 const* base_addr, __m128i vindex, const int scale)
    VPGATHERDQ ymm, vm32y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_i32gather_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m256d _mm256_i32gather_pd (double const* base_addr, __m128i vindex, const int scale)
    VGATHERDPD ymm, vm32y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_i32gather_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m256 _mm256_i32gather_ps (float const* base_addr, __m256i vindex, const int scale)
    VGATHERDPS ymm, vm32y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_i64gather_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m128i _mm256_i64gather_epi32 (int const* base_addr, __m256i vindex, const int scale)
    VPGATHERQD xmm, vm64y, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_i64gather_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m256i _mm256_i64gather_epi64 (__int64 const* base_addr, __m256i vindex, const int scale)
    VPGATHERQQ ymm, vm64y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_i64gather_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m256d _mm256_i64gather_pd (double const* base_addr, __m256i vindex, const int scale)
    VGATHERQPD ymm, vm64y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_i64gather_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"". ""scale"" should be 1, 2, 4 or 8.
    
    __m128 _mm256_i64gather_ps (float const* base_addr, __m256i vindex, const int scale)
    VGATHERQPS xmm, vm64y, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_inserti128_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Copy ""a"" to ""dst"", then insert 128 bits (composed of integer data) from ""b"" into ""dst"" at the location specified by ""imm8"".
    
    __m256i _mm256_inserti128_si256 (__m256i a, __m128i b, const int imm8)
    VINSERTI128 ymm, ymm, xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_madd_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Multiply packed signed 16-bit integers in ""a"" and ""b"", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in ""dst"".
    
    __m256i _mm256_madd_epi16 (__m256i a, __m256i b)
    VPMADDWD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_maddubs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Vertically multiply each unsigned 8-bit integer from ""a"" with the corresponding signed 8-bit integer from ""b"", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in ""dst"".
    
    __m256i _mm256_maddubs_epi16 (__m256i a, __m256i b)
    VPMADDUBSW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mask_i32gather_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 32-bit integers from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m256i _mm256_mask_i32gather_epi32 (__m256i src, int const* base_addr, __m256i vindex, __m256i mask, const int scale)
    VPGATHERDD ymm, vm32y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mask_i32gather_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 64-bit integers from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m256i _mm256_mask_i32gather_epi64 (__m256i src, __int64 const* base_addr, __m128i vindex, __m256i mask, const int scale)
    VPGATHERDQ ymm, vm32y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mask_i32gather_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather double-precision (64-bit) floating-point elements from memory using 32-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m256d _mm256_mask_i32gather_pd (__m256d src, double const* base_addr, __m128i vindex, __m256d mask, const int scale)
    VPGATHERDPD ymm, vm32y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mask_i32gather_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather single-precision (32-bit) floating-point elements from memory using 32-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 32-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m256 _mm256_mask_i32gather_ps (__m256 src, float const* base_addr, __m256i vindex, __m256 mask, const int scale)
    VPGATHERDPS ymm, vm32y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mask_i64gather_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 32-bit integers from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m128i _mm256_mask_i64gather_epi32 (__m128i src, int const* base_addr, __m256i vindex, __m128i mask, const int scale)
    VPGATHERQD xmm, vm32y, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mask_i64gather_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather 64-bit integers from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m256i _mm256_mask_i64gather_epi64 (__m256i src, __int64 const* base_addr, __m256i vindex, __m256i mask, const int scale)
    VPGATHERQQ ymm, vm32y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mask_i64gather_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather double-precision (64-bit) floating-point elements from memory using 64-bit indices. 64-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m256d _mm256_mask_i64gather_pd (__m256d src, double const* base_addr, __m256i vindex, __m256d mask, const int scale)
    VGATHERQPD ymm, vm32y, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mask_i64gather_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Gather single-precision (32-bit) floating-point elements from memory using 64-bit indices. 32-bit elements are loaded from addresses starting at ""base_addr"" and offset by each 64-bit element in ""vindex"" (each index is scaled by the factor in ""scale""). Gathered elements are merged into ""dst"" using ""mask"" (elements are copied from ""src"" when the highest bit is not set in the corresponding element). ""scale"" should be 1, 2, 4 or 8.
    
    __m128 _mm256_mask_i64gather_ps (__m128 src, float const* base_addr, __m256i vindex, __m128 mask, const int scale)
    VGATHERQPS xmm, vm32y, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_maskload_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Load packed 32-bit integers from memory into ""dst"" using ""mask"" (elements are zeroed out when the highest bit is not set in the corresponding element).
    
    __m256i _mm256_maskload_epi32 (int const* mem_addr, __m256i mask)
    VPMASKMOVD ymm, ymm, m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_maskload_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Load packed 64-bit integers from memory into ""dst"" using ""mask"" (elements are zeroed out when the highest bit is not set in the corresponding element).
    
    __m256i _mm256_maskload_epi64 (__int64 const* mem_addr, __m256i mask)
    VPMASKMOVQ ymm, ymm, m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_maskstore_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Store packed 32-bit integers from ""a"" into memory using ""mask"" (elements are not stored when the highest bit is not set in the corresponding element).
    
    void _mm256_maskstore_epi32 (int* mem_addr, __m256i mask, __m256i a)
    VPMASKMOVD m256, ymm, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_maskstore_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Store packed 64-bit integers from ""a"" into memory using ""mask"" (elements are not stored when the highest bit is not set in the corresponding element).
    
    void _mm256_maskstore_epi64 (__int64* mem_addr, __m256i mask, __m256i a)
    VPMASKMOVQ m256, ymm, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_max_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 16-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m256i _mm256_max_epi16 (__m256i a, __m256i b)
    VPMAXSW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_max_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 32-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m256i _mm256_max_epi32 (__m256i a, __m256i b)
    VPMAXSD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_max_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 8-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m256i _mm256_max_epi8 (__m256i a, __m256i b)
    VPMAXSB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_max_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed unsigned 16-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m256i _mm256_max_epu16 (__m256i a, __m256i b)
    VPMAXUW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_max_epu32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed unsigned 32-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m256i _mm256_max_epu32 (__m256i a, __m256i b)
    VPMAXUD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_max_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed unsigned 8-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m256i _mm256_max_epu8 (__m256i a, __m256i b)
    VPMAXUB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_min_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 16-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m256i _mm256_min_epi16 (__m256i a, __m256i b)
    VPMINSW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_min_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 32-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m256i _mm256_min_epi32 (__m256i a, __m256i b)
    VPMINSD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_min_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed 8-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m256i _mm256_min_epi8 (__m256i a, __m256i b)
    VPMINSB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_min_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed unsigned 16-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m256i _mm256_min_epu16 (__m256i a, __m256i b)
    VPMINUW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_min_epu32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed unsigned 32-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m256i _mm256_min_epu32 (__m256i a, __m256i b)
    VPMINUD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_min_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compare packed unsigned 8-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m256i _mm256_min_epu8 (__m256i a, __m256i b)
    VPMINUB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_movemask_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Create mask from the most significant bit of each 8-bit element in ""a"", and store the result in ""dst"".
    
    int _mm256_movemask_epi8 (__m256i a)
    VPMOVMSKB reg, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mpsadbw_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in ""a"" compared to those in ""b"", and store the 16-bit results in ""dst"".
    	Eight SADs are performed for each 128-bit lane using one quadruplet from ""b"" and eight quadruplets from ""a"". One quadruplet is selected from ""b"" starting at on the offset specified in ""imm8"". Eight quadruplets are formed from sequential 8-bit integers selected from ""a"" starting at the offset specified in ""imm8"".
    
    __m256i _mm256_mpsadbw_epu8 (__m256i a, __m256i b, const int imm8)
    VMPSADBW ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mul_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Multiply the low 32-bit integers from each packed 64-bit element in ""a"" and ""b"", and store the signed 64-bit results in ""dst"".
    
    __m256i _mm256_mul_epi32 (__m256i a, __m256i b)
    VPMULDQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mul_epu32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Multiply the low unsigned 32-bit integers from each packed 64-bit element in ""a"" and ""b"", and store the unsigned 64-bit results in ""dst"".
    
    __m256i _mm256_mul_epu32 (__m256i a, __m256i b)
    VPMULUDQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mulhi_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Multiply the packed 16-bit integers in ""a"" and ""b"", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in ""dst"".
    
    __m256i _mm256_mulhi_epi16 (__m256i a, __m256i b)
    VPMULHW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mulhi_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Multiply the packed unsigned 16-bit integers in ""a"" and ""b"", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in ""dst"".
    
    __m256i _mm256_mulhi_epu16 (__m256i a, __m256i b)
    VPMULHUW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mulhrs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Multiply packed 16-bit integers in ""a"" and ""b"", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to ""dst"".
    
    __m256i _mm256_mulhrs_epi16 (__m256i a, __m256i b)
    VPMULHRSW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mullo_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Multiply the packed 16-bit integers in ""a"" and ""b"", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in ""dst"".
    
    __m256i _mm256_mullo_epi16 (__m256i a, __m256i b)
    VPMULLW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mullo_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Multiply the packed 32-bit integers in ""a"" and ""b"", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in ""dst"".
    
    __m256i _mm256_mullo_epi32 (__m256i a, __m256i b)
    VPMULLD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_or_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compute the bitwise OR of 256 bits (representing integer data) in ""a"" and ""b"", and store the result in ""dst"".
    
    __m256i _mm256_or_si256 (__m256i a, __m256i b)
    VPOR ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_packs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Convert packed 16-bit integers from ""a"" and ""b"" to packed 8-bit integers using signed saturation, and store the results in ""dst"".
    
    __m256i _mm256_packs_epi16 (__m256i a, __m256i b)
    VPACKSSWB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_packs_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Convert packed 32-bit integers from ""a"" and ""b"" to packed 16-bit integers using signed saturation, and store the results in ""dst"".
    
    __m256i _mm256_packs_epi32 (__m256i a, __m256i b)
    VPACKSSDW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_packus_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Convert packed 16-bit integers from ""a"" and ""b"" to packed 8-bit integers using unsigned saturation, and store the results in ""dst"".
    
    __m256i _mm256_packus_epi16 (__m256i a, __m256i b)
    VPACKUSWB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_packus_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Convert packed 32-bit integers from ""a"" and ""b"" to packed 16-bit integers using unsigned saturation, and store the results in ""dst"".
    
    __m256i _mm256_packus_epi32 (__m256i a, __m256i b)
    VPACKUSDW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permute2x128_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shuffle 128-bits (composed of integer data) selected by ""imm8"" from ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_permute2x128_si256 (__m256i a, __m256i b, const int imm8)
    VPERM2I128 ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permute4x64_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shuffle 64-bit integers in ""a"" across lanes using the control in ""imm8"", and store the results in ""dst"".
    
    __m256i _mm256_permute4x64_epi64 (__m256i a, const int imm8)
    VPERMQ ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permute4x64_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shuffle double-precision (64-bit) floating-point elements in ""a"" across lanes using the control in ""imm8"", and store the results in ""dst"".
    
    __m256d _mm256_permute4x64_pd (__m256d a, const int imm8)
    VPERMPD ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permutevar8x32_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shuffle 32-bit integers in ""a"" across lanes using the corresponding index in ""idx"", and store the results in ""dst"".
    
    __m256i _mm256_permutevar8x32_epi32 (__m256i a, __m256i idx)
    VPERMD ymm, ymm/m256, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permutevar8x32_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shuffle single-precision (32-bit) floating-point elements in ""a"" across lanes using the corresponding index in ""idx"".
    
    __m256 _mm256_permutevar8x32_ps (__m256 a, __m256i idx)
    VPERMPS ymm, ymm/m256, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sad_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compute the absolute differences of packed unsigned 8-bit integers in ""a"" and ""b"", then horizontally sum each consecutive 8 differences to produce four unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in ""dst"".
    
    __m256i _mm256_sad_epu8 (__m256i a, __m256i b)
    VPSADBW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_shuffle_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shuffle 32-bit integers in ""a"" within 128-bit lanes using the control in ""imm8"", and store the results in ""dst"".
    
    __m256i _mm256_shuffle_epi32 (__m256i a, const int imm8)
    VPSHUFD ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_shuffle_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shuffle 8-bit integers in ""a"" within 128-bit lanes according to shuffle control mask in the corresponding 8-bit element of ""b"", and store the results in ""dst"".
    
    __m256i _mm256_shuffle_epi8 (__m256i a, __m256i b)
    VPSHUFB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_shufflehi_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shuffle 16-bit integers in the high 64 bits of 128-bit lanes of ""a"" using the control in ""imm8"". Store the results in the high 64 bits of 128-bit lanes of ""dst"", with the low 64 bits of 128-bit lanes being copied from from ""a"" to ""dst"".
    
    __m256i _mm256_shufflehi_epi16 (__m256i a, const int imm8)
    VPSHUFHW ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_shufflelo_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shuffle 16-bit integers in the low 64 bits of 128-bit lanes of ""a"" using the control in ""imm8"". Store the results in the low 64 bits of 128-bit lanes of ""dst"", with the high 64 bits of 128-bit lanes being copied from from ""a"" to ""dst"".
    
    __m256i _mm256_shufflelo_epi16 (__m256i a, const int imm8)
    VPSHUFLW ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sign_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Negate packed 16-bit integers in ""a"" when the corresponding signed 16-bit integer in ""b"" is negative, and store the results in ""dst"". Element in ""dst"" are zeroed out when the corresponding element in ""b"" is zero.
    
    __m256i _mm256_sign_epi16 (__m256i a, __m256i b)
    VPSIGNW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sign_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Negate packed 32-bit integers in ""a"" when the corresponding signed 32-bit integer in ""b"" is negative, and store the results in ""dst"". Element in ""dst"" are zeroed out when the corresponding element in ""b"" is zero.
    
    __m256i _mm256_sign_epi32 (__m256i a, __m256i b)
    VPSIGND ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sign_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Negate packed 8-bit integers in ""a"" when the corresponding signed 8-bit integer in ""b"" is negative, and store the results in ""dst"". Element in ""dst"" are zeroed out when the corresponding element in ""b"" is zero.
    
    __m256i _mm256_sign_epi8 (__m256i a, __m256i b)
    VPSIGNB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sll_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 16-bit integers in ""a"" left by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_sll_epi16 (__m256i a, __m128i count)
    VPSLLW ymm, ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sll_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" left by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_sll_epi32 (__m256i a, __m128i count)
    VPSLLD ymm, ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sll_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" left by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_sll_epi64 (__m256i a, __m128i count)
    VPSLLQ ymm, ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_slli_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 16-bit integers in ""a"" left by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_slli_epi16 (__m256i a, int imm8)
    VPSLLW ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_slli_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" left by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_slli_epi32 (__m256i a, int imm8)
    VPSLLD ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_slli_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" left by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_slli_epi64 (__m256i a, int imm8)
    VPSLLQ ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sllv_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" left by the amount specified by the corresponding element in ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_sllv_epi32 (__m256i a, __m256i count)
    VPSLLVD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sllv_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" left by the amount specified by the corresponding element in ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_sllv_epi64 (__m256i a, __m256i count)
    VPSLLVQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_srai_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 16-bit integers in ""a"" right by ""imm8"" while shifting in sign bits, and store the results in ""dst"".
    
    __m256i _mm256_srai_epi16 (__m256i a, int imm8)
    VPSRAW ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_srai_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" right by ""imm8"" while shifting in sign bits, and store the results in ""dst"".
    
    __m256i _mm256_srai_epi32 (__m256i a, int imm8)
    VPSRAD ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_srav_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" right by the amount specified by the corresponding element in ""count"" while shifting in sign bits, and store the results in ""dst"".
    
    __m256i _mm256_srav_epi32 (__m256i a, __m256i count)
    VPSRAVD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_srl_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 16-bit integers in ""a"" right by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_srl_epi16 (__m256i a, __m128i count)
    VPSRLW ymm, ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_srl_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" right by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_srl_epi32 (__m256i a, __m128i count)
    VPSRLD ymm, ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_srl_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" right by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_srl_epi64 (__m256i a, __m128i count)
    VPSRLQ ymm, ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_srli_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 16-bit integers in ""a"" right by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_srli_epi16 (__m256i a, int imm8)
    VPSRLW ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_srli_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" right by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_srli_epi32 (__m256i a, int imm8)
    VPSRLD ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_srli_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" right by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_srli_epi64 (__m256i a, int imm8)
    VPSRLQ ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_srlv_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" right by the amount specified by the corresponding element in ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_srlv_epi32 (__m256i a, __m256i count)
    VPSRLVD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_srlv_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" right by the amount specified by the corresponding element in ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m256i _mm256_srlv_epi64 (__m256i a, __m256i count)
    VPSRLVQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_stream_load_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Load 256-bits of integer data from memory into ""dst"" using a non-temporal memory hint.
    	""mem_addr"" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
    
    __m256i _mm256_stream_load_si256 (__m256i const* mem_addr)
    VMOVNTDQA ymm, m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sub_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Subtract packed 16-bit integers in ""b"" from packed 16-bit integers in ""a"", and store the results in ""dst"".
    
    __m256i _mm256_sub_epi16 (__m256i a, __m256i b)
    VPSUBW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sub_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Subtract packed 32-bit integers in ""b"" from packed 32-bit integers in ""a"", and store the results in ""dst"".
    
    __m256i _mm256_sub_epi32 (__m256i a, __m256i b)
    VPSUBD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sub_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Subtract packed 64-bit integers in ""b"" from packed 64-bit integers in ""a"", and store the results in ""dst"".
    
    __m256i _mm256_sub_epi64 (__m256i a, __m256i b)
    VPSUBQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sub_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Subtract packed 8-bit integers in ""b"" from packed 8-bit integers in ""a"", and store the results in ""dst"".
    
    __m256i _mm256_sub_epi8 (__m256i a, __m256i b)
    VPSUBB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_subs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Subtract packed 16-bit integers in ""b"" from packed 16-bit integers in ""a"" using saturation, and store the results in ""dst"".
    
    __m256i _mm256_subs_epi16 (__m256i a, __m256i b)
    VPSUBSW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_subs_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Subtract packed 8-bit integers in ""b"" from packed 8-bit integers in ""a"" using saturation, and store the results in ""dst"".
    
    __m256i _mm256_subs_epi8 (__m256i a, __m256i b)
    VPSUBSB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_subs_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Subtract packed unsigned 16-bit integers in ""b"" from packed unsigned 16-bit integers in ""a"" using saturation, and store the results in ""dst"".
    
    __m256i _mm256_subs_epu16 (__m256i a, __m256i b)
    VPSUBUSW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_subs_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Subtract packed unsigned 8-bit integers in ""b"" from packed unsigned 8-bit integers in ""a"" using saturation, and store the results in ""dst"".
    
    __m256i _mm256_subs_epu8 (__m256i a, __m256i b)
    VPSUBUSB ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpackhi_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Unpack and interleave 16-bit integers from the high half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_unpackhi_epi16 (__m256i a, __m256i b)
    VPUNPCKHWD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpackhi_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Unpack and interleave 32-bit integers from the high half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_unpackhi_epi32 (__m256i a, __m256i b)
    VPUNPCKHDQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpackhi_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Unpack and interleave 64-bit integers from the high half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_unpackhi_epi64 (__m256i a, __m256i b)
    VPUNPCKHQDQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpackhi_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Unpack and interleave 8-bit integers from the high half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_unpackhi_epi8 (__m256i a, __m256i b)
    VPUNPCKHBW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpacklo_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Unpack and interleave 16-bit integers from the low half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_unpacklo_epi16 (__m256i a, __m256i b)
    VPUNPCKLWD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpacklo_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Unpack and interleave 32-bit integers from the low half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_unpacklo_epi32 (__m256i a, __m256i b)
    VPUNPCKLDQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpacklo_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Unpack and interleave 64-bit integers from the low half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_unpacklo_epi64 (__m256i a, __m256i b)
    VPUNPCKLQDQ ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpacklo_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Unpack and interleave 8-bit integers from the low half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_unpacklo_epi8 (__m256i a, __m256i b)
    VPUNPCKLBW ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_xor_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX2";
                descriptor.Description = @"Compute the bitwise XOR of 256 bits (representing integer data) in ""a"" and ""b"", and store the result in ""dst"".
    
    __m256i _mm256_xor_si256 (__m256i a, __m256i b)
    VPXOR ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class AvxIntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_broadcast_ss", (Func<object, object>)mm_broadcast_ss);
            RegisterFunction("mm_cmp_pd", (Func<object, object, System.Runtime.Intrinsics.X86.FloatComparisonMode, object>)mm_cmp_pd);
            RegisterFunction("mm_cmp_ps", (Func<object, object, System.Runtime.Intrinsics.X86.FloatComparisonMode, object>)mm_cmp_ps);
            RegisterFunction("mm_cmp_sd", (Func<object, object, System.Runtime.Intrinsics.X86.FloatComparisonMode, object>)mm_cmp_sd);
            RegisterFunction("mm_cmp_ss", (Func<object, object, System.Runtime.Intrinsics.X86.FloatComparisonMode, object>)mm_cmp_ss);
            RegisterFunction("mm_maskload_pd", (Func<object, object, object>)mm_maskload_pd);
            RegisterFunction("mm_maskload_ps", (Func<object, object, object>)mm_maskload_ps);
            RegisterAction("mm_maskstore_pd", (Action<object, object, object>)mm_maskstore_pd);
            RegisterAction("mm_maskstore_ps", (Action<object, object, object>)mm_maskstore_ps);
            RegisterFunction("mm_permute_pd", (Func<object, byte, object>)mm_permute_pd);
            RegisterFunction("mm_permute_ps", (Func<object, byte, object>)mm_permute_ps);
            RegisterFunction("mm_permutevar_pd", (Func<object, object, object>)mm_permutevar_pd);
            RegisterFunction("mm_permutevar_ps", (Func<object, object, object>)mm_permutevar_ps);
            RegisterFunction("mm_testc_pd", (Func<object, object, Kalk.Core.KalkBool>)mm_testc_pd);
            RegisterFunction("mm_testc_ps", (Func<object, object, Kalk.Core.KalkBool>)mm_testc_ps);
            RegisterFunction("mm_testnzc_pd", (Func<object, object, Kalk.Core.KalkBool>)mm_testnzc_pd);
            RegisterFunction("mm_testnzc_ps", (Func<object, object, Kalk.Core.KalkBool>)mm_testnzc_ps);
            RegisterFunction("mm_testz_pd", (Func<object, object, Kalk.Core.KalkBool>)mm_testz_pd);
            RegisterFunction("mm_testz_ps", (Func<object, object, Kalk.Core.KalkBool>)mm_testz_ps);
            RegisterFunction("mm256_add_pd", (Func<object, object, object>)mm256_add_pd);
            RegisterFunction("mm256_add_ps", (Func<object, object, object>)mm256_add_ps);
            RegisterFunction("mm256_addsub_pd", (Func<object, object, object>)mm256_addsub_pd);
            RegisterFunction("mm256_addsub_ps", (Func<object, object, object>)mm256_addsub_ps);
            RegisterFunction("mm256_and_pd", (Func<object, object, object>)mm256_and_pd);
            RegisterFunction("mm256_and_ps", (Func<object, object, object>)mm256_and_ps);
            RegisterFunction("mm256_andnot_pd", (Func<object, object, object>)mm256_andnot_pd);
            RegisterFunction("mm256_andnot_ps", (Func<object, object, object>)mm256_andnot_ps);
            RegisterFunction("mm256_blend_pd", (Func<object, object, byte, object>)mm256_blend_pd);
            RegisterFunction("mm256_blend_ps", (Func<object, object, byte, object>)mm256_blend_ps);
            RegisterFunction("mm256_blendv_pd", (Func<object, object, object, object>)mm256_blendv_pd);
            RegisterFunction("mm256_blendv_ps", (Func<object, object, object, object>)mm256_blendv_ps);
            RegisterFunction("mm256_broadcast_pd", (Func<object, object>)mm256_broadcast_pd);
            RegisterFunction("mm256_broadcast_ps", (Func<object, object>)mm256_broadcast_ps);
            RegisterFunction("mm256_broadcast_sd", (Func<object, object>)mm256_broadcast_sd);
            RegisterFunction("mm256_broadcast_ss", (Func<object, object>)mm256_broadcast_ss);
            RegisterFunction("mm256_ceil_pd", (Func<object, object>)mm256_ceil_pd);
            RegisterFunction("mm256_ceil_ps", (Func<object, object>)mm256_ceil_ps);
            RegisterFunction("mm256_cmp_pd", (Func<object, object, System.Runtime.Intrinsics.X86.FloatComparisonMode, object>)mm256_cmp_pd);
            RegisterFunction("mm256_cmp_ps", (Func<object, object, System.Runtime.Intrinsics.X86.FloatComparisonMode, object>)mm256_cmp_ps);
            RegisterFunction("mm256_cmpeq_pd", (Func<object, object, object>)mm256_cmpeq_pd);
            RegisterFunction("mm256_cmpeq_ps", (Func<object, object, object>)mm256_cmpeq_ps);
            RegisterFunction("mm256_cmpge_pd", (Func<object, object, object>)mm256_cmpge_pd);
            RegisterFunction("mm256_cmpge_ps", (Func<object, object, object>)mm256_cmpge_ps);
            RegisterFunction("mm256_cmpgt_pd", (Func<object, object, object>)mm256_cmpgt_pd);
            RegisterFunction("mm256_cmpgt_ps", (Func<object, object, object>)mm256_cmpgt_ps);
            RegisterFunction("mm256_cmple_pd", (Func<object, object, object>)mm256_cmple_pd);
            RegisterFunction("mm256_cmple_ps", (Func<object, object, object>)mm256_cmple_ps);
            RegisterFunction("mm256_cmplt_pd", (Func<object, object, object>)mm256_cmplt_pd);
            RegisterFunction("mm256_cmplt_ps", (Func<object, object, object>)mm256_cmplt_ps);
            RegisterFunction("mm256_cmpneq_pd", (Func<object, object, object>)mm256_cmpneq_pd);
            RegisterFunction("mm256_cmpneq_ps", (Func<object, object, object>)mm256_cmpneq_ps);
            RegisterFunction("mm256_cmpnge_pd", (Func<object, object, object>)mm256_cmpnge_pd);
            RegisterFunction("mm256_cmpnge_ps", (Func<object, object, object>)mm256_cmpnge_ps);
            RegisterFunction("mm256_cmpngt_pd", (Func<object, object, object>)mm256_cmpngt_pd);
            RegisterFunction("mm256_cmpngt_ps", (Func<object, object, object>)mm256_cmpngt_ps);
            RegisterFunction("mm256_cmpnle_pd", (Func<object, object, object>)mm256_cmpnle_pd);
            RegisterFunction("mm256_cmpnle_ps", (Func<object, object, object>)mm256_cmpnle_ps);
            RegisterFunction("mm256_cmpnlt_pd", (Func<object, object, object>)mm256_cmpnlt_pd);
            RegisterFunction("mm256_cmpnlt_ps", (Func<object, object, object>)mm256_cmpnlt_ps);
            RegisterFunction("mm256_cmpord_pd", (Func<object, object, object>)mm256_cmpord_pd);
            RegisterFunction("mm256_cmpord_ps", (Func<object, object, object>)mm256_cmpord_ps);
            RegisterFunction("mm256_cmpunord_pd", (Func<object, object, object>)mm256_cmpunord_pd);
            RegisterFunction("mm256_cmpunord_ps", (Func<object, object, object>)mm256_cmpunord_ps);
            RegisterFunction("mm256_cvtepi32_pd", (Func<object, object>)mm256_cvtepi32_pd);
            RegisterFunction("mm256_cvtepi32_ps", (Func<object, object>)mm256_cvtepi32_ps);
            RegisterFunction("mm256_cvtpd_epi32", (Func<object, object>)mm256_cvtpd_epi32);
            RegisterFunction("mm256_cvtpd_ps", (Func<object, object>)mm256_cvtpd_ps);
            RegisterFunction("mm256_cvtps_epi32", (Func<object, object>)mm256_cvtps_epi32);
            RegisterFunction("mm256_cvtps_pd", (Func<object, object>)mm256_cvtps_pd);
            RegisterFunction("mm256_cvttpd_epi32", (Func<object, object>)mm256_cvttpd_epi32);
            RegisterFunction("mm256_cvttps_epi32", (Func<object, object>)mm256_cvttps_epi32);
            RegisterFunction("mm256_div_pd", (Func<object, object, object>)mm256_div_pd);
            RegisterFunction("mm256_div_ps", (Func<object, object, object>)mm256_div_ps);
            RegisterFunction("mm256_dp_ps", (Func<object, object, byte, object>)mm256_dp_ps);
            RegisterFunction("mm256_extractf128_pd", (Func<object, byte, object>)mm256_extractf128_pd);
            RegisterFunction("mm256_extractf128_ps", (Func<object, byte, object>)mm256_extractf128_ps);
            RegisterFunction("mm256_extractf128_si256", (Func<object, byte, object>)mm256_extractf128_si256);
            RegisterFunction("mm256_floor_pd", (Func<object, object>)mm256_floor_pd);
            RegisterFunction("mm256_floor_ps", (Func<object, object>)mm256_floor_ps);
            RegisterFunction("mm256_hadd_pd", (Func<object, object, object>)mm256_hadd_pd);
            RegisterFunction("mm256_hadd_ps", (Func<object, object, object>)mm256_hadd_ps);
            RegisterFunction("mm256_hsub_pd", (Func<object, object, object>)mm256_hsub_pd);
            RegisterFunction("mm256_hsub_ps", (Func<object, object, object>)mm256_hsub_ps);
            RegisterFunction("mm256_insertf128_pd", (Func<object, object, byte, object>)mm256_insertf128_pd);
            RegisterFunction("mm256_insertf128_ps", (Func<object, object, byte, object>)mm256_insertf128_ps);
            RegisterFunction("mm256_insertf128_si256", (Func<object, object, byte, object>)mm256_insertf128_si256);
            RegisterFunction("mm256_lddqu_si256", (Func<object, object>)mm256_lddqu_si256);
            RegisterFunction("mm256_load_pd", (Func<object, object>)mm256_load_pd);
            RegisterFunction("mm256_load_ps", (Func<object, object>)mm256_load_ps);
            RegisterFunction("mm256_load_si256", (Func<object, object>)mm256_load_si256);
            RegisterFunction("mm256_loadu_pd", (Func<object, object>)mm256_loadu_pd);
            RegisterFunction("mm256_loadu_ps", (Func<object, object>)mm256_loadu_ps);
            RegisterFunction("mm256_loadu_si256", (Func<object, object>)mm256_loadu_si256);
            RegisterFunction("mm256_maskload_pd", (Func<object, object, object>)mm256_maskload_pd);
            RegisterFunction("mm256_maskload_ps", (Func<object, object, object>)mm256_maskload_ps);
            RegisterAction("mm256_maskstore_pd", (Action<object, object, object>)mm256_maskstore_pd);
            RegisterAction("mm256_maskstore_ps", (Action<object, object, object>)mm256_maskstore_ps);
            RegisterFunction("mm256_max_pd", (Func<object, object, object>)mm256_max_pd);
            RegisterFunction("mm256_max_ps", (Func<object, object, object>)mm256_max_ps);
            RegisterFunction("mm256_min_pd", (Func<object, object, object>)mm256_min_pd);
            RegisterFunction("mm256_min_ps", (Func<object, object, object>)mm256_min_ps);
            RegisterFunction("mm256_movedup_pd", (Func<object, object>)mm256_movedup_pd);
            RegisterFunction("mm256_movehdup_ps", (Func<object, object>)mm256_movehdup_ps);
            RegisterFunction("mm256_moveldup_ps", (Func<object, object>)mm256_moveldup_ps);
            RegisterFunction("mm256_movemask_pd", (Func<object, int>)mm256_movemask_pd);
            RegisterFunction("mm256_movemask_ps", (Func<object, int>)mm256_movemask_ps);
            RegisterFunction("mm256_mul_pd", (Func<object, object, object>)mm256_mul_pd);
            RegisterFunction("mm256_mul_ps", (Func<object, object, object>)mm256_mul_ps);
            RegisterFunction("mm256_or_pd", (Func<object, object, object>)mm256_or_pd);
            RegisterFunction("mm256_or_ps", (Func<object, object, object>)mm256_or_ps);
            RegisterFunction("mm256_permute_pd", (Func<object, byte, object>)mm256_permute_pd);
            RegisterFunction("mm256_permute_ps", (Func<object, byte, object>)mm256_permute_ps);
            RegisterFunction("mm256_permute2f128_pd", (Func<object, object, byte, object>)mm256_permute2f128_pd);
            RegisterFunction("mm256_permute2f128_ps", (Func<object, object, byte, object>)mm256_permute2f128_ps);
            RegisterFunction("mm256_permute2f128_si256", (Func<object, object, byte, object>)mm256_permute2f128_si256);
            RegisterFunction("mm256_permutevar_pd", (Func<object, object, object>)mm256_permutevar_pd);
            RegisterFunction("mm256_permutevar_ps", (Func<object, object, object>)mm256_permutevar_ps);
            RegisterFunction("mm256_rcp_ps", (Func<object, object>)mm256_rcp_ps);
            RegisterFunction("mm256_round_pd1", (Func<object, object>)mm256_round_pd1);
            RegisterFunction("mm256_round_pd1_to_nearest_integer", (Func<object, object>)mm256_round_pd1_to_nearest_integer);
            RegisterFunction("mm256_round_pd1_to_negative_infinity", (Func<object, object>)mm256_round_pd1_to_negative_infinity);
            RegisterFunction("mm256_round_pd1_to_positive_infinity", (Func<object, object>)mm256_round_pd1_to_positive_infinity);
            RegisterFunction("mm256_round_pd1_to_zero", (Func<object, object>)mm256_round_pd1_to_zero);
            RegisterFunction("mm256_round_ps", (Func<object, object>)mm256_round_ps);
            RegisterFunction("mm256_round_ps_to_nearest_integer", (Func<object, object>)mm256_round_ps_to_nearest_integer);
            RegisterFunction("mm256_round_ps_to_negative_infinity", (Func<object, object>)mm256_round_ps_to_negative_infinity);
            RegisterFunction("mm256_round_ps_to_positive_infinity", (Func<object, object>)mm256_round_ps_to_positive_infinity);
            RegisterFunction("mm256_round_ps_to_zero", (Func<object, object>)mm256_round_ps_to_zero);
            RegisterFunction("mm256_rsqrt_ps", (Func<object, object>)mm256_rsqrt_ps);
            RegisterFunction("mm256_shuffle_pd", (Func<object, object, byte, object>)mm256_shuffle_pd);
            RegisterFunction("mm256_shuffle_ps", (Func<object, object, byte, object>)mm256_shuffle_ps);
            RegisterFunction("mm256_sqrt_pd", (Func<object, object>)mm256_sqrt_pd);
            RegisterFunction("mm256_sqrt_ps", (Func<object, object>)mm256_sqrt_ps);
            RegisterAction("mm256_store_pd", (Action<object, object>)mm256_store_pd);
            RegisterAction("mm256_store_ps", (Action<object, object>)mm256_store_ps);
            RegisterAction("mm256_store_si256", (Action<object, object>)mm256_store_si256);
            RegisterAction("mm256_storeu_pd", (Action<object, object>)mm256_storeu_pd);
            RegisterAction("mm256_storeu_ps", (Action<object, object>)mm256_storeu_ps);
            RegisterAction("mm256_storeu_si256", (Action<object, object>)mm256_storeu_si256);
            RegisterAction("mm256_stream_pd", (Action<object, object>)mm256_stream_pd);
            RegisterAction("mm256_stream_ps", (Action<object, object>)mm256_stream_ps);
            RegisterAction("mm256_stream_si256", (Action<object, object>)mm256_stream_si256);
            RegisterFunction("mm256_sub_pd", (Func<object, object, object>)mm256_sub_pd);
            RegisterFunction("mm256_sub_ps", (Func<object, object, object>)mm256_sub_ps);
            RegisterFunction("mm256_testc_pd", (Func<object, object, Kalk.Core.KalkBool>)mm256_testc_pd);
            RegisterFunction("mm256_testc_ps", (Func<object, object, Kalk.Core.KalkBool>)mm256_testc_ps);
            RegisterFunction("mm256_testc_si256", (Func<object, object, Kalk.Core.KalkBool>)mm256_testc_si256);
            RegisterFunction("mm256_testnzc_pd", (Func<object, object, Kalk.Core.KalkBool>)mm256_testnzc_pd);
            RegisterFunction("mm256_testnzc_ps", (Func<object, object, Kalk.Core.KalkBool>)mm256_testnzc_ps);
            RegisterFunction("mm256_testnzc_si256", (Func<object, object, Kalk.Core.KalkBool>)mm256_testnzc_si256);
            RegisterFunction("mm256_testz_pd", (Func<object, object, Kalk.Core.KalkBool>)mm256_testz_pd);
            RegisterFunction("mm256_testz_ps", (Func<object, object, Kalk.Core.KalkBool>)mm256_testz_ps);
            RegisterFunction("mm256_testz_si256", (Func<object, object, Kalk.Core.KalkBool>)mm256_testz_si256);
            RegisterFunction("mm256_unpackhi_pd", (Func<object, object, object>)mm256_unpackhi_pd);
            RegisterFunction("mm256_unpackhi_ps", (Func<object, object, object>)mm256_unpackhi_ps);
            RegisterFunction("mm256_unpacklo_pd", (Func<object, object, object>)mm256_unpacklo_pd);
            RegisterFunction("mm256_unpacklo_ps", (Func<object, object, object>)mm256_unpacklo_ps);
            RegisterFunction("mm256_xor_pd", (Func<object, object, object>)mm256_xor_pd);
            RegisterFunction("mm256_xor_ps", (Func<object, object, object>)mm256_xor_ps);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_broadcast_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Broadcast a single-precision (32-bit) floating-point element from memory to all elements of ""dst"".
    
    __m128 _mm_broadcast_ss (float const * mem_addr)
    VBROADCASTSS xmm, m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmp_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" based on the comparison operand specified by ""imm8"", and store the results in ""dst"".
    
    __m128d _mm_cmp_pd (__m128d a, __m128d b, const int imm8)
    VCMPPD xmm, xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmp_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" based on the comparison operand specified by ""imm8"", and store the results in ""dst"".
    
    __m128 _mm_cmp_ps (__m128 a, __m128 b, const int imm8)
    VCMPPS xmm, xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmp_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" based on the comparison operand specified by ""imm8"", store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmp_sd (__m128d a, __m128d b, const int imm8)
    VCMPSS xmm, xmm, xmm/m32, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmp_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" based on the comparison operand specified by ""imm8"", store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmp_ss (__m128 a, __m128 b, const int imm8)
    VCMPSD xmm, xmm, xmm/m64, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_maskload_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Load packed double-precision (64-bit) floating-point elements from memory into ""dst"" using ""mask"" (elements are zeroed out when the high bit of the corresponding element is not set).
    
    __m128d _mm_maskload_pd (double const * mem_addr, __m128i mask)
    VMASKMOVPD xmm, xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_maskload_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Load packed single-precision (32-bit) floating-point elements from memory into ""dst"" using ""mask"" (elements are zeroed out when the high bit of the corresponding element is not set).
    
    __m128 _mm_maskload_ps (float const * mem_addr, __m128i mask)
    VMASKMOVPS xmm, xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_maskstore_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store packed double-precision (64-bit) floating-point elements from ""a"" into memory using ""mask"".
    
    void _mm_maskstore_pd (double * mem_addr, __m128i mask, __m128d a)
    VMASKMOVPD m128, xmm, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_maskstore_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store packed single-precision (32-bit) floating-point elements from ""a"" into memory using ""mask"".
    
    void _mm_maskstore_ps (float * mem_addr, __m128i mask, __m128 a)
    VMASKMOVPS m128, xmm, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_permute_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle double-precision (64-bit) floating-point elements in ""a"" using the control in ""imm8"", and store the results in ""dst"".
    
    __m128d _mm_permute_pd (__m128d a, int imm8)
    VPERMILPD xmm, xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_permute_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle single-precision (32-bit) floating-point elements in ""a"" using the control in ""imm8"", and store the results in ""dst"".
    
    __m128 _mm_permute_ps (__m128 a, int imm8)
    VPERMILPS xmm, xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_permutevar_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle double-precision (64-bit) floating-point elements in ""a"" using the control in ""b"", and store the results in ""dst"".
    
    __m128d _mm_permutevar_pd (__m128d a, __m128i b)
    VPERMILPD xmm, xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_permutevar_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle single-precision (32-bit) floating-point elements in ""a"" using the control in ""b"", and store the results in ""dst"".
    
    __m128 _mm_permutevar_ps (__m128 a, __m128i b)
    VPERMILPS xmm, xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_testc_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 128-bit value, and set ""ZF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return the ""CF"" value.
    
    int _mm_testc_pd (__m128d a, __m128d b)
    VTESTPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_testc_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 128-bit value, and set ""ZF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return the ""CF"" value.
    
    int _mm_testc_ps (__m128 a, __m128 b)
    VTESTPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_testnzc_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 128-bit value, and set ""ZF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return 1 if both the ""ZF"" and ""CF"" values are zero, otherwise return 0.
    
    int _mm_testnzc_pd (__m128d a, __m128d b)
    VTESTPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_testnzc_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 128-bit value, and set ""ZF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return 1 if both the ""ZF"" and ""CF"" values are zero, otherwise return 0.
    
    int _mm_testnzc_ps (__m128 a, __m128 b)
    VTESTPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_testz_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 128 bits (representing double-precision (64-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 128-bit value, and set ""ZF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return the ""ZF"" value.
    
    int _mm_testz_pd (__m128d a, __m128d b)
    VTESTPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_testz_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 128 bits (representing single-precision (32-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 128-bit value, and set ""ZF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return the ""ZF"" value.
    
    int _mm_testz_ps (__m128 a, __m128 b)
    VTESTPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_add_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Add packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256d _mm256_add_pd (__m256d a, __m256d b)
    VADDPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_add_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Add packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256 _mm256_add_ps (__m256 a, __m256 b)
    VADDPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_addsub_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Alternatively add and subtract packed double-precision (64-bit) floating-point elements in ""a"" to/from packed elements in ""b"", and store the results in ""dst"".
    
    __m256d _mm256_addsub_pd (__m256d a, __m256d b)
    VADDSUBPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_addsub_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Alternatively add and subtract packed single-precision (32-bit) floating-point elements in ""a"" to/from packed elements in ""b"", and store the results in ""dst"".
    
    __m256 _mm256_addsub_ps (__m256 a, __m256 b)
    VADDSUBPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_and_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256d _mm256_and_pd (__m256d a, __m256d b)
    VANDPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_and_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256 _mm256_and_ps (__m256 a, __m256 b)
    VANDPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_andnot_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in ""a"" and then AND with ""b"", and store the results in ""dst"".
    
    __m256d _mm256_andnot_pd (__m256d a, __m256d b)
    VANDNPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_andnot_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in ""a"" and then AND with ""b"", and store the results in ""dst"".
    
    __m256 _mm256_andnot_ps (__m256 a, __m256 b)
    VANDNPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_blend_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Blend packed double-precision (64-bit) floating-point elements from ""a"" and ""b"" using control mask ""imm8"", and store the results in ""dst"".
    
    __m256d _mm256_blend_pd (__m256d a, __m256d b, const int imm8)
    VBLENDPD ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_blend_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Blend packed single-precision (32-bit) floating-point elements from ""a"" and ""b"" using control mask ""imm8"", and store the results in ""dst"".
    
    __m256 _mm256_blend_ps (__m256 a, __m256 b, const int imm8)
    VBLENDPS ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_blendv_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Blend packed double-precision (64-bit) floating-point elements from ""a"" and ""b"" using ""mask"", and store the results in ""dst"".
    
    __m256d _mm256_blendv_pd (__m256d a, __m256d b, __m256d mask)
    VBLENDVPD ymm, ymm, ymm/m256, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_blendv_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Blend packed single-precision (32-bit) floating-point elements from ""a"" and ""b"" using ""mask"", and store the results in ""dst"".
    
    __m256 _mm256_blendv_ps (__m256 a, __m256 b, __m256 mask)
    VBLENDVPS ymm, ymm, ymm/m256, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_broadcast_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Broadcast 128 bits from memory (composed of 2 packed double-precision (64-bit) floating-point elements) to all elements of ""dst"".
    
    __m256d _mm256_broadcast_pd (__m128d const * mem_addr)
    VBROADCASTF128, ymm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_broadcast_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Broadcast 128 bits from memory (composed of 4 packed single-precision (32-bit) floating-point elements) to all elements of ""dst"".
    
    __m256 _mm256_broadcast_ps (__m128 const * mem_addr)
    VBROADCASTF128, ymm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_broadcast_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Broadcast a double-precision (64-bit) floating-point element from memory to all elements of ""dst"".
    
    __m256d _mm256_broadcast_sd (double const * mem_addr)
    VBROADCASTSD ymm, m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_broadcast_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Broadcast a single-precision (32-bit) floating-point element from memory to all elements of ""dst"".
    
    __m256 _mm256_broadcast_ss (float const * mem_addr)
    VBROADCASTSS ymm, m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_ceil_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" up to an integer value, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m256d _mm256_ceil_pd (__m256d a)
    VROUNDPD ymm, ymm/m256, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_ceil_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" up to an integer value, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m256 _mm256_ceil_ps (__m256 a)
    VROUNDPS ymm, ymm/m256, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmp_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" based on the comparison operand specified by ""imm8"", and store the results in ""dst"".
    
    __m256d _mm256_cmp_pd (__m256d a, __m256d b, const int imm8)
    VCMPPD ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmp_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" based on the comparison operand specified by ""imm8"", and store the results in ""dst"".
    
    __m256 _mm256_cmp_ps (__m256 a, __m256 b, const int imm8)
    VCMPPS ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpeq_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmpeq_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(0)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpeq_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmpeq_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(0)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpge_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmpge_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(13)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpge_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmpge_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(13)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpgt_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmpgt_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(14)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpgt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmpgt_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(14)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmple_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmple_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(2)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmple_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmple_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(2)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmplt_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmplt_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(1)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmplt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmplt_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(1)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpneq_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmpneq_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(4)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpneq_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmpneq_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(4)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpnge_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmpnge_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(9)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpnge_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmpnge_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(9)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpngt_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmpngt_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(10)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpngt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmpngt_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(10)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpnle_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmpnle_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(6)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpnle_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmpnle_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(6)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpnlt_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmpnlt_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(5)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpnlt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmpnlt_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(5)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpord_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmpord_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(7)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpord_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmpord_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(7)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpunord_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256d _mm256_cmpunord_pd (__m256d a,  __m256d b) CMPPD ymm, ymm/m256, imm8(3)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cmpunord_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"__m256 _mm256_cmpunord_ps (__m256 a,  __m256 b) CMPPS ymm, ymm/m256, imm8(3)
    The above native signature does not exist. We provide this additional overload for completeness.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepi32_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Convert packed 32-bit integers in ""a"" to packed double-precision (64-bit) floating-point elements, and store the results in ""dst"".
    
    __m256d _mm256_cvtepi32_pd (__m128i a)
    VCVTDQ2PD ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtepi32_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Convert packed 32-bit integers in ""a"" to packed single-precision (32-bit) floating-point elements, and store the results in ""dst"".
    
    __m256 _mm256_cvtepi32_ps (__m256i a)
    VCVTDQ2PS ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtpd_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Convert packed double-precision (64-bit) floating-point elements in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m128i _mm256_cvtpd_epi32 (__m256d a)
    VCVTPD2DQ xmm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtpd_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Convert packed double-precision (64-bit) floating-point elements in ""a"" to packed single-precision (32-bit) floating-point elements, and store the results in ""dst"".
    
    __m128 _mm256_cvtpd_ps (__m256d a)
    VCVTPD2PS xmm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtps_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Convert packed single-precision (32-bit) floating-point elements in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m256i _mm256_cvtps_epi32 (__m256 a)
    VCVTPS2DQ ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvtps_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Convert packed single-precision (32-bit) floating-point elements in ""a"" to packed double-precision (64-bit) floating-point elements, and store the results in ""dst"".
    
    __m256d _mm256_cvtps_pd (__m128 a)
    VCVTPS2PD ymm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvttpd_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Convert packed double-precision (64-bit) floating-point elements in ""a"" to packed 32-bit integers with truncation, and store the results in ""dst"".
    
    __m128i _mm256_cvttpd_epi32 (__m256d a)
    VCVTTPD2DQ xmm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_cvttps_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Convert packed single-precision (32-bit) floating-point elements in ""a"" to packed 32-bit integers with truncation, and store the results in ""dst"".
    
    __m256i _mm256_cvttps_epi32 (__m256 a)
    VCVTTPS2DQ ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_div_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Divide packed double-precision (64-bit) floating-point elements in ""a"" by packed elements in ""b"", and store the results in ""dst"".
    
    __m256d _mm256_div_pd (__m256d a, __m256d b)
    VDIVPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_div_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Divide packed single-precision (32-bit) floating-point elements in ""a"" by packed elements in ""b"", and store the results in ""dst"".
    
    __m256 _mm256_div_ps (__m256 a, __m256 b)
    VDIVPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_dp_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Conditionally multiply the packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" using the high 4 bits in ""imm8"", sum the four products, and conditionally store the sum in ""dst"" using the low 4 bits of ""imm8"".
    
    __m256 _mm256_dp_ps (__m256 a, __m256 b, const int imm8)
    VDPPS ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_extractf128_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Extract 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from ""a"", selected with ""imm8"", and store the result in ""dst"".
    
    __m128d _mm256_extractf128_pd (__m256d a, const int imm8)
    VEXTRACTF128 xmm/m128, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_extractf128_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Extract 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from ""a"", selected with ""imm8"", and store the result in ""dst"".
    
    __m128 _mm256_extractf128_ps (__m256 a, const int imm8)
    VEXTRACTF128 xmm/m128, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_extractf128_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Extract 128 bits (composed of integer data) from ""a"", selected with ""imm8"", and store the result in ""dst"".
    
    __m128i _mm256_extractf128_si256 (__m256i a, const int imm8)
    VEXTRACTF128 xmm/m128, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_floor_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" down to an integer value, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m256d _mm256_floor_pd (__m256d a)
    VROUNDPS ymm, ymm/m256, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_floor_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" down to an integer value, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m256 _mm256_floor_ps (__m256 a)
    VROUNDPS ymm, ymm/m256, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_hadd_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Horizontally add adjacent pairs of double-precision (64-bit) floating-point elements in ""a"" and ""b"", and pack the results in ""dst"".
    
    __m256d _mm256_hadd_pd (__m256d a, __m256d b)
    VHADDPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_hadd_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in ""a"" and ""b"", and pack the results in ""dst"".
    
    __m256 _mm256_hadd_ps (__m256 a, __m256 b)
    VHADDPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_hsub_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Horizontally subtract adjacent pairs of double-precision (64-bit) floating-point elements in ""a"" and ""b"", and pack the results in ""dst"".
    
    __m256d _mm256_hsub_pd (__m256d a, __m256d b)
    VHSUBPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_hsub_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in ""a"" and ""b"", and pack the results in ""dst"".
    
    __m256 _mm256_hsub_ps (__m256 a, __m256 b)
    VHSUBPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_insertf128_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Copy ""a"" to ""dst"", then insert 128 bits (composed of 2 packed double-precision (64-bit) floating-point elements) from ""b"" into ""dst"" at the location specified by ""imm8"".
    
    __m256d _mm256_insertf128_pd (__m256d a, __m128d b, int imm8)
    VINSERTF128 ymm, ymm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_insertf128_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Copy ""a"" to ""dst"", then insert 128 bits (composed of 4 packed single-precision (32-bit) floating-point elements) from ""b"" into ""dst"" at the location specified by ""imm8"".
    
    __m256 _mm256_insertf128_ps (__m256 a, __m128 b, int imm8)
    VINSERTF128 ymm, ymm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_insertf128_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Copy ""a"" to ""dst"", then insert 128 bits from ""b"" into ""dst"" at the location specified by ""imm8"".
    
    __m256i _mm256_insertf128_si256 (__m256i a, __m128i b, int imm8)
    VINSERTF128 ymm, ymm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_lddqu_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Load 256-bits of integer data from unaligned memory into ""dst"". This intrinsic may perform better than ""_mm256_loadu_si256"" when the data crosses a cache line boundary.
    
    __m256i _mm256_lddqu_si256 (__m256i const * mem_addr)
    VLDDQU ymm, m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_load_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into ""dst"".
    	""mem_addr"" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
    
    __m256d _mm256_load_pd (double const * mem_addr)
    VMOVAPD ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_load_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into ""dst"".
    	""mem_addr"" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
    
    __m256 _mm256_load_ps (float const * mem_addr)
    VMOVAPS ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_load_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Load 256-bits of integer data from memory into ""dst"".
    	""mem_addr"" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
    
    __m256i _mm256_load_si256 (__m256i const * mem_addr)
    VMOVDQA ymm, m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_loadu_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Load 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from memory into ""dst"".
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m256d _mm256_loadu_pd (double const * mem_addr)
    VMOVUPD ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_loadu_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Load 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from memory into ""dst"".
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m256 _mm256_loadu_ps (float const * mem_addr)
    VMOVUPS ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_loadu_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Load 256-bits of integer data from memory into ""dst"".
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m256i _mm256_loadu_si256 (__m256i const * mem_addr)
    VMOVDQU ymm, m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_maskload_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Load packed double-precision (64-bit) floating-point elements from memory into ""dst"" using ""mask"" (elements are zeroed out when the high bit of the corresponding element is not set).
    
    __m256d _mm256_maskload_pd (double const * mem_addr, __m256i mask)
    VMASKMOVPD ymm, ymm, m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_maskload_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Load packed single-precision (32-bit) floating-point elements from memory into ""dst"" using ""mask"" (elements are zeroed out when the high bit of the corresponding element is not set).
    
    __m256 _mm256_maskload_ps (float const * mem_addr, __m256i mask)
    VMASKMOVPS ymm, ymm, m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_maskstore_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store packed double-precision (64-bit) floating-point elements from ""a"" into memory using ""mask"".
    
    void _mm256_maskstore_pd (double * mem_addr, __m256i mask, __m256d a)
    VMASKMOVPD m256, ymm, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_maskstore_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store packed single-precision (32-bit) floating-point elements from ""a"" into memory using ""mask"".
    
    void _mm256_maskstore_ps (float * mem_addr, __m256i mask, __m256 a)
    VMASKMOVPS m256, ymm, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_max_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m256d _mm256_max_pd (__m256d a, __m256d b)
    VMAXPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_max_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m256 _mm256_max_ps (__m256 a, __m256 b)
    VMAXPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_min_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m256d _mm256_min_pd (__m256d a, __m256d b)
    VMINPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_min_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m256 _mm256_min_ps (__m256 a, __m256 b)
    VMINPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_movedup_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Duplicate even-indexed double-precision (64-bit) floating-point elements from ""a"", and store the results in ""dst"".
    
    __m256d _mm256_movedup_pd (__m256d a)
    VMOVDDUP ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_movehdup_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Duplicate odd-indexed single-precision (32-bit) floating-point elements from ""a"", and store the results in ""dst"".
    
    __m256 _mm256_movehdup_ps (__m256 a)
    VMOVSHDUP ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_moveldup_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Duplicate even-indexed single-precision (32-bit) floating-point elements from ""a"", and store the results in ""dst"".
    
    __m256 _mm256_moveldup_ps (__m256 a)
    VMOVSLDUP ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_movemask_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Set each bit of mask ""dst"" based on the most significant bit of the corresponding packed double-precision (64-bit) floating-point element in ""a"".
    
    int _mm256_movemask_pd (__m256d a)
    VMOVMSKPD reg, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_movemask_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Set each bit of mask ""dst"" based on the most significant bit of the corresponding packed single-precision (32-bit) floating-point element in ""a"".
    
    int _mm256_movemask_ps (__m256 a)
    VMOVMSKPS reg, ymm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mul_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Multiply packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256d _mm256_mul_pd (__m256d a, __m256d b)
    VMULPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_mul_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Multiply packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256 _mm256_mul_ps (__m256 a, __m256 b)
    VMULPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_or_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256d _mm256_or_pd (__m256d a, __m256d b)
    VORPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_or_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256 _mm256_or_ps (__m256 a, __m256 b)
    VORPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permute_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle double-precision (64-bit) floating-point elements in ""a"" within 128-bit lanes using the control in ""imm8"", and store the results in ""dst"".
    
    __m256d _mm256_permute_pd (__m256d a, int imm8)
    VPERMILPD ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permute_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle single-precision (32-bit) floating-point elements in ""a"" within 128-bit lanes using the control in ""imm8"", and store the results in ""dst"".
    
    __m256 _mm256_permute_ps (__m256 a, int imm8)
    VPERMILPS ymm, ymm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permute2f128_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) selected by ""imm8"" from ""a"" and ""b"", and store the results in ""dst"".
    
    __m256d _mm256_permute2f128_pd (__m256d a, __m256d b, int imm8)
    VPERM2F128 ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permute2f128_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) selected by ""imm8"" from ""a"" and ""b"", and store the results in ""dst"".
    
    __m256 _mm256_permute2f128_ps (__m256 a, __m256 b, int imm8)
    VPERM2F128 ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permute2f128_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle 128-bits (composed of integer data) selected by ""imm8"" from ""a"" and ""b"", and store the results in ""dst"".
    
    __m256i _mm256_permute2f128_si256 (__m256i a, __m256i b, int imm8)
    VPERM2F128 ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permutevar_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle double-precision (64-bit) floating-point elements in ""a"" within 128-bit lanes using the control in ""b"", and store the results in ""dst"".
    
    __m256d _mm256_permutevar_pd (__m256d a, __m256i b)
    VPERMILPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_permutevar_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle single-precision (32-bit) floating-point elements in ""a"" within 128-bit lanes using the control in ""b"", and store the results in ""dst"".
    
    __m256 _mm256_permutevar_ps (__m256 a, __m256i b)
    VPERMILPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_rcp_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in ""a"", and store the results in ""dst"". The maximum relative error for this approximation is less than 1.5*2^-12.
    
    __m256 _mm256_rcp_ps (__m256 a)
    VRCPPS ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_round_pd1"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m256d _mm256_round_pd (__m256d a, _MM_FROUND_CUR_DIRECTION)
    VROUNDPD ymm, ymm/m256, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_round_pd1_to_nearest_integer"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m256d _mm256_round_pd (__m256d a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC)
    VROUNDPD ymm, ymm/m256, imm8(8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_round_pd1_to_negative_infinity"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m256d _mm256_round_pd (__m256d a, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC)
    VROUNDPD ymm, ymm/m256, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_round_pd1_to_positive_infinity"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m256d _mm256_round_pd (__m256d a, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC)
    VROUNDPD ymm, ymm/m256, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_round_pd1_to_zero"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m256d _mm256_round_pd (__m256d a, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC)
    VROUNDPD ymm, ymm/m256, imm8(11)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_round_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m256 _mm256_round_ps (__m256 a, _MM_FROUND_CUR_DIRECTION)
    VROUNDPS ymm, ymm/m256, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_round_ps_to_nearest_integer"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m256 _mm256_round_ps (__m256 a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC)
    VROUNDPS ymm, ymm/m256, imm8(8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_round_ps_to_negative_infinity"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m256 _mm256_round_ps (__m256 a, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC)
    VROUNDPS ymm, ymm/m256, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_round_ps_to_positive_infinity"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m256 _mm256_round_ps (__m256 a, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC)
    VROUNDPS ymm, ymm/m256, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_round_ps_to_zero"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m256 _mm256_round_ps (__m256 a, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC)
    VROUNDPS ymm, ymm/m256, imm8(11)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_rsqrt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in ""a"", and store the results in ""dst"". The maximum relative error for this approximation is less than 1.5*2^-12.
    
    __m256 _mm256_rsqrt_ps (__m256 a)
    VRSQRTPS ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_shuffle_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle double-precision (64-bit) floating-point elements within 128-bit lanes using the control in ""imm8"", and store the results in ""dst"".
    
    __m256d _mm256_shuffle_pd (__m256d a, __m256d b, const int imm8)
    VSHUFPD ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_shuffle_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Shuffle single-precision (32-bit) floating-point elements in ""a"" within 128-bit lanes using the control in ""imm8"", and store the results in ""dst"".
    
    __m256 _mm256_shuffle_ps (__m256 a, __m256 b, const int imm8)
    VSHUFPS ymm, ymm, ymm/m256, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sqrt_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the square root of packed double-precision (64-bit) floating-point elements in ""a"", and store the results in ""dst"".
    
    __m256d _mm256_sqrt_pd (__m256d a)
    VSQRTPD ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sqrt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the square root of packed single-precision (32-bit) floating-point elements in ""a"", and store the results in ""dst"".
    
    __m256 _mm256_sqrt_ps (__m256 a)
    VSQRTPS ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_store_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from ""a"" into memory.
    	""mem_addr"" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
    
    void _mm256_store_pd (double * mem_addr, __m256d a)
    VMOVAPD m256, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_store_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from ""a"" into memory.
    	""mem_addr"" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
    
    void _mm256_store_ps (float * mem_addr, __m256 a)
    VMOVAPS m256, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_store_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store 256-bits of integer data from ""a"" into memory.
    	""mem_addr"" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
    
    void _mm256_store_si256 (__m256i * mem_addr, __m256i a)
    MOVDQA m256, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_storeu_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from ""a"" into memory.
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    void _mm256_storeu_pd (double * mem_addr, __m256d a)
    MOVUPD m256, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_storeu_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from ""a"" into memory.
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    void _mm256_storeu_ps (float * mem_addr, __m256 a)
    MOVUPS m256, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_storeu_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store 256-bits of integer data from ""a"" into memory.
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    void _mm256_storeu_si256 (__m256i * mem_addr, __m256i a)
    MOVDQU m256, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_stream_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store 256-bits (composed of 4 packed double-precision (64-bit) floating-point elements) from ""a"" into memory using a non-temporal memory hint.
    	""mem_addr"" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
    
    void _mm256_stream_pd (double * mem_addr, __m256d a)
    MOVNTPD m256, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_stream_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store 256-bits (composed of 8 packed single-precision (32-bit) floating-point elements) from ""a"" into memory using a non-temporal memory hint.
    	""mem_addr"" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
    
    void _mm256_stream_ps (float * mem_addr, __m256 a)
    MOVNTPS m256, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_stream_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Store 256-bits of integer data from ""a"" into memory using a non-temporal memory hint.
    	""mem_addr"" must be aligned on a 32-byte boundary or a general-protection exception may be generated.
    
    void _mm256_stream_si256 (__m256i * mem_addr, __m256i a)
    VMOVNTDQ m256, ymm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm256_sub_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Subtract packed double-precision (64-bit) floating-point elements in ""b"" from packed double-precision (64-bit) floating-point elements in ""a"", and store the results in ""dst"".
    
    __m256d _mm256_sub_pd (__m256d a, __m256d b)
    VSUBPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_sub_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Subtract packed single-precision (32-bit) floating-point elements in ""b"" from packed single-precision (32-bit) floating-point elements in ""a"", and store the results in ""dst"".
    
    __m256 _mm256_sub_ps (__m256 a, __m256 b)
    VSUBPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_testc_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 256-bit value, and set ""ZF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return the ""CF"" value.
    
    int _mm256_testc_pd (__m256d a, __m256d b)
    VTESTPS ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_testc_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 256-bit value, and set ""ZF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return the ""CF"" value.
    
    int _mm256_testc_ps (__m256 a, __m256 b)
    VTESTPS ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_testc_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 256 bits (representing integer data) in ""a"" and ""b"", and set ""ZF"" to 1 if the result is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", and set ""CF"" to 1 if the result is zero, otherwise set ""CF"" to 0. Return the ""CF"" value.
    
    int _mm256_testc_si256 (__m256i a, __m256i b)
    VPTEST ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_testnzc_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 256-bit value, and set ""ZF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return 1 if both the ""ZF"" and ""CF"" values are zero, otherwise return 0.
    
    int _mm256_testnzc_pd (__m256d a, __m256d b)
    VTESTPD ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_testnzc_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 256-bit value, and set ""ZF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return 1 if both the ""ZF"" and ""CF"" values are zero, otherwise return 0.
    
    int _mm256_testnzc_ps (__m256 a, __m256 b)
    VTESTPS ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_testnzc_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 256 bits (representing integer data) in ""a"" and ""b"", and set ""ZF"" to 1 if the result is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", and set ""CF"" to 1 if the result is zero, otherwise set ""CF"" to 0. Return 1 if both the ""ZF"" and ""CF"" values are zero, otherwise return 0.
    
    int _mm256_testnzc_si256 (__m256i a, __m256i b)
    VPTEST ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_testz_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 256 bits (representing double-precision (64-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 256-bit value, and set ""ZF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 64-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return the ""ZF"" value.
    
    int _mm256_testz_pd (__m256d a, __m256d b)
    VTESTPD ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_testz_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 256 bits (representing single-precision (32-bit) floating-point elements) in ""a"" and ""b"", producing an intermediate 256-bit value, and set ""ZF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", producing an intermediate value, and set ""CF"" to 1 if the sign bit of each 32-bit element in the intermediate value is zero, otherwise set ""CF"" to 0. Return the ""ZF"" value.
    
    int _mm256_testz_ps (__m256 a, __m256 b)
    VTESTPS ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_testz_si256"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise AND of 256 bits (representing integer data) in ""a"" and ""b"", and set ""ZF"" to 1 if the result is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", and set ""CF"" to 1 if the result is zero, otherwise set ""CF"" to 0. Return the ""ZF"" value.
    
    int _mm256_testz_si256 (__m256i a, __m256i b)
    VPTEST ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpackhi_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Unpack and interleave double-precision (64-bit) floating-point elements from the high half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256d _mm256_unpackhi_pd (__m256d a, __m256d b)
    VUNPCKHPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpackhi_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Unpack and interleave single-precision (32-bit) floating-point elements from the high half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256 _mm256_unpackhi_ps (__m256 a, __m256 b)
    VUNPCKHPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpacklo_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Unpack and interleave double-precision (64-bit) floating-point elements from the low half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256d _mm256_unpacklo_pd (__m256d a, __m256d b)
    VUNPCKLPD ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_unpacklo_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Unpack and interleave single-precision (32-bit) floating-point elements from the low half of each 128-bit lane in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256 _mm256_unpacklo_ps (__m256 a, __m256 b)
    VUNPCKLPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_xor_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256d _mm256_xor_pd (__m256d a, __m256d b)
    VXORPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm256_xor_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / AVX";
                descriptor.Description = @"Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m256 _mm256_xor_ps (__m256 a, __m256 b)
    VXORPS ymm, ymm, ymm/m256";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Bmi1IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("andn_u32", (Func<uint, uint, uint>)andn_u32);
            RegisterFunction("bextr_u32", (Func<uint, byte, byte, uint>)bextr_u32);
            RegisterFunction("bextr2_u32", (Func<uint, ushort, uint>)bextr2_u32);
            RegisterFunction("blsi_u32", (Func<uint, uint>)blsi_u32);
            RegisterFunction("blsmsk_u32", (Func<uint, uint>)blsmsk_u32);
            RegisterFunction("blsr_u32", (Func<uint, uint>)blsr_u32);
            RegisterFunction("mm_tzcnt_32", (Func<uint, uint>)mm_tzcnt_32);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["andn_u32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned int _andn_u32 (unsigned int a, unsigned int b)
    ANDN r32a, r32b, reg/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["bextr_u32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned int _bextr_u32 (unsigned int a, unsigned int start, unsigned int len)
    BEXTR r32a, reg/m32, r32b";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["bextr2_u32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned int _bextr2_u32 (unsigned int a, unsigned int control)
    BEXTR r32a, reg/m32, r32b";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["blsi_u32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned int _blsi_u32 (unsigned int a)
    BLSI reg, reg/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["blsmsk_u32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned int _blsmsk_u32 (unsigned int a)
    BLSMSK reg, reg/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["blsr_u32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned int _blsr_u32 (unsigned int a)
    BLSR reg, reg/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_tzcnt_32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"int _mm_tzcnt_32 (unsigned int a)
    TZCNT reg, reg/m32";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Bmi1X64IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("andn_u64", (Func<ulong, ulong, ulong>)andn_u64);
            RegisterFunction("bextr_u64", (Func<ulong, byte, byte, ulong>)bextr_u64);
            RegisterFunction("bextr2_u64", (Func<ulong, ushort, ulong>)bextr2_u64);
            RegisterFunction("blsi_u64", (Func<ulong, ulong>)blsi_u64);
            RegisterFunction("blsmsk_u64", (Func<ulong, ulong>)blsmsk_u64);
            RegisterFunction("blsr_u64", (Func<ulong, ulong>)blsr_u64);
            RegisterFunction("mm_tzcnt_64", (Func<ulong, ulong>)mm_tzcnt_64);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["andn_u64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned __int64 _andn_u64 (unsigned __int64 a, unsigned __int64 b)
    ANDN r64a, r64b, reg/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["bextr_u64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned __int64 _bextr_u64 (unsigned __int64 a, unsigned int start, unsigned int len)
    BEXTR r64a, reg/m64, r64b";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["bextr2_u64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned __int64 _bextr2_u64 (unsigned __int64 a, unsigned __int64 control)
    BEXTR r64a, reg/m64, r64b";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["blsi_u64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned __int64 _blsi_u64 (unsigned __int64 a)
    BLSI reg, reg/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["blsmsk_u64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned __int64 _blsmsk_u64 (unsigned __int64 a)
    BLSMSK reg, reg/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["blsr_u64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"unsigned __int64 _blsr_u64 (unsigned __int64 a)
    BLSR reg, reg/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_tzcnt_64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI1";
                descriptor.Description = @"__int64 _mm_tzcnt_64 (unsigned __int64 a)
    TZCNT reg, reg/m64";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Bmi2IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("bzhi_u32", (Func<uint, uint, uint>)bzhi_u32);
            RegisterFunction("mulx_u32", (Func<uint, uint, uint>)mulx_u32);
            RegisterFunction("pdep_u32", (Func<uint, uint, uint>)pdep_u32);
            RegisterFunction("pext_u32", (Func<uint, uint, uint>)pext_u32);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["bzhi_u32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI2";
                descriptor.Description = @"unsigned int _bzhi_u32 (unsigned int a, unsigned int index)
    BZHI r32a, reg/m32, r32b";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mulx_u32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI2";
                descriptor.Description = @"unsigned int _mulx_u32 (unsigned int a, unsigned int b, unsigned int* hi)
    MULX r32a, r32b, reg/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["pdep_u32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI2";
                descriptor.Description = @"unsigned int _pdep_u32 (unsigned int a, unsigned int mask)
    PDEP r32a, r32b, reg/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["pext_u32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI2";
                descriptor.Description = @"unsigned int _pext_u32 (unsigned int a, unsigned int mask)
    PEXT r32a, r32b, reg/m32";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Bmi2X64IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("bzhi_u64", (Func<ulong, ulong, ulong>)bzhi_u64);
            RegisterFunction("mulx_u64", (Func<ulong, ulong, ulong>)mulx_u64);
            RegisterFunction("pdep_u64", (Func<ulong, ulong, ulong>)pdep_u64);
            RegisterFunction("pext_u64", (Func<ulong, ulong, ulong>)pext_u64);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["bzhi_u64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI2";
                descriptor.Description = @"unsigned __int64 _bzhi_u64 (unsigned __int64 a, unsigned int index)
    BZHI r64a, reg/m32, r64b";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mulx_u64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI2";
                descriptor.Description = @"unsigned __int64 _mulx_u64 (unsigned __int64 a, unsigned __int64 b, unsigned __int64* hi)
    MULX r64a, r64b, reg/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["pdep_u64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI2";
                descriptor.Description = @"unsigned __int64 _pdep_u64 (unsigned __int64 a, unsigned __int64 mask)
    PDEP r64a, r64b, reg/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["pext_u64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / BMI2";
                descriptor.Description = @"unsigned __int64 _pext_u64 (unsigned __int64 a, unsigned __int64 mask)
    PEXT r64a, r64b, reg/m64";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.Arm
{
    public partial class Crc32Arm64IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("crc32cd", (Func<uint, ulong, uint>)crc32cd);
            RegisterFunction("crc32d", (Func<uint, ulong, uint>)crc32d);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["crc32cd"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / CRC32";
                descriptor.Description = @"uint32_t __crc32cd (uint32_t a, uint64_t b)
    A64: CRC32CX Wd, Wn, Xm
    
    
    Instruction Documentation: [crc32cd](https://developer.arm.com/architectures/instruction-sets/intrinsics/crc32cd)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["crc32d"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / CRC32";
                descriptor.Description = @"uint32_t __crc32d (uint32_t a, uint64_t b)
    A64: CRC32X Wd, Wn, Xm
    
    
    Instruction Documentation: [crc32d](https://developer.arm.com/architectures/instruction-sets/intrinsics/crc32d)";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.Arm
{
    public partial class Crc32IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("crc32b", (Func<uint, byte, uint>)crc32b);
            RegisterFunction("crc32cb", (Func<uint, byte, uint>)crc32cb);
            RegisterFunction("crc32ch", (Func<uint, ushort, uint>)crc32ch);
            RegisterFunction("crc32cw", (Func<uint, uint, uint>)crc32cw);
            RegisterFunction("crc32h", (Func<uint, ushort, uint>)crc32h);
            RegisterFunction("crc32w", (Func<uint, uint, uint>)crc32w);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["crc32b"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / CRC32";
                descriptor.Description = @"uint32_t __crc32b (uint32_t a, uint8_t b)
    A32: CRC32B Rd, Rn, Rm
    A64: CRC32B Wd, Wn, Wm
    
    
    Instruction Documentation: [crc32b](https://developer.arm.com/architectures/instruction-sets/intrinsics/crc32b)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["crc32cb"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / CRC32";
                descriptor.Description = @"uint32_t __crc32cb (uint32_t a, uint8_t b)
    A32: CRC32CB Rd, Rn, Rm
    A64: CRC32CB Wd, Wn, Wm
    
    
    Instruction Documentation: [crc32cb](https://developer.arm.com/architectures/instruction-sets/intrinsics/crc32cb)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["crc32ch"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / CRC32";
                descriptor.Description = @"uint32_t __crc32ch (uint32_t a, uint16_t b)
    A32: CRC32CH Rd, Rn, Rm
    A64: CRC32CH Wd, Wn, Wm
    
    
    Instruction Documentation: [crc32ch](https://developer.arm.com/architectures/instruction-sets/intrinsics/crc32ch)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["crc32cw"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / CRC32";
                descriptor.Description = @"uint32_t __crc32cw (uint32_t a, uint32_t b)
    A32: CRC32CW Rd, Rn, Rm
    A64: CRC32CW Wd, Wn, Wm
    
    
    Instruction Documentation: [crc32cw](https://developer.arm.com/architectures/instruction-sets/intrinsics/crc32cw)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["crc32h"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / CRC32";
                descriptor.Description = @"uint32_t __crc32h (uint32_t a, uint16_t b)
    A32: CRC32H Rd, Rn, Rm
    A64: CRC32H Wd, Wn, Wm
    
    
    Instruction Documentation: [crc32h](https://developer.arm.com/architectures/instruction-sets/intrinsics/crc32h)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["crc32w"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / CRC32";
                descriptor.Description = @"uint32_t __crc32w (uint32_t a, uint32_t b)
    A32: CRC32W Rd, Rn, Rm
    A64: CRC32W Wd, Wn, Wm
    
    
    Instruction Documentation: [crc32w](https://developer.arm.com/architectures/instruction-sets/intrinsics/crc32w)";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules
{
    public partial class CsvModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("parse_csv", (Func<string, bool, Scriban.Runtime.ScriptRange>)ParseCsv);
            RegisterFunction("load_csv", (Func<string, bool, Scriban.Runtime.ScriptRange>)LoadCsv);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptor;
                descriptor.Category = "Modules (e.g `import Files`)";
                descriptor.Description = @"Module for loading/parsing CSV text/files.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["parse_csv"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Parse the specified text as a CSV, returning each CSV line in an array.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The text to parse.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("headers", @"true if the text to parse has CSV headers. Default is fault.")  { IsOptional = true });
                descriptor.Returns = @"An array of CSV columns values.";
                descriptor.Example = @"    >>> items = parse_csv(""a,b,c\n1,2,3\n4,5,6\n"")
    # items = parse_csv(""a,b,c\n1,2,3\n4,5,6\n"")
    items = [[1, 2, 3], [4, 5, 6]]
    >>> items[0].a
    # items[0].a
    out = 1
    >>> items[0].b
    # items[0].b
    out = 2
    >>> items[0].c
    # items[0].c
    out = 3
";
            }
            {
                var descriptor = Descriptors["load_csv"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Loads the specified file as a CSV, returning each CSV line in an array.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"The file path to load and parse as CSV.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("headers", @"true if the file to parse has CSV headers. Default is fault.")  { IsOptional = true });
                descriptor.Returns = @"An array of CSV columns values.";
                descriptor.Example = @"    >>> items = load_csv(""test.csv"")
    # items = load_csv(""test.csv"")
    items = [[1, 2, 3], [4, 5, 6]]
    >>> items[0].a
    # items[0].a
    out = 1
    >>> items[1].a
    # items[1].a
    out = 4
    >>> items[1].c
    # items[1].c
    out = 6
";
            }
        }        
    }
}
namespace Kalk.Core.Modules
{
    public partial class CurrencyModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterConstant("currencies", Currencies);
            RegisterFunction("currency", (Func<Scriban.Syntax.ScriptVariable, decimal?, Kalk.Core.KalkCurrency>)Currency);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptor;
                descriptor.Category = "Modules (e.g `import Files`)";
                descriptor.Description = @"";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["currencies"];
                descriptor.Category = "Unit Functions";
                descriptor.Description = @"Gets all the defined currencies. The default base currency is EUR.";
                descriptor.IsCommand = false;
                descriptor.Returns = @"All the defined currencies.";
                descriptor.Example = @"    >>> currencies
    # Builtin Currencies (Last Update: 06 Mar 2022)
    currency(AED, 4.1321);      # 4.1321   AED => 1 EUR
    currency(AFN, 101.9887);    # 101.9887 AFN => 1 EUR
    currency(ALL, 122.7378);    # 122.7378 ALL => 1 EUR
    currency(AMD, 547.57);      # 547.57   AMD => 1 EUR
    currency(ANG, 1.991);       # 1.991    ANG => 1 EUR
    currency(AOA, 556.8346);    # 556.8346 AOA => 1 EUR
    currency(ARS, 119.7553);    # 119.7553 ARS => 1 EUR
    currency(AUD, 1.5035);      # 1.5035   AUD => 1 EUR
    currency(AWG, 2.0255);      # 2.0255   AWG => 1 EUR
    currency(AZN, 1.9218);      # 1.9218   AZN => 1 EUR
    currency(BAM, 1.9793);      # 1.9793   BAM => 1 EUR
    currency(BBD, 2.2596);      # 2.2596   BBD => 1 EUR
    currency(BDT, 97.0603);     # 97.0603  BDT => 1 EUR
    currency(BGN, 1.9434);      # 1.9434   BGN => 1 EUR
    currency(BHD, 0.4176);      # 0.4176   BHD => 1 EUR
    currency(BIF, 2237.6264);   # 2237.6264 BIF => 1 EUR
    currency(BND, 1.521);       # 1.521    BND => 1 EUR
    currency(BOB, 7.637);       # 7.637    BOB => 1 EUR
    currency(BRL, 5.7249);      # 5.7249   BRL => 1 EUR
    currency(BSD, 1.1188);      # 1.1188   BSD => 1 EUR
    currency(BWP, 13.0967);     # 13.0967  BWP => 1 EUR
    currency(BYN, 3.0139);      # 3.0139   BYN => 1 EUR
    currency(BZD, 2.2559);      # 2.2559   BZD => 1 EUR
    currency(CAD, 1.4037);      # 1.4037   CAD => 1 EUR
    currency(CDF, 2239.6954);   # 2239.6954 CDF => 1 EUR
    currency(CHF, 1.0139);      # 1.0139   CHF => 1 EUR
    currency(CLP, 883.8071);    # 883.8071 CLP => 1 EUR
    currency(CNY, 6.9712);      # 6.9712   CNY => 1 EUR
    currency(COP, 4286.4925);   # 4286.4925 COP => 1 EUR
    currency(CRC, 716.9159);    # 716.9159 CRC => 1 EUR
    currency(CUP, 1.1188);      # 1.1188   CUP => 1 EUR
    currency(CVE, 111.8813);    # 111.8813 CVE => 1 EUR
    currency(CZK, 25.0893);     # 25.0893  CZK => 1 EUR
    currency(DJF, 199.2294);    # 199.2294 DJF => 1 EUR
    currency(DKK, 7.4076);      # 7.4076   DKK => 1 EUR
    currency(DOP, 60.9968);     # 60.9968  DOP => 1 EUR
    currency(DZD, 158.8736);    # 158.8736 DZD => 1 EUR
    currency(EGP, 17.3547);     # 17.3547  EGP => 1 EUR
    currency(ERN, 16.8738);     # 16.8738  ERN => 1 EUR
    currency(ETB, 57.3988);     # 57.3988  ETB => 1 EUR
    currency(EUR);              # Base currency
    currency(FJD, 2.3779);      # 2.3779   FJD => 1 EUR
    currency(GBP, 0.8274);      # 0.8274   GBP => 1 EUR
    currency(GEL, 3.4675);      # 3.4675   GEL => 1 EUR
    currency(GHS, 7.7215);      # 7.7215   GHS => 1 EUR
    currency(GIP, 0.834);       # 0.834    GIP => 1 EUR
    currency(GMD, 59.7344);     # 59.7344  GMD => 1 EUR
    currency(GNF, 10050.7494);  # 10050.7494 GNF => 1 EUR
    currency(GTQ, 8.64);        # 8.64     GTQ => 1 EUR
    currency(GYD, 234.1451);    # 234.1451 GYD => 1 EUR
    currency(HKD, 8.6189);      # 8.6189   HKD => 1 EUR
    currency(HNL, 27.5567);     # 27.5567  HNL => 1 EUR
    currency(HRK, 7.502);       # 7.502    HRK => 1 EUR
    currency(HTG, 116.6989);    # 116.6989 HTG => 1 EUR
    currency(HUF, 371.8363);    # 371.8363 HUF => 1 EUR
    currency(IDR, 15844.3432);  # 15844.3432 IDR => 1 EUR
    currency(ILS, 3.5775);      # 3.5775   ILS => 1 EUR
    currency(INR, 83.7335);     # 83.7335  INR => 1 EUR
    currency(IQD, 1653.9687);   # 1653.9687 IQD => 1 EUR
    currency(IRR, 47584.1953);  # 47584.1953 IRR => 1 EUR
    currency(ISK, 145.4218);    # 145.4218 ISK => 1 EUR
    currency(JMD, 173.0165);    # 173.0165 JMD => 1 EUR
    currency(JOD, 0.7851);      # 0.7851   JOD => 1 EUR
    currency(JPY, 127.1764);    # 127.1764 JPY => 1 EUR
    currency(KES, 127.469);     # 127.469  KES => 1 EUR
    currency(KGS, 96.0913);     # 96.0913  KGS => 1 EUR
    currency(KHR, 4548.7899);   # 4548.7899 KHR => 1 EUR
    currency(KMF, 494.4337);    # 494.4337 KMF => 1 EUR
    currency(KRW, 1336.5796);   # 1336.5796 KRW => 1 EUR
    currency(KWD, 0.3362);      # 0.3362   KWD => 1 EUR
    currency(KZT, 488.6859);    # 488.6859 KZT => 1 EUR
    currency(LAK, 12816.035);   # 12816.035 LAK => 1 EUR
    currency(LBP, 1701.7387);   # 1701.7387 LBP => 1 EUR
    currency(LKR, 224.4293);    # 224.4293 LKR => 1 EUR
    currency(LRD, 172.4008);    # 172.4008 LRD => 1 EUR
    currency(LSL, 17.3326);     # 17.3326  LSL => 1 EUR
    currency(LYD, 5.2191);      # 5.2191   LYD => 1 EUR
    currency(MAD, 10.7205);     # 10.7205  MAD => 1 EUR
    currency(MDL, 19.921);      # 19.921   MDL => 1 EUR
    currency(MGA, 4469.0602);   # 4469.0602 MGA => 1 EUR
    currency(MKD, 62.1946);     # 62.1946  MKD => 1 EUR
    currency(MMK, 1990.3292);   # 1990.3292 MMK => 1 EUR
    currency(MNT, 3229.6408);   # 3229.6408 MNT => 1 EUR
    currency(MOP, 9.013);       # 9.013    MOP => 1 EUR
    currency(MRO, 40.1478);     # 40.1478  MRO => 1 EUR
    currency(MRU, 40.7098);     # 40.7098  MRU => 1 EUR
    currency(MUR, 49.6868);     # 49.6868  MUR => 1 EUR
    currency(MVR, 17.3016);     # 17.3016  MVR => 1 EUR
    currency(MWK, 913.7045);    # 913.7045 MWK => 1 EUR
    currency(MXN, 22.8123);     # 22.8123  MXN => 1 EUR
    currency(MYR, 4.6522);      # 4.6522   MYR => 1 EUR
    currency(MZN, 71.7698);     # 71.7698  MZN => 1 EUR
    currency(NAD, 17.3264);     # 17.3264  NAD => 1 EUR
    currency(NGN, 462.1707);    # 462.1707 NGN => 1 EUR
    currency(NIO, 40.0038);     # 40.0038  NIO => 1 EUR
    currency(NOK, 9.8676);      # 9.8676   NOK => 1 EUR
    currency(NPR, 135.0813);    # 135.0813 NPR => 1 EUR
    currency(NZD, 1.6167);      # 1.6167   NZD => 1 EUR
    currency(OMR, 0.4266);      # 0.4266   OMR => 1 EUR
    currency(PAB, 1.111);       # 1.111    PAB => 1 EUR
    currency(PEN, 4.1375);      # 4.1375   PEN => 1 EUR
    currency(PGK, 3.8901);      # 3.8901   PGK => 1 EUR
    currency(PHP, 57.3084);     # 57.3084  PHP => 1 EUR
    currency(PKR, 199.6326);    # 199.6326 PKR => 1 EUR
    currency(PLN, 4.6972);      # 4.6972   PLN => 1 EUR
    currency(PYG, 7755.7086);   # 7755.7086 PYG => 1 EUR
    currency(QAR, 4.0413);      # 4.0413   QAR => 1 EUR
    currency(RON, 4.9172);      # 4.9172   RON => 1 EUR
    currency(RSD, 119.3434);    # 119.3434 RSD => 1 EUR
    currency(RUB, 112.2525);    # 112.2525 RUB => 1 EUR
    currency(RWF, 1135.3319);   # 1135.3319 RWF => 1 EUR
    currency(SAR, 4.1418);      # 4.1418   SAR => 1 EUR
    currency(SBD, 9.1509);      # 9.1509   SBD => 1 EUR
    currency(SCR, 16.116);      # 16.116   SCR => 1 EUR
    currency(SDG, 499.429);     # 499.429  SDG => 1 EUR
    currency(SEK, 10.7168);     # 10.7168  SEK => 1 EUR
    currency(SGD, 1.4967);      # 1.4967   SGD => 1 EUR
    currency(SLL, 13022.7453);  # 13022.7453 SLL => 1 EUR
    currency(SOS, 647.3956);    # 647.3956 SOS => 1 EUR
    currency(SRD, 22.9053);     # 22.9053  SRD => 1 EUR
    currency(SSP, 481.2219);    # 481.2219 SSP => 1 EUR
    currency(STN, 24.9843);     # 24.9843  STN => 1 EUR
    currency(SVC, 9.7967);      # 9.7967   SVC => 1 EUR
    currency(SYP, 2849.6831);   # 2849.6831 SYP => 1 EUR
    currency(SZL, 17.3326);     # 17.3326  SZL => 1 EUR
    currency(THB, 36.5233);     # 36.5233  THB => 1 EUR
    currency(TJS, 12.8);        # 12.8     TJS => 1 EUR
    currency(TMT, 3.9647);      # 3.9647   TMT => 1 EUR
    currency(TND, 3.2868);      # 3.2868   TND => 1 EUR
    currency(TOP, 2.544);       # 2.544    TOP => 1 EUR
    currency(TRY, 15.584);      # 15.584   TRY => 1 EUR
    currency(TTD, 7.5908);      # 7.5908   TTD => 1 EUR
    currency(TWD, 31.0675);     # 31.0675  TWD => 1 EUR
    currency(TZS, 2592.0071);   # 2592.0071 TZS => 1 EUR
    currency(UAH, 32.6392);     # 32.6392  UAH => 1 EUR
    currency(UGX, 3954.6622);   # 3954.6622 UGX => 1 EUR
    currency(USD, 1.1033);      # 1.1033   USD => 1 EUR
    currency(UYU, 47.3672);     # 47.3672  UYU => 1 EUR
    currency(UZS, 12247.9056);  # 12247.9056 UZS => 1 EUR
    currency(VES, 4.855);       # 4.855    VES => 1 EUR
    currency(VND, 25428.9059);  # 25428.9059 VND => 1 EUR
    currency(VUV, 126.043);     # 126.043  VUV => 1 EUR
    currency(WST, 2.8821);      # 2.8821   WST => 1 EUR
    currency(XAF, 662.6246);    # 662.6246 XAF => 1 EUR
    currency(XCD, 3.0335);      # 3.0335   XCD => 1 EUR
    currency(XOF, 662.8467);    # 662.8467 XOF => 1 EUR
    currency(XPF, 120.3832);    # 120.3832 XPF => 1 EUR
    currency(YER, 280.0428);    # 280.0428 YER => 1 EUR
    currency(ZAR, 16.8689);     # 16.8689  ZAR => 1 EUR
    currency(ZMW, 19.9607);     # 19.9607  ZMW => 1 EUR
";
            }
            {
                var descriptor = Descriptors["currency"];
                descriptor.Category = "Unit Functions";
                descriptor.Description = @"Gets or sets the default currency. The default base currency is EUR.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("name", @"If not null, name of the currency to set.")  { IsOptional = true });
                descriptor.Params.Add(new KalkParamDescriptor("value", @"If name is not null, value of the currency")  { IsOptional = true });
                descriptor.Returns = @"The default defined currency.";
                descriptor.Example = @"    >>> USD
    currency(USD, 1.1033);      # 1.1033   USD => 1 EUR
    >>> 2 USD
    # 2 * USD
    out = 1.8127918828265197793338250828 * EUR
    >>> currency(GBP) # Defines GBP as the default currency instead of EUR
    # currency(GBP) # Defines GBP as the default currency instead of EUR
    out = GBP
    >>> USD
    currency(USD, 1.3334);      # 1.3334   USD => 1 GBP
    >>> 2 USD |> to EUR # Convert 2 dollars to EUR
    # 2 * USD |> to(EUR) # Convert 2 dollars to EUR
    out = 1.8127918828265266 * EUR
";
            }
        }        
    }
}
namespace Kalk.Core.Modules
{
    public partial class FileModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("pwd", (Func<string>)CurrentDirectory);
            RegisterFunction("cd", (Func<string, string>)ChangeDirectory);
            RegisterFunction("file_exists", (Func<string, Kalk.Core.KalkBool>)FileExists);
            RegisterFunction("dir_exists", (Func<string, Kalk.Core.KalkBool>)DirectoryExists);
            RegisterFunction("dir", (Func<string, bool, System.Collections.IEnumerable>)DirectoryListing);
            RegisterAction("rm", (Action<string>)RemoveFile);
            RegisterAction("mkdir", (Action<string>)CreateDirectory);
            RegisterAction("rmdir", (Action<string, bool>)RemoveDirectory);
            RegisterFunction("load_text", (Func<string, string, string>)LoadText);
            RegisterFunction("load_bytes", (Func<string, Kalk.Core.KalkNativeBuffer>)LoadBytes);
            RegisterFunction("load_lines", (Func<string, string, Scriban.Runtime.ScriptRange>)LoadLines);
            RegisterFunction("save_lines", (Func<System.Collections.IEnumerable, string, string, object>)SaveLines);
            RegisterFunction("save_text", (Func<string, string, string, object>)SaveText);
            RegisterFunction("save_bytes", (Func<System.Collections.IEnumerable, string, object>)SaveBytes);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptor;
                descriptor.Category = "Modules (e.g `import Files`)";
                descriptor.Description = @"Modules providing file related functions.";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["pwd"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Gets the current directory.";
                descriptor.IsCommand = false;
                descriptor.Returns = @"The current directory.";
                descriptor.Example = @"    >>> pwd
    # pwd
    out = ""/code/kalk/tests""
";
            }
            {
                var descriptor = Descriptors["cd"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Changes the current directory to the specified path.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path to the directory to change.")  { IsOptional = true });
                descriptor.Returns = @"The current directory or throws an exception if the directory does not exists";
                descriptor.Example = @"    >>> cd
    # cd
    out = ""/code/kalk/tests""
    >>> mkdir ""testdir""
    >>> cd ""testdir""
    # cd(""testdir"")
    out = ""/code/kalk/tests/testdir""
    >>> cd ""..""
    # cd("".."")
    out = ""/code/kalk/tests""
    >>> rmdir ""testdir""
    >>> dir_exists ""testdir""
    # dir_exists(""testdir"")
    out = false
";
            }
            {
                var descriptor = Descriptors["file_exists"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Checks if the specified file path exists on the disk.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path to a file.")  { IsOptional = false });
                descriptor.Returns = @"`true` if the specified file path exists on the disk.";
                descriptor.Example = @"    >>> rm ""test.txt""
    >>> file_exists ""test.txt""
    # file_exists(""test.txt"")
    out = false
    >>> save_text(""content"", ""test.txt"")
    >>> file_exists ""test.txt""
    # file_exists(""test.txt"")
    out = true
";
            }
            {
                var descriptor = Descriptors["dir_exists"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Checks if the specified directory path exists on the disk.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path to a directory.")  { IsOptional = false });
                descriptor.Returns = @"`true` if the specified directory path exists on the disk.";
                descriptor.Example = @"    >>> mkdir ""testdir""
    >>> dir_exists ""testdir""
    # dir_exists(""testdir"")
    out = true
    >>> rmdir ""testdir""
    >>> dir_exists ""testdir""
    # dir_exists(""testdir"")
    out = false
";
            }
            {
                var descriptor = Descriptors["dir"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"List files and directories from the specified path or the current directory.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"The specified directory or the current directory if not specified.")  { IsOptional = true });
                descriptor.Params.Add(new KalkParamDescriptor("recursive", @"A boolean to perform a recursive list. Default is `false`.")  { IsOptional = true });
                descriptor.Returns = @"An enumeration of the files and directories.";
                descriptor.Example = @"    >>> mkdir ""testdir""
    >>> cd ""testdir""
    # cd(""testdir"")
    out = ""/code/kalk/tests/testdir""
    >>> mkdir ""subdir""
    >>> save_text(""content"", ""file.txt"")
    >>> dir "".""
    # dir(""."")
    out = [""./file.txt"", ""./subdir""]
    >>> save_text(""content"", ""subdir/file2.txt"")
    >>> dir(""."", true)
    # dir(""."", true)
    out = [""./file.txt"", ""./subdir"", ""./subdir/file2.txt""]
    >>> cd ""..""
    # cd("".."")
    out = ""/code/kalk/tests""
    >>> rmdir(""testdir"", true)
";
            }
            {
                var descriptor = Descriptors["rm"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Deletes a file from the specified path.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path to the file to delete.")  { IsOptional = false });
                descriptor.Example = @"    >>> rm ""test.txt""
    >>> file_exists ""test.txt""
    # file_exists(""test.txt"")
    out = false
    >>> save_text(""content"", ""test.txt"")
    >>> file_exists ""test.txt""
    # file_exists(""test.txt"")
    out = true
";
            }
            {
                var descriptor = Descriptors["mkdir"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Creates a directory at the specified path.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path of the directory to create.")  { IsOptional = false });
                descriptor.Example = @"    >>> mkdir ""testdir""
    >>> dir_exists ""testdir""
    # dir_exists(""testdir"")
    out = true
    >>> rmdir ""testdir""
    >>> dir_exists ""testdir""
    # dir_exists(""testdir"")
    out = false
";
            }
            {
                var descriptor = Descriptors["rmdir"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Deletes the directory at the specified path.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path to the directory to delete.")  { IsOptional = false });
                descriptor.Example = @"    >>> mkdir ""testdir""
    >>> dir_exists ""testdir""
    # dir_exists(""testdir"")
    out = true
    >>> rmdir ""testdir""
    >>> dir_exists ""testdir""
    # dir_exists(""testdir"")
    out = false
";
            }
            {
                var descriptor = Descriptors["load_text"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Loads the specified file as text.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path to a file to load as text.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("encoding", @"The encoding of the file. Default is ""utf-8""")  { IsOptional = true });
                descriptor.Returns = @"The file loaded as a string.";
                descriptor.Example = @"    >>> load_text ""test.csv""
    # load_text(""test.csv"")
    out = ""a,b,c\n1,2,3\n4,5,6""
";
            }
            {
                var descriptor = Descriptors["load_bytes"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Loads the specified file as binary.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path to a file to load as binary.")  { IsOptional = false });
                descriptor.Returns = @"The file loaded as a a byte buffer.";
                descriptor.Example = @"    >>> load_bytes ""test.csv""
    # load_bytes(""test.csv"")
    out = bytebuffer([97, 44, 98, 44, 99, 10, 49, 44, 50, 44, 51, 10, 52, 44, 53, 44, 54])
    >>> ascii out
    # ascii(out)
    out = ""a,b,c\n1,2,3\n4,5,6""
";
            }
            {
                var descriptor = Descriptors["load_lines"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Load each lines from the specified file path.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path to a file to load lines from.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("encoding", @"The encoding of the file. Default is ""utf-8""")  { IsOptional = true });
                descriptor.Returns = @"An enumeration on the lines.";
                descriptor.Example = @"    >>> load_lines ""test.csv""
    # load_lines(""test.csv"")
    out = [""a,b,c"", ""1,2,3"", ""4,5,6""]
";
            }
            {
                var descriptor = Descriptors["save_lines"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Saves an array of data as string to the specified files.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("lines", @"An array of data.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path to the file to save the lines to.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("encoding", @"The encoding of the file. Default is ""utf-8""")  { IsOptional = true });
                descriptor.Example = @"    >>> save_lines(1..10, ""lines.txt"")
    >>> load_lines(""lines.txt"")
    # load_lines(""lines.txt"")
    out = [""1"", ""2"", ""3"", ""4"", ""5"", ""6"", ""7"", ""8"", ""9"", ""10""]
";
            }
            {
                var descriptor = Descriptors["save_text"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Saves a text to the specified file path.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The text to save.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path to the file to save the text to.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("encoding", @"The encoding of the file. Default is ""utf-8""")  { IsOptional = true });
                descriptor.Example = @"    >>> save_text(""Hello World!"", ""test.txt"")
    >>> load_text(""test.txt"")
    # load_text(""test.txt"")
    out = ""Hello World!""
";
            }
            {
                var descriptor = Descriptors["save_bytes"];
                descriptor.Category = "Misc File Functions";
                descriptor.Description = @"Saves a byte buffer to the specified file path.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("data", @"The data to save.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("path", @"Path to the file to save the data to.")  { IsOptional = false });
                descriptor.Example = @"    >>> utf8(""Hello World!"")
    # utf8(""Hello World!"")
    out = bytebuffer([72, 101, 108, 108, 111, 32, 87, 111, 114, 108, 100, 33])
    >>> save_bytes(out, ""test.bin"")
    >>> load_bytes(""test.bin"")
    # load_bytes(""test.bin"")
    out = bytebuffer([72, 101, 108, 108, 111, 32, 87, 111, 114, 108, 100, 33])
    >>> utf8(out)
    # utf8(out)
    out = ""Hello World!""
";
            }
        }        
    }
}
namespace Kalk.Core.Modules
{
    public partial class HardwareIntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptor;
                descriptor.Category = "Modules (e.g `import Files`)";
                descriptor.Description = @"Module with CPU Hardware intrinsics.";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core
{
    public partial class KalkEngine
    {
        protected void RegisterFunctionsAuto()
        {
            RegisterConstant("config", Config);
            RegisterConstant("aliases", Aliases);
            RegisterConstant("shortcuts", Shortcuts);
            RegisterFunction("action", (Func<string, Kalk.Core.KalkActionObject>)Action);
            RegisterAction("license", (Action)License);
            RegisterFunction("clipboard", (Func<object, object>)Clipboard);
            RegisterAction("display", (Action<Scriban.Syntax.ScriptVariable>)Display);
            RegisterAction("echo", (Action<Scriban.Syntax.ScriptVariable>)Echo);
            RegisterAction("print", (Action<object>)Print);
            RegisterAction("printf", (Action<object>)PrintFormatted);
            RegisterFunction("sprintf", (Func<object, string>)StringPrintFormatted);
            RegisterAction("printh", (Action<object>)Printh);
            RegisterAction("help", (Action<Scriban.Syntax.ScriptExpression>)Help);
            RegisterAction("reset", (Action)Reset);
            RegisterAction("version", (Action)ShowVersion);
            RegisterAction("list", (Action)List);
            RegisterAction("del", (Action<Scriban.Syntax.ScriptVariable>)DeleteVariable);
            RegisterAction("exit", (Action)Exit);
            RegisterAction("history", (Action<object>)History);
            RegisterFunction("eval", (Func<string, bool, object>)EvaluateText);
            RegisterFunction("load", (Func<string, bool, object>)LoadFile);
            RegisterAction("clear", (Action<Scriban.Syntax.ScriptExpression>)Clear);
            RegisterAction("cls", (Action)Cls);
            RegisterFunction("out", (Func<object>)Last);
            RegisterAction("out2clipboard", (Action)LastToClipboard);
            RegisterAction("shortcut", (Action<Scriban.Syntax.ScriptVariable, Scriban.Syntax.ScriptExpression[]>)Shortcut);
            RegisterAction("alias", (Action<Scriban.Syntax.ScriptVariable, Scriban.Syntax.ScriptVariable[]>)Alias);
            RegisterFunction("kind", (Func<object, string>)Kind);
            RegisterConstant("units", Units);
            RegisterFunction("to", (Func<Kalk.Core.KalkExpression, Kalk.Core.KalkExpression, Kalk.Core.KalkExpression>)ConvertTo);
            RegisterFunction("unit", (Func<Scriban.Syntax.ScriptVariable, string, Scriban.Syntax.ScriptVariable, Kalk.Core.KalkExpression, string, string, Kalk.Core.KalkExpression>)DefineUserUnit);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["config"];
                descriptor.Category = "General";
                descriptor.Description = @"Gets the config object.";
                descriptor.IsCommand = false;
                descriptor.Example = @"    >>> config
    # config
    out = {help_max_column: 100, limit_to_string: ""auto""}
";
            }
            {
                var descriptor = Descriptors["aliases"];
                descriptor.Category = "General";
                descriptor.Description = @"Displays all built-in and user-defined aliases.";
                descriptor.IsCommand = false;
                descriptor.Remarks = @"Aliases are usually used to define equivalent variable names for equivalent mathematical symbols. To create an alias, see the command `alias`.";
                descriptor.Example = @"    >>> aliases
    # Builtin Aliases
    alias(alpha, Α, α)
    alias(beta, Β, β)
    alias(chi, Χ, χ)
    alias(delta, Δ, δ)
    alias(epsilon, Ε, ε)
    alias(eta, Η, η)
    alias(gamma, Γ, γ)
    alias(iota, Ι, ι)
    alias(kappa, Κ, κ)
    alias(lambda, Λ, λ)
    alias(mu, Μ, μ)
    alias(nu, Ν, ν)
    alias(omega, Ω, ω)
    alias(omicron, Ο, ο)
    alias(phi, Φ, φ, ϕ)
    alias(pi, Π, π)
    alias(psi, Ψ, ψ)
    alias(rho, Ρ, ρ)
    alias(sigma, Σ, σ)
    alias(tau, Τ, τ)
    alias(theta, Θ, θ, ϑ)
    alias(upsilon, Υ, υ)
    alias(xi, Ξ, ξ)
    alias(zeta, Ζ, ζ)
";
            }
            {
                var descriptor = Descriptors["shortcuts"];
                descriptor.Category = "General";
                descriptor.Description = @"Displays all built-in and user-defined keyboard shortcuts.";
                descriptor.IsCommand = false;
                descriptor.Remarks = @"To create an keyboard shortcut, see the command `shortcut`.";
                descriptor.Example = @"    >>> clear shortcuts
    >>> shortcut(tester, ""ctrl+d"", '""' + date + '""')
    >>> shortcuts
    # User-defined Shortcuts
    shortcut(tester, ""ctrl+d"", '""' + date + '""')                 # ctrl+d => '""' + date + '""'
";
            }
            {
                var descriptor = Descriptors["action"];
                descriptor.Category = "General";
                descriptor.Description = @"Creates an action for the command line editor experience related to
     cursor/text manipulation. This action can then be used by the `shortcut` command.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("action", @"The name of the action to create. This name must be
    
     {.table}
     | Action                | Description               |
     |-----------------------|---------------------------|
     | `cursor_left`         | Move the cursor to the left
     | `cursor_right`        | Move the cursor to the right
     | `history_previous`    | Bring the previous command from the history
     | `history_next`        | Bring the next command from the history
     | `copy`                | Copy the selection to the clipboard 
     | `cut`                 | Cut the selection to the clipboard 
     | `paste`               | Paste the content of the clipboard at the position of the cursor
     | `cursor_word_left`    | Move the cursor to the left by one word boundary
     | `cursor_word_right`   | Move the cursor to the right by one word boundary
     | `cursor_line_start`   | Move the cursor to the beginning of the line
     | `cursor_line_end`     | Move the cursor to the end of the line
     | `completion`          | Trigger a completion at the cursor's position
     | `delete_left`         | Delete the character to the left of the cursor
     | `delete_right`        | Delete the character to the right of the cursor
     | `delete_word_left`    | Delete a word to the left of the cursor
     | `delete_word_right`   | Delete a word to the right of the cursor
     | `validate_line`       | Validate the current line
     | `force_validate_line` | Validate the current line and force a new line even in case of a syntax error
     | `exit`                | Exit the program
     | `copy`                | Copy the content of the selection to the clipboard or if there is no selection, exit the program")  { IsOptional = false });
                descriptor.Returns = @"An action object.";
                descriptor.Remarks = @"This function is not meant to be used directly but in conjunction with the `shortcut` command.";
                descriptor.Example = @"     >>> shortcut(cursor_left, ""left, ctrl+b"", action(""cursor_left""))
";
            }
            {
                var descriptor = Descriptors["license"];
                descriptor.Category = "General";
                descriptor.Description = @"Displays the license";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["clipboard"];
                descriptor.Category = "General";
                descriptor.Description = @"Gets or sets the current content of the clipboard.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"Value to set the clipboard to. If not set, this function returns the current content of the clipboard.")  { IsOptional = true });
                descriptor.Returns = @"Returns the content of the clipboard.";
                descriptor.Remarks = @"On Unix platform, if you are running from WSL or from raw console, the clipboard is not supported.";
                descriptor.Example = @"    >>> clipboard ""text""
    # clipboard(""text"")
    out = ""text""
    >>> clipboard
    # clipboard
    out = ""text""
";
            }
            {
                var descriptor = Descriptors["display"];
                descriptor.Category = "General";
                descriptor.Description = @"Gets or sets the display mode.
    
     - `raw` for raw mode, where integers are displayed as raw integers.
     - `std` for standard mode, integers are displayed with _ separator every 3 digits. This is the default.
     - `dev` for developer mode to display advanced details about integers, vectors and floating point values.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("name", @"An optional parameter to set the display mode. Default is `std`. If this parameter is not set, this function will display the display mode currently used.")  { IsOptional = true });
                descriptor.Example = @"     >>> display
     # Display mode: std (Standard)
     >>> display dev
     # Display mode: dev (Developer)
     >>> 1.5
     # 1.5
     out = 1.5
         # IEEE 754 - double - 64-bit
         #
         = 0x_3FF80000_00000000
         = 0x____3____F____F____8____0____0____0____0____0____0____0____0____0____0____0____0
         #    seee eeee eeee ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff ffff
         = 0b_0011_1111_1111_1000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000_0000
         #   63                48                  32                  16                   0
         #
         # sign    exponent              |-------------------- fraction --------------------|
         =   1 * 2 ^ (1023 - 1023) * 0b1.1000000000000000000000000000000000000000000000000000
     >>> display invalid
     Invalid display name `invalid`. Expecting `std`, `dev` or `raw`. (Parameter 'name')
";
            }
            {
                var descriptor = Descriptors["echo"];
                descriptor.Category = "General";
                descriptor.Description = @"Gets or sets the current echo mode.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"An optional `true`/`on` or `false`/`off` value to enable or disable the echo. A value of `false` will disable any output generated by a command except for the print commands. If this parameter is not set, this function will display the current display mode.")  { IsOptional = true });
                descriptor.Example = @"    >>> echo
    # Echo is on.
    >>> 1 + 2
    # 1 + 2
    out = 3
    >>> echo off
    >>> 1 + 2
    >>> echo
    >>> echo on
    # Echo is on.
    >>> 1 + 2
    # 1 + 2
    out = 3
";
            }
            {
                var descriptor = Descriptors["print"];
                descriptor.Category = "General";
                descriptor.Description = @"Prints the specified value to the output.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"A value to print to the output.")  { IsOptional = false });
                descriptor.Remarks = @"When the `echo` is off, this method will still output.";
                descriptor.Example = @"    >>> print ""kalk""
    kalk
    >>> echo off
    >>> print ""kalk2""
    kalk2
";
            }
            {
                var descriptor = Descriptors["printf"];
                descriptor.Category = "General";
                descriptor.Description = @"Prints a formatted string where values to format are embraced by `{{` and `}}`.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"A template string to the output. Values to format must be embraced by `{{` and `}}`.")  { IsOptional = false });
                descriptor.Remarks = @"When the `echo` is off, this method will still output.";
                descriptor.Example = @"    >>> x = 1; y = ""yes""
    # x = 1; y = ""yes""
    x = 1
    y = ""yes""
    >>> printf ""Hello {{x}} World and {{y}}""
    Hello 1 World and yes
";
            }
            {
                var descriptor = Descriptors["sprintf"];
                descriptor.Category = "General";
                descriptor.Description = @"Formats a formatted string where values to format are embraced by `{{` and `}}`.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"A template string to the output. Values to format must be embraced by `{{` and `}}`.")  { IsOptional = false });
                descriptor.Returns = @"A string formatted with the specified embedded values.";
                descriptor.Example = @"    >>> x = 1; y = ""yes""
    # x = 1; y = ""yes""
    x = 1
    y = ""yes""
    >>> sprintf ""Hello {{x}} World and {{y}}""
    # sprintf(""Hello {{x}} World and {{y}}"")
    out = ""Hello 1 World and yes""
";
            }
            {
                var descriptor = Descriptors["printh"];
                descriptor.Category = "General";
                descriptor.Description = @"Prints the specified value to the output formatted with kalk syntax highlighting.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"A value to print to the output.")  { IsOptional = false });
                descriptor.Remarks = @"When the `echo` is off, this method will still output.";
                descriptor.Example = @"    >>> printh ""# This is a kalk comment""
    # This is a kalk comment
";
            }
            {
                var descriptor = Descriptors["help"];
                descriptor.Category = "General";
                descriptor.Description = @"Displays the documentation of the specified topic or function name.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("expression", @"An optional topic or function name. If this parameter is not set, it will display all available topics and functions.")  { IsOptional = true });
                descriptor.Example = @"    >>> help cls
    # cls
    #
    #   Clears the screen.
    #
    # Example
    .   >>> cls
";
            }
            {
                var descriptor = Descriptors["reset"];
                descriptor.Category = "General";
                descriptor.Description = @"Removes all user-defined variables and functions.";
                descriptor.IsCommand = true;
                descriptor.Example = @"    >>> x = 5; y = 2
    # x = 5; y = 2
    x = 5
    y = 2
    >>> list
    # Variables
    x = 5
    y = 2
    >>> reset
    >>> list
    # No variables
";
            }
            {
                var descriptor = Descriptors["version"];
                descriptor.Category = "General";
                descriptor.Description = @"Prints the version of kalk.";
                descriptor.IsCommand = true;
                descriptor.Example = @"    >>> version
    kalk 1.0.0 - Copyright (c) 2020 Alexandre Mutel
";
            }
            {
                var descriptor = Descriptors["list"];
                descriptor.Category = "General";
                descriptor.Description = @"Lists all user-defined variables and functions.";
                descriptor.IsCommand = true;
                descriptor.Example = @"    >>> x = 5; y = 2; f(x) = x + 5
    # x = 5; y = 2; f(x) = x + 5
    x = 5
    y = 2
     f(x) = x + 5
    >>> list
    # Variables
    x = 5
    y = 2
    # Functions
     f(x) = x + 5
";
            }
            {
                var descriptor = Descriptors["del"];
                descriptor.Category = "General";
                descriptor.Description = @"Deletes a user defined variable or function.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("variable", @"Name of the variable or function to delete.")  { IsOptional = false });
                descriptor.Example = @"    >>> x = 5; y = 2
    # x = 5; y = 2
    x = 5
    y = 2
    >>> del x
    # Variable `x == 5` deleted.
    >>> list
    # Variables
    y = 2
    >>> del y
    # Variable `y == 2` deleted.
    >>> f(x) = x + 5
    # f(x) = x + 5
    f(x) = x + 5
    >>> list
    # Functions
    f(x) = x + 5
    >>> del f
    # Function `f(x) = x + 5` deleted.
    >>> list
    # No variables
";
            }
            {
                var descriptor = Descriptors["exit"];
                descriptor.Category = "General";
                descriptor.Description = @"Exits kalk.";
                descriptor.IsCommand = true;
                descriptor.Example = @"    >>> exit
";
            }
            {
                var descriptor = Descriptors["history"];
                descriptor.Category = "General";
                descriptor.Description = @"Displays the command history.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("line", @"An optional parameter that indicates:
    
     - if it is >= 0, the index of the history command to re-run. (e.g `history 1` to re-run the command 1 in the history)
     - if it is < 0, how many recent lines to display. (e.g `history -3` would display the last 3 lines in the history)")  { IsOptional = true });
                descriptor.Example = @"     >>> 1 + 5
     # 1 + 5
     out = 6
     >>> abs(out)
     # abs(out)
     out = 6
     >>> history
     0: 1 + 5
     1: abs(out)
";
            }
            {
                var descriptor = Descriptors["eval"];
                descriptor.Category = "General";
                descriptor.Description = @"Evaluates dynamically the input string as an expression.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The text of the expression to evaluate.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("output", @"An optional parameter to output intermediate results of nested expressions. Default is `false`.")  { IsOptional = true });
                descriptor.Returns = @"The result of the evaluation.";
                descriptor.Example = @"    >>> eval ""1+5""
    # eval(""1+5"")
    out = 6
    >>> eval ""eval '1+5'""
    # eval(""eval '1+5'"")
    out = 6
";
            }
            {
                var descriptor = Descriptors["load"];
                descriptor.Category = "General";
                descriptor.Description = @"Loads and evaluates the specified script from a file location on a disk.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("path", @"The file location of the script to load and evaluate.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("output", @"An optional parameter to output intermediate results of nested expressions. Default is `false`.")  { IsOptional = true });
                descriptor.Returns = @"The result of the evaluation.";
                descriptor.Example = @"    >>> import Files
    # 14 functions successfully imported from module `Files`.
    >>> save_text(""x = 1\ny = 2\nx + y"", ""test.kalk"")
    >>> load ""test.kalk""
    # load(""test.kalk"")
    x = 1
    y = 2
    out = 3
";
            }
            {
                var descriptor = Descriptors["clear"];
                descriptor.Category = "General";
                descriptor.Description = @"Clears the screen (by default) or the history (e.g clear history).";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("what", @"An optional argument specifying what to clear. Can be of the following value:
    * screen: to clear the screen (default if not passed)
    * history: to clear the history
    * shortcuts: to clear all shortcuts defined. WARNING, clearing shortcuts is removing all common shortcuts, including basic navigation and edition mode!")  { IsOptional = true });
                descriptor.Example = @"    >>> 1 + 2
    # 1 + 2
    out = 3
    >>> history
    0: 1 + 2
    >>> clear history
    >>> history
    # History empty
";
            }
            {
                var descriptor = Descriptors["cls"];
                descriptor.Category = "General";
                descriptor.Description = @"Clears the screen.";
                descriptor.IsCommand = true;
                descriptor.Example = @"    >>> cls
";
            }
            {
                var descriptor = Descriptors["out"];
                descriptor.Category = "General";
                descriptor.Description = @"Returns the last evaluated result.";
                descriptor.IsCommand = false;
                descriptor.Returns = @"The last evaluated result as an object.";
                descriptor.Example = @"    >>> 1 + 2
    # 1 + 2
    out = 3
    >>> out + 1
    # out + 1
    out = 4
";
            }
            {
                var descriptor = Descriptors["out2clipboard"];
                descriptor.Category = "General";
                descriptor.Description = @"Copies the last evaluated content to the clipboard.
    
     This is equivalent to `out |> clipboard`.";
                descriptor.IsCommand = true;
                descriptor.Example = @"     >>> 1 + 2
     # 1 + 2
     out = 3
     >>> out2clipboard
     >>> clipboard
     # clipboard
     out = ""3""
";
            }
            {
                var descriptor = Descriptors["shortcut"];
                descriptor.Category = "General";
                descriptor.Description = @"Creates a keyboard shortcut associated with an expression or remove a keyboard shortcut.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("name", @"Name of the shortcut")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("shortcuts", @"A collection of pair of shortcut description (e.g `ctrl+a`) and associated shortcut expression (e.g `1 + 2`).")  { IsOptional = false });
                descriptor.Remarks = @"See the command `shortcuts` to list the shortcuts currently defined. By default several shortcuts for common mathematical symbols are defined (e.g for the symbol pi: `shortcut(pi, ""ctrl+g p"", ""Π"", ""ctrl+g p"", ""π"")`).
    
     If no shortcuts are associated to the name, the existing shortcuts for this name will be removed.";
                descriptor.Example = @"     >>> # Creates a shortcut that will print 3 when pressing ctrl+R.
     >>> shortcut(myshortcut, ""ctrl+g"", 1 + 2)
     >>> # Overrides the previous shortcut that will print the text
     >>> # `kalk` when pressing ctrl+g.
     >>> shortcut(myshortcut, ""ctrl+g"", ""kalk"")
     >>> # Overrides the previous shortcut that will print the text
     >>> # `kalk` when pressing ctrl+g or the text `kalk2` when pressing
     >>> # ctrl+e and r key.
     >>> shortcut(myshortcut, ""ctrl+g"", ""kalk"", ""ctrl+e r"", ""kalk2"")
     >>> # Remove the previous defined shortcuts
     >>> shortcut(myshortcut)
";
            }
            {
                var descriptor = Descriptors["alias"];
                descriptor.Category = "General";
                descriptor.Description = @"Creates an alias between variable names.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("name", @"Name of the original alias name.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("aliases", @"Variable names that are all equivalent to the alias name.")  { IsOptional = false });
                descriptor.Remarks = @"See the command `aliases` to list the aliases currently defined. Several aliases are defined by default for common mathematical symbols (e.g `alias(pi, Π, π)`).";
                descriptor.Example = @"    >>> alias(var1, var2, var3)
    >>> var1 = 2
    # var1 = 2
    var1 = 2
    >>> var2
    # var2
    out = 2
    >>> var3
    # var3
    out = 2
    >>> list
    # Variables
    var1 = 2
    >>> var2 = 1
    # var2 = 1
    var2 = 1
    >>> list
    # Variables
    var1 = 1
";
            }
            {
                var descriptor = Descriptors["kind"];
                descriptor.Category = "General";
                descriptor.Description = @"Gets the kind of a value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"A value to inspect the kind")  { IsOptional = false });
                descriptor.Example = @"    >>> kind 1
    # kind(1)
    out = ""int""
    >>> kind ""a""
    # kind(""a"")
    out = ""string""
    >>> kind byte (1)
    # kind(byte(1))
    out = ""byte""
    >>> kind []
    # kind([])
    out = ""array""
    >>> kind {}
    # kind({})
    out = ""object""
";
            }
            {
                var descriptor = Descriptors["units"];
                descriptor.Category = "Unit Functions";
                descriptor.Description = @"If used in an expression, returns an object containing all units defined.
    Otherwise it will display units in a friendly format.
    By default, no units are defined. You can define units by using the `unit` function
    and you can also import predefined units or currencies via `import StandardUnits` or
    `import Currencies`.";
                descriptor.IsCommand = false;
                descriptor.Example = @"    >>> unit(tomato, ""A tomato unit"", prefix: ""decimal"")
    # unit(tomato, ""A tomato unit"", prefix: ""decimal"")
    out = tomato
    >>> unit(ketchup, ""A ketchup unit"", kup, 5 tomato, prefix: ""decimal"")
    # unit(ketchup, ""A ketchup unit"", kup, 5 * tomato, prefix: ""decimal"")
    out = kup
    >>> units
    # User Defined Units
    unit(ketchup, ""A ketchup unit"", kup, 5 * tomato, prefix: ""decimal"")
      - yottaketchup/Ykup, zettaketchup/Zkup, exaketchup/Ekup, petaketchup/Pkup, teraketchup/Tkup,
        gigaketchup/Gkup, megaketchup/Mkup, kiloketchup/kkup, hectoketchup/hkup, decaketchup/dakup,
        deciketchup/dkup, centiketchup/ckup, milliketchup/mkup, microketchup/µkup, nanoketchup/nkup,
        picoketchup/pkup, femtoketchup/fkup, attoketchup/akup, zeptoketchup/zkup, yoctoketchup/ykup
    
    unit(tomato, ""A tomato unit"", tomato, prefix: ""decimal"")
      - yottatomato/Ytomato, zettatomato/Ztomato, exatomato/Etomato, petatomato/Ptomato,
        teratomato/Ttomato, gigatomato/Gtomato, megatomato/Mtomato, kilotomato/ktomato,
        hectotomato/htomato, decatomato/datomato, decitomato/dtomato, centitomato/ctomato,
        millitomato/mtomato, microtomato/µtomato, nanotomato/ntomato, picotomato/ptomato,
        femtotomato/ftomato, attotomato/atomato, zeptotomato/ztomato, yoctotomato/ytomato
";
            }
            {
                var descriptor = Descriptors["to"];
                descriptor.Category = "Unit Functions";
                descriptor.Description = @"Converts from one value unit to a destination unit.
    
     The pipe operator |> can be used between the src and destination unit to make it
     more readable. Example: `105 g |> to kg`";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("src", @"The source value with units.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("dst", @"The destination unit.")  { IsOptional = false });
                descriptor.Returns = @"The result of the calculation.";
                descriptor.Example = @"     >>> import StandardUnits
     # 1294 units successfully imported from module `StandardUnits`.
     >>> 10 kg/s |> to kg/h
     # ((10 * kg) / s) |> to(kg / h)
     out = 36000 * kg / h
     >>> 50 kg/m |> to g/km
     # ((50 * kg) / m) |> to(g / km)
     out = 50000000 * g / km
";
            }
            {
                var descriptor = Descriptors["unit"];
                descriptor.Category = "Unit Functions";
                descriptor.Description = @"Defines a unit with the specified name and characteristics.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("name", @"Long name of the unit.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("description", @"A description of the unit. This value is optional.")  { IsOptional = true });
                descriptor.Params.Add(new KalkParamDescriptor("symbol", @"Short name (symbol) of the unit. This value is optional.")  { IsOptional = true });
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The expression value of this unit. This value is optional.")  { IsOptional = true });
                descriptor.Params.Add(new KalkParamDescriptor("plural", @"The plural name of this unit. This value is optional.")  { IsOptional = true });
                descriptor.Params.Add(new KalkParamDescriptor("prefix", @"A comma list separated of prefix kinds:
    - ""decimal"": Defines the twenty prefixes for the International System of Units (SI). Example: Yotta/Y, kilo/k, milli/m...
    - ""binary"": Defines the binary prefixes. See https://en.wikipedia.org/wiki/Binary_prefix. Example: kibbi/Ki, mebi/Mi...
    - Individual prefixes:
      Decimal prefixes:
      - `Y` - `Yotta` (10^24)
      - `Z` - `Zetta` (10^21)
      - `E` - `Exa` (10^18)
      - `P` - `Peta` (10^15)
      - `T` - `Tera` (10^12)
      - `G` - `Giga` (10^9)
      - `M` - `Mega` (10^6)
      - `k` - `kilo` (10^3)
      - `h` - `hecto` (10^2)
      - `da` - `deca` (10^1)
      - `d` - `deci` (10^)-1
      - `c` - `centi` (10^)-2
      - `m` - `milli` (10^)-3
      - `µ` - `micro` (10^-6)
      - `n` - `nano` (10^)-9
      - `p` - `pico` (10^)-12
      - `f` - `femto` (10^)-15
      - `a` - `atto` (10^)-18
      - `z` - `zepto` (10^)-21
      - `y` - `yocto` (10^)-24
      
      Binary prefixes:
      - `Ki` - `Kibi` (2^10)
      - `Mi` - `Mibi` (2^20)
      - `Gi` - `Gibi` (2^30)
      - `Ti` - `Tibi` (2^40)
      - `Pi` - `Pibi` (2^50)
      - `Ei` - `Eibi` (2^60)
      - `Zi` - `Zibi` (2^70)
      - `Yi` - `Yibi` (2^80)")  { IsOptional = true });
                descriptor.Returns = @"The associated unit object.";
                descriptor.Example = @"    >>> unit(tomato, ""A tomato unit"", prefix: ""decimal"")
    # unit(tomato, ""A tomato unit"", prefix: ""decimal"")
    out = tomato
    >>> unit(ketchup, ""A ketchup unit"", kup, 5 tomato, prefix: ""decimal"")
    # unit(ketchup, ""A ketchup unit"", kup, 5 * tomato, prefix: ""decimal"")
    out = kup
    >>> 4 kup
    # 4 * kup
    out = 20 * tomato
    >>> tomato
    unit(tomato, ""A tomato unit"", tomato, prefix: ""decimal"")
      - yottatomato/Ytomato, zettatomato/Ztomato, exatomato/Etomato, petatomato/Ptomato, 
        teratomato/Ttomato, gigatomato/Gtomato, megatomato/Mtomato, kilotomato/ktomato, 
        hectotomato/htomato, decatomato/datomato, decitomato/dtomato, centitomato/ctomato, 
        millitomato/mtomato, microtomato/µtomato, nanotomato/ntomato, picotomato/ptomato, 
        femtotomato/ftomato, attotomato/atomato, zeptotomato/ztomato, yoctotomato/ytomato
    >>> ketchup
    unit(ketchup, ""A ketchup unit"", kup, 5 * tomato, prefix: ""decimal"")
      - yottaketchup/Ykup, zettaketchup/Zkup, exaketchup/Ekup, petaketchup/Pkup, teraketchup/Tkup, 
        gigaketchup/Gkup, megaketchup/Mkup, kiloketchup/kkup, hectoketchup/hkup, decaketchup/dakup, 
        deciketchup/dkup, centiketchup/ckup, milliketchup/mkup, microketchup/µkup, nanoketchup/nkup, 
        picoketchup/pkup, femtoketchup/fkup, attoketchup/akup, zeptoketchup/zkup, yoctoketchup/ykup
";
            }
        }        
    }
}
namespace Kalk.Core
{
    public partial class MathModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterConstant("nan", Nan);
            RegisterConstant("inf", Inf);
            RegisterConstant("pi", Pi);
            RegisterConstant("e", E);
            RegisterFunction("fib", (Func<Kalk.Core.KalkIntValue, object>)Fib);
            RegisterFunction("i", (Func<object>)ComplexNumber);
            RegisterFunction("all", (Func<object, Kalk.Core.KalkBool>)All);
            RegisterFunction("any", (Func<object, Kalk.Core.KalkBool>)Any);
            RegisterFunction("abs", (Func<Kalk.Core.KalkCompositeValue, object>)Abs);
            RegisterFunction("rnd", (Func<Kalk.Core.KalkCompositeValue, object>)Rnd);
            RegisterAction("seed", (Action<int?>)Seed);
            RegisterFunction("modf", (Func<Kalk.Core.KalkCompositeValue, Scriban.Runtime.ScriptArray>)Modf);
            RegisterFunction("radians", (Func<Kalk.Core.KalkCompositeValue, object>)Radians);
            RegisterFunction("degrees", (Func<Kalk.Core.KalkCompositeValue, object>)Degrees);
            RegisterFunction("sign", (Func<Kalk.Core.KalkCompositeValue, object>)Sign);
            RegisterFunction("cos", (Func<Kalk.Core.KalkDoubleValue, object>)Cos);
            RegisterFunction("acos", (Func<Kalk.Core.KalkDoubleValue, object>)Acos);
            RegisterFunction("cosh", (Func<Kalk.Core.KalkDoubleValue, object>)Cosh);
            RegisterFunction("acosh", (Func<Kalk.Core.KalkDoubleValue, object>)Acosh);
            RegisterFunction("sin", (Func<Kalk.Core.KalkDoubleValue, object>)Sin);
            RegisterFunction("asin", (Func<Kalk.Core.KalkDoubleValue, object>)Asin);
            RegisterFunction("sinh", (Func<Kalk.Core.KalkDoubleValue, object>)Sinh);
            RegisterFunction("asinh", (Func<Kalk.Core.KalkDoubleValue, object>)Asinh);
            RegisterFunction("tan", (Func<Kalk.Core.KalkDoubleValue, object>)Tan);
            RegisterFunction("atan", (Func<Kalk.Core.KalkDoubleValue, object>)Atan);
            RegisterFunction("tanh", (Func<Kalk.Core.KalkDoubleValue, object>)Tanh);
            RegisterFunction("atanh", (Func<Kalk.Core.KalkDoubleValue, object>)Atanh);
            RegisterFunction("atan2", (Func<Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, object>)Atan2);
            RegisterFunction("fmod", (Func<Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, object>)Fmod);
            RegisterFunction("frac", (Func<Kalk.Core.KalkDoubleValue, object>)Frac);
            RegisterFunction("rsqrt", (Func<Kalk.Core.KalkDoubleValue, object>)Rsqrt);
            RegisterFunction("sqrt", (Func<Kalk.Core.KalkDoubleValue, object>)Sqrt);
            RegisterFunction("log", (Func<Kalk.Core.KalkDoubleValue, object>)Log);
            RegisterFunction("log2", (Func<Kalk.Core.KalkDoubleValue, object>)Log2);
            RegisterFunction("log10", (Func<Kalk.Core.KalkDoubleValue, object>)Log10);
            RegisterFunction("exp", (Func<Kalk.Core.KalkDoubleValue, object>)Exp);
            RegisterFunction("exp2", (Func<Kalk.Core.KalkDoubleValue, object>)Exp2);
            RegisterFunction("pow", (Func<Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, object>)Pow);
            RegisterFunction("round", (Func<Kalk.Core.KalkDoubleValue, object>)Round);
            RegisterFunction("floor", (Func<Kalk.Core.KalkDoubleValue, object>)Floor);
            RegisterFunction("ceil", (Func<Kalk.Core.KalkDoubleValue, object>)Ceiling);
            RegisterFunction("trunc", (Func<Kalk.Core.KalkDoubleValue, object>)Trunc);
            RegisterFunction("saturate", (Func<Kalk.Core.KalkDoubleValue, object>)Saturate);
            RegisterFunction("min", (Func<Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, object>)Min);
            RegisterFunction("max", (Func<Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, object>)Max);
            RegisterFunction("step", (Func<Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, object>)Step);
            RegisterFunction("smoothstep", (Func<Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, object>)Smoothstep);
            RegisterFunction("lerp", (Func<Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, object>)Lerp);
            RegisterFunction("clamp", (Func<Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, Kalk.Core.KalkDoubleValue, object>)Clamp);
            RegisterFunction("real", (Func<Kalk.Core.KalkComplex, double>)Real);
            RegisterFunction("imag", (Func<Kalk.Core.KalkComplex, double>)Imag);
            RegisterFunction("phase", (Func<Kalk.Core.KalkComplex, double>)Phase);
            RegisterFunction("isfinite", (Func<Kalk.Core.KalkCompositeValue, object>)IsFinite);
            RegisterFunction("isinf", (Func<Kalk.Core.KalkCompositeValue, object>)IsInf);
            RegisterFunction("isnan", (Func<Kalk.Core.KalkCompositeValue, object>)IsNan);
            RegisterFunction("sum", (Func<object, object[], object>)Sum);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["nan"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Defines the ""Not a Number"" constant for a double.";
                descriptor.IsCommand = false;
                descriptor.Example = @"    >>> nan
    # nan
    out = nan
";
            }
            {
                var descriptor = Descriptors["inf"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Defines the infinity constant for a double.";
                descriptor.IsCommand = false;
                descriptor.Example = @"    >>> inf
    # inf
    out = inf
";
            }
            {
                var descriptor = Descriptors["pi"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Defines the PI constant. pi = 3.14159265358979";
                descriptor.IsCommand = false;
                descriptor.Example = @"    >>> pi
    # pi
    out = 3.141592653589793
";
            }
            {
                var descriptor = Descriptors["e"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Defines the natural logarithmic base. e = 2.71828182845905";
                descriptor.IsCommand = false;
                descriptor.Example = @"    >>> e
    # e
    out = 2.718281828459045
";
            }
            {
                var descriptor = Descriptors["fib"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Calculates the fibonacci number for the specified input.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The input number.")  { IsOptional = false });
                descriptor.Returns = @"The fibonacci number.";
                descriptor.Example = @"    >>> fib 50
    # fib(50)
    out = 12_586_269_025
";
            }
            {
                var descriptor = Descriptors["i"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Defines the imaginary part of a complex number.";
                descriptor.IsCommand = false;
                descriptor.Returns = @"A complex number.";
                descriptor.Example = @"    >>> 1 + 2i
    # 1 + 2 * i
    out = 1 + 2i
";
            }
            {
                var descriptor = Descriptors["all"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Determines if all components of the specified value are non-zero.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"true if all components of the x parameter are non-zero; otherwise, false.";
                descriptor.Remarks = @"This function is similar to the `any` function.
    The `any` function determines if any components of the specified value are non-zero, while the `all` function determines if all components of the specified value are non-zero.";
                descriptor.Example = @"    >>> all(bool4(true, false, true, false))
    # all(bool4(true, false, true, false))
    out = false
    >>> all(bool4(true, true, true, true))
    # all(bool4(true, true, true, true))
    out = true
    >>> all([0,1,0,2])
    # all([0,1,0,2])
    out = false
    >>> all([1,1,1,1])
    # all([1,1,1,1])
    out = true
";
            }
            {
                var descriptor = Descriptors["any"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Determines if any components of the specified value are non-zero.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"true if any components of the x parameter are non-zero; otherwise, false.";
                descriptor.Remarks = @"This function is similar to the `all` intrinsic function.
    The `any` function determines if any components of the specified value are non-zero,
    while the `all` function determines if all components of the specified value are non-zero.";
                descriptor.Example = @"    >>> any(bool4(true, false, true, false))
    # any(bool4(true, false, true, false))
    out = true
    >>> any(bool4(false, false, false, false))
    # any(bool4(false, false, false, false))
    out = false
    >>> any([0,1,0,2])
    # any([0,1,0,2])
    out = true
    >>> any([0,0,0,0])
    # any([0,0,0,0])
    out = false
";
            }
            {
                var descriptor = Descriptors["abs"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the absolute value of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The absolute value of the x parameter.";
                descriptor.Example = @"    >>> abs(-1)
    # abs(-1)
    out = 1
    >>> abs(float4(-1, 1, -2, -3))
    # abs(float4(-1, 1, -2, -3))
    out = float4(1, 1, 2, 3)
";
            }
            {
                var descriptor = Descriptors["rnd"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns a random value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"A value to create random values for.")  { IsOptional = true });
                descriptor.Returns = @"A random value or a random value of the x parameter.";
                descriptor.Example = @"    >>> seed(0); rnd
    # seed(0); rnd
    out = 0.7262432699679598
    >>> rnd
    # rnd
    out = 0.8173253595909687
    >>> rnd(float4)
    # rnd(float4)
    out = float4(0.7680227, 0.5581612, 0.20603316, 0.5588848)
";
            }
            {
                var descriptor = Descriptors["seed"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Setup the seed function for rnd. The default seed is random.";
                descriptor.IsCommand = true;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"An original seed value for the `rnd` function.")  { IsOptional = true });
                descriptor.Remarks = @"The x is not specified, it will generate a random seed automatically.";
                descriptor.Example = @"    >>> seed(0); rnd
    # seed(0); rnd
    out = 0.7262432699679598
    >>> seed(1); rnd
    # seed(1); rnd
    out = 0.24866858415709278
";
            }
            {
                var descriptor = Descriptors["modf"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Splits the value x into fractional and integer parts, each of which has the same sign as x.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The input value.")  { IsOptional = false });
                descriptor.Returns = @"The signed-fractional portion of x.";
                descriptor.Example = @"    >>> modf(1.5)
    # modf(1.5)
    out = [1, 0.5]
    >>> modf(float2(-1.2, 3.4))
    # modf(float2(-1.2, 3.4))
    out = [float2(-1, 3), float2(-0.20000005, 0.4000001)]
";
            }
            {
                var descriptor = Descriptors["radians"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Converts the specified value from degrees to radians.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value in degrees.")  { IsOptional = false });
                descriptor.Returns = @"The x parameter converted from degrees to radians.";
                descriptor.Example = @"    >>> radians(90)
    # radians(90)
    out = 1.5707963267948966
    >>> radians(180)
    # radians(180)
    out = 3.141592653589793
";
            }
            {
                var descriptor = Descriptors["degrees"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Converts the specified value from radians to degrees.";
                descriptor.IsCommand = false;
                descriptor.Returns = @"The x parameter converted from radians to degrees.";
                descriptor.Example = @"    >>> degrees(pi/2)
    # degrees(pi / 2)
    out = 90
    >>> degrees(pi)
    # degrees(pi)
    out = 180
";
            }
            {
                var descriptor = Descriptors["sign"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns an integer that indicates the sign of a number.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"A signed number.")  { IsOptional = false });
                descriptor.Returns = @"A number that indicates the sign of x:
     - -1 if x is less than zero
     - 0 if x is equal to zero
     - 1 if x is greater than zero.";
                descriptor.Example = @"    >>> sign(-5); sign(0); sign(2.3)
    # sign(-5); sign(0); sign(2.3)
    out = -1
    out = 0
    out = 1
    >>> sign float4(-1, 2, 0, 1.5)
    # sign(float4(-1, 2, 0, 1.5))
    out = float4(-1, 1, 0, 1)
";
            }
            {
                var descriptor = Descriptors["cos"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the cosine of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value, in radians.")  { IsOptional = false });
                descriptor.Returns = @"The cosine of the x parameter.";
                descriptor.Example = @"    >>> cos 0.5
    # cos(0.5)
    out = 0.8775825618903728
    >>> cos float4(pi, pi/2, 0, 0.5)
    # cos(float4(pi, pi / 2, 0, 0.5))
    out = float4(-1, -4.371139E-08, 1, 0.87758255)
";
            }
            {
                var descriptor = Descriptors["acos"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the arccosine of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value. Each component should be a floating-point value within the range of -1 to 1.")  { IsOptional = false });
                descriptor.Returns = @"The arccosine of the x parameter.";
                descriptor.Example = @"    >>> acos(-1)
    # acos(-1)
    out = 3.141592653589793
    >>> acos(0)
    # acos(0)
    out = 1.5707963267948966
    >>> acos(1)
    # acos(1)
    out = 0
    >>> acos(float4(-1,0,1,0.5))
    # acos(float4(-1, 0, 1, 0.5))
    out = float4(3.1415927, 1.5707964, 0, 1.0471976)
";
            }
            {
                var descriptor = Descriptors["cosh"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the hyperbolic cosine of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value, in radians.")  { IsOptional = false });
                descriptor.Returns = @"The hyperbolic cosine of the x parameter.";
                descriptor.Example = @"    >>> cosh(-1)
    # cosh(-1)
    out = 1.5430806348152437
    >>> cosh(1)
    # cosh(1)
    out = 1.5430806348152437
    >>> cosh(0)
    # cosh(0)
    out = 1
    >>> cosh(float4(-1, 1, 0, 2))
    # cosh(float4(-1, 1, 0, 2))
    out = float4(1.5430807, 1.5430807, 1, 3.7621956)
";
            }
            {
                var descriptor = Descriptors["acosh"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the inverse hyperbolic cosine of a number. The number must be greater than or equal to 1.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"Any real number equal to or greater than 1.")  { IsOptional = false });
                descriptor.Returns = @"The inverse hyperbolic cosine of the x parameter";
                descriptor.Example = @"    >>> acosh(1)
    # acosh(1)
    out = 0
    >>> acosh(10)
    # acosh(10)
    out = 2.993222846126381
    >>> acosh(float4(1,2,4,10))
    # acosh(float4(1, 2, 4, 10))
    out = float4(0, 1.316958, 2.063437, 2.993223)
";
            }
            {
                var descriptor = Descriptors["sin"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the sine of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value, in radians.")  { IsOptional = false });
                descriptor.Returns = @"The sine of the x parameter.";
                descriptor.Example = @"    >>> sin 0.5
    # sin(0.5)
    out = 0.479425538604203
    >>> sin float4(pi, pi/2, 0, 0.5)
    # sin(float4(pi, pi / 2, 0, 0.5))
    out = float4(-8.742278E-08, 1, 0, 0.47942555)
";
            }
            {
                var descriptor = Descriptors["asin"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the arcsine of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value. Each component of the x parameter should be within the range of -π/2 to π/2.")  { IsOptional = false });
                descriptor.Returns = @"The arcsine of the x parameter.";
                descriptor.Example = @"    >>> asin 0.5
    # asin(0.5)
    out = 0.5235987755982989
    >>> asin float4(-1, 0, 1, 0.5)
    # asin(float4(-1, 0, 1, 0.5))
    out = float4(-1.5707964, 0, 1.5707964, 0.5235988)
";
            }
            {
                var descriptor = Descriptors["sinh"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the hyperbolic sine of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value, in radians.")  { IsOptional = false });
                descriptor.Returns = @"The hyperbolic sine of the x parameter.";
                descriptor.Example = @"    >>> sinh(-1)
    # sinh(-1)
    out = -1.1752011936438014
    >>> sinh(0)
    # sinh(0)
    out = 0
    >>> sinh(1)
    # sinh(1)
    out = 1.1752011936438014
    >>> sinh(float4(-1, 1, 0, 2))
    # sinh(float4(-1, 1, 0, 2))
    out = float4(-1.1752012, 1.1752012, 0, 3.6268604)
";
            }
            {
                var descriptor = Descriptors["asinh"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the inverse hyperbolic sine of a number.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The inverse hyperbolic sine of the x parameter.";
                descriptor.Example = @"    >>> asinh(-1.1752011936438014)
    # asinh(-1.1752011936438014)
    out = -1
    >>> asinh(0)
    # asinh(0)
    out = 0
    >>> asinh(1.1752011936438014)
    # asinh(1.1752011936438014)
    out = 1
    >>> asinh(float4(-1.1752011936438014, 0, 1.1752011936438014, 2))
    # asinh(float4(-1.1752011936438014, 0, 1.1752011936438014, 2))
    out = float4(-1, 0, 1, 1.4436355)
";
            }
            {
                var descriptor = Descriptors["tan"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the tangent of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value, in radians.")  { IsOptional = false });
                descriptor.Returns = @"The tangent of the x parameter.";
                descriptor.Example = @"    >>> tan(0.5)
    # tan(0.5)
    out = 0.5463024898437905
    >>> tan(1)
    # tan(1)
    out = 1.5574077246549023
    >>> tan float4(1, 2, 3, 4)
    # tan(float4(1, 2, 3, 4))
    out = float4(1.5574077, -2.1850398, -0.14254655, 1.1578213)
";
            }
            {
                var descriptor = Descriptors["atan"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the arctangent of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The arctangent of the x parameter. This value is within the range of -π/2 to π/2.";
                descriptor.Example = @"    >>> atan(0.5)
    # atan(0.5)
    out = 0.4636476090008061
    >>> atan(1)
    # atan(1)
    out = 0.7853981633974483
    >>> atan(0)
    # atan(0)
    out = 0
    >>> atan(float4(0,1,2,3))
    # atan(float4(0, 1, 2, 3))
    out = float4(0, 0.7853982, 1.1071488, 1.2490457)
";
            }
            {
                var descriptor = Descriptors["tanh"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the hyperbolic tangent of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value, in radians.")  { IsOptional = false });
                descriptor.Returns = @"The hyperbolic tangent of the x parameter.";
                descriptor.Example = @"    >>> tanh(0)
    # tanh(0)
    out = 0
    >>> tanh(1)
    # tanh(1)
    out = 0.7615941559557649
    >>> tanh(2)
    # tanh(2)
    out = 0.9640275800758169
    >>> tanh(float4(0, 1, 2, 3))
    # tanh(float4(0, 1, 2, 3))
    out = float4(0, 0.7615942, 0.9640276, 0.9950548)
";
            }
            {
                var descriptor = Descriptors["atanh"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the inverse hyperbolic tangent of a number.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value. Number must be between -1 and 1 (excluding -1 and 1).")  { IsOptional = false });
                descriptor.Returns = @"The inverse hyperbolic tangent of the x parameter";
                descriptor.Example = @"    >>> atanh(0)
    # atanh(0)
    out = 0
    >>> atanh(0.5)
    # atanh(0.5)
    out = 0.5493061443340549
    >>> atanh(float4(-0.5, 0, 0.5, 0.8))
    # atanh(float4(-0.5, 0, 0.5, 0.8))
    out = float4(-0.54930615, 0, 0.54930615, 1.0986123)
";
            }
            {
                var descriptor = Descriptors["atan2"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the arctangent of two values (x,y).";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("y", @"The y value.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The x value.")  { IsOptional = false });
                descriptor.Returns = @"The arctangent of (y,x).";
                descriptor.Remarks = @"The signs of the x and y parameters are used to determine the quadrant of the return values within the range of -π to π. The `atan2` function is well-defined for every point other than the origin, even if y equals 0 and x does not equal 0.";
                descriptor.Example = @"    >>> atan2(1,1)
    # atan2(1, 1)
    out = 0.7853981633974483
    >>> atan2(1,0)
    # atan2(1, 0)
    out = 1.5707963267948966
    >>> atan2(0,1)
    # atan2(0, 1)
    out = 0
    >>> atan2(float4(1), float4(0,1,-1,2))
    # atan2(float4(1), float4(0, 1, -1, 2))
    out = float4(1.5707964, 0.7853982, 2.3561945, 0.4636476)
";
            }
            {
                var descriptor = Descriptors["fmod"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the floating-point remainder of x/y.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The floating-point dividend.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("y", @"The floating-point divisor.")  { IsOptional = false });
                descriptor.Returns = @"The floating-point remainder of the x parameter divided by the y parameter.";
                descriptor.Remarks = @"The floating-point remainder is calculated such that x = i * y + f, where i is an integer, f has the same sign as x, and the absolute value of f is less than the absolute value of y.";
                descriptor.Example = @"    >>> fmod(2.5, 2)
    # fmod(2.5, 2)
    out = 0.5
    >>> fmod(2.5, 3)
    # fmod(2.5, 3)
    out = 2.5
    >>> fmod(-1.5, 1)
    # fmod(-1.5, 1)
    out = -0.5
    >>> fmod(float4(1.5, 1.2, -2.3, -4.6), 0.2)
    # fmod(float4(1.5, 1.2, -2.3, -4.6), 0.2)
    out = float4(0.09999998, 2.9802322E-08, -0.09999992, -0.19999984)
";
            }
            {
                var descriptor = Descriptors["frac"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the fractional (or decimal) part of x; which is greater than or equal to 0 and less than 1.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The fractional part of the x parameter.";
                descriptor.Example = @"    >>> frac(1.25)
    # frac(1.25)
    out = 0.25
    >>> frac(10.5)
    # frac(10.5)
    out = 0.5
    >>> frac(-1.75)
    # frac(-1.75)
    out = 0.25
    >>> frac(-10.25)
    # frac(-10.25)
    out = 0.75
    >>> frac(float4(1.25, 10.5, -1.75, -10.25))
    # frac(float4(1.25, 10.5, -1.75, -10.25))
    out = float4(0.25, 0.5, 0.25, 0.75)
";
            }
            {
                var descriptor = Descriptors["rsqrt"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the reciprocal of the square root of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The reciprocal of the square root of the x parameter.";
                descriptor.Remarks = @"This function uses the following formula: 1 / sqrt(x).";
                descriptor.Example = @"    >>> rsqrt(1)
    # rsqrt(1)
    out = 1
    >>> rsqrt(2)
    # rsqrt(2)
    out = 0.7071067811865475
    >>> rsqrt(float4(1,2,3,4))
    # rsqrt(float4(1, 2, 3, 4))
    out = float4(1, 0.70710677, 0.57735026, 0.5)
";
            }
            {
                var descriptor = Descriptors["sqrt"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the square root of the specified floating-point value, per component.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified floating-point value.")  { IsOptional = false });
                descriptor.Returns = @"The square root of the x parameter, per component.";
                descriptor.Example = @"    >>> sqrt(1)
    # sqrt(1)
    out = 1
    >>> sqrt(2)
    # sqrt(2)
    out = 1.4142135623730951
    >>> sqrt(float4(1,2,3,4))
    # sqrt(float4(1, 2, 3, 4))
    out = float4(1, 1.4142135, 1.7320508, 2)
";
            }
            {
                var descriptor = Descriptors["log"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the base-e logarithm of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The base-e logarithm of the x parameter. If the x parameter is negative, this function returns indefinite. If the x parameter is 0, this function returns `-inf`.";
                descriptor.Example = @"    >>> log 1
    # log(1)
    out = 0
    >>> log 2
    # log(2)
    out = 0.6931471805599453
    >>> log 0
    # log(0)
    out = -inf
    >>> log float4(0,1,2,3)
    # log(float4(0, 1, 2, 3))
    out = float4(-inf, 0, 0.6931472, 1.0986123)
";
            }
            {
                var descriptor = Descriptors["log2"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the base-2 logarithm of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The base-2 logarithm of the x parameter. If the x parameter is negative, this function returns indefinite. If the x parameter is 0, this function returns -inf.";
                descriptor.Example = @"    >>> log2 0
    # log2(0)
    out = -inf
    >>> log2 8
    # log2(8)
    out = 3
    >>> log2 129
    # log2(129)
    out = 7.011227255423254
    >>> log2 float4(0, 2, 16, 257)
    # log2(float4(0, 2, 16, 257))
    out = float4(-inf, 1, 4, 8.005625)
";
            }
            {
                var descriptor = Descriptors["log10"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the base-10 logarithm of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The base-10 logarithm of the x parameter. If the x parameter is negative, this function returns indefinite. If the x is 0, this function returns -inf.";
                descriptor.Example = @"    >>> log10 0
    # log10(0)
    out = -inf
    >>> log10 10
    # log10(10)
    out = 1
    >>> log10 100
    # log10(100)
    out = 2
    >>> log10 1001
    # log10(1001)
    out = 3.000434077479319
    >>> log10(float4(0,10,100,1001))
    # log10(float4(0, 10, 100, 1001))
    out = float4(-inf, 1, 2, 3.0004342)
";
            }
            {
                var descriptor = Descriptors["exp"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the base-e exponential, or e^x, of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The base-e exponential of the x parameter.";
                descriptor.Example = @"    >>> exp(0)
    # exp(0)
    out = 1
    >>> exp(1)
    # exp(1)
    out = 2.718281828459045
    >>> exp(float4(0,1,2,3))
    # exp(float4(0, 1, 2, 3))
    out = float4(1, 2.7182817, 7.389056, 20.085537)
";
            }
            {
                var descriptor = Descriptors["exp2"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the base 2 exponential, or 2^x, of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The base-2 exponential of the x parameter.";
                descriptor.Example = @"    >>> exp2(0)
    # exp2(0)
    out = 1
    >>> exp2(1)
    # exp2(1)
    out = 2
    >>> exp2(4)
    # exp2(4)
    out = 16
    >>> exp2(float4(0,1,2,3))
    # exp2(float4(0, 1, 2, 3))
    out = float4(1, 2, 4, 8)
";
            }
            {
                var descriptor = Descriptors["pow"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the specified value raised to the specified power.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("y", @"The specified power.")  { IsOptional = false });
                descriptor.Returns = @"The x parameter raised to the power of the y parameter.";
                descriptor.Example = @"    >>> pow(1.5, 3.5)
    # pow(1.5, 3.5)
    out = 4.133513940946613
    >>> pow(2, 4)
    # pow(2, 4)
    out = 16
    >>> pow(float4(1,2,3,4), 4)
    # pow(float4(1, 2, 3, 4), 4)
    out = float4(1, 16, 81, 256)
    >>> pow(float4(1..4), float4(5..8))
    # pow(float4(1..4), float4(5..8))
    out = float4(1, 64, 2187, 65536)
";
            }
            {
                var descriptor = Descriptors["round"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Rounds the specified value to the nearest integer.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The x parameter, rounded to the nearest integer within a floating-point type.";
                descriptor.Example = @"    >>> round(0.2); round(1.5); round(10.7)
    # round(0.2); round(1.5); round(10.7)
    out = 0
    out = 2
    out = 11
    >>> round(-0.2); round(-1.5); round(-10.7)
    # round(-0.2); round(-1.5); round(-10.7)
    out = -0
    out = -2
    out = -11
";
            }
            {
                var descriptor = Descriptors["floor"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the largest integer that is less than or equal to the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The largest integer value (returned as a floating-point type) that is less than or equal to the x parameter.";
                descriptor.Example = @"    >>> floor(0.2); floor(1.5); floor(10.7)
    # floor(0.2); floor(1.5); floor(10.7)
    out = 0
    out = 1
    out = 10
    >>> floor(-0.2); floor(-1.5); floor(-10.7)
    # floor(-0.2); floor(-1.5); floor(-10.7)
    out = -1
    out = -2
    out = -11
";
            }
            {
                var descriptor = Descriptors["ceil"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the smallest integer value that is greater than or equal to the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified input.")  { IsOptional = false });
                descriptor.Returns = @"The smallest integer value (returned as a floating-point type) that is greater than or equal to the x parameter.";
                descriptor.Example = @"    >>> ceil(0.2); ceil(1.5); ceil(10.7)
    # ceil(0.2); ceil(1.5); ceil(10.7)
    out = 1
    out = 2
    out = 11
    >>> ceil(-0.2); ceil(-1.5); ceil(-10.7)
    # ceil(-0.2); ceil(-1.5); ceil(-10.7)
    out = -0
    out = -1
    out = -10
";
            }
            {
                var descriptor = Descriptors["trunc"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Truncates a floating-point value to the integer component.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified input.")  { IsOptional = false });
                descriptor.Returns = @"The input value truncated to an integer component.";
                descriptor.Remarks = @"This function truncates a floating-point value to the integer component. Given a floating-point value of 1.6, the trunc function would return 1.0, where as the round function would return 2.0.";
                descriptor.Example = @"    >>> trunc(0.2); trunc(1.5); trunc(10.7)
    # trunc(0.2); trunc(1.5); trunc(10.7)
    out = 0
    out = 1
    out = 10
    >>> trunc(-0.2); trunc(-1.5); trunc(-10.7)
    # trunc(-0.2); trunc(-1.5); trunc(-10.7)
    out = -0
    out = -1
    out = -10
";
            }
            {
                var descriptor = Descriptors["saturate"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Clamps the specified value within the range of 0 to 1.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"The x parameter, clamped within the range of 0 to 1.";
                descriptor.Example = @"    >>> saturate(10)
    # saturate(10)
    out = 1
    >>> saturate(-10)
    # saturate(-10)
    out = 0
    >>> saturate(float4(-1, 0.5, 1, 2))
    # saturate(float4(-1, 0.5, 1, 2))
    out = float4(0, 0.5, 1, 1)
";
            }
            {
                var descriptor = Descriptors["min"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Selects the lesser of x and y.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The x input value.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("y", @"The y input value.")  { IsOptional = false });
                descriptor.Returns = @"The x or y parameter, whichever is the smallest value.";
                descriptor.Example = @"    >>> min(-5, 6)
    # min(-5, 6)
    out = -5
    >>> min(1, 0)
    # min(1, 0)
    out = 0
    >>> min(float4(0, 1, 2, 3), float4(1, 0, 3, 2))
    # min(float4(0, 1, 2, 3), float4(1, 0, 3, 2))
    out = float4(0, 0, 2, 2)
";
            }
            {
                var descriptor = Descriptors["max"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Selects the greater of x and y.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The x input value.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("y", @"The y input value.")  { IsOptional = false });
                descriptor.Returns = @"The x or y parameter, whichever is the largest value.";
                descriptor.Example = @"    >>> max(-5, 6)
    # max(-5, 6)
    out = 6
    >>> max(1, 0)
    # max(1, 0)
    out = 1
    >>> max(float4(0, 1, 2, 3), float4(1, 0, 3, 2))
    # max(float4(0, 1, 2, 3), float4(1, 0, 3, 2))
    out = float4(1, 1, 3, 3)
";
            }
            {
                var descriptor = Descriptors["step"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Compares two values, returning 0 or 1 based on which value is greater.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("y", @"The first floating-point value to compare.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The second floating-point value to compare.")  { IsOptional = false });
                descriptor.Returns = @"1 if the x parameter is greater than or equal to the y parameter; otherwise, 0.";
                descriptor.Remarks = @"This function uses the following formula: (x >= y) ? 1 : 0. The function returns either 0 or 1 depending on whether the x parameter is greater than the y parameter. To compute a smooth interpolation between 0 and 1, use the `smoothstep` function.";
                descriptor.Example = @"    >>> step(1, 5)
    # step(1, 5)
    out = 1
    >>> step(5, 1)
    # step(5, 1)
    out = 0
    >>> step(float4(0, 1, 2, 3), float4(1, 0, 3, 2))
    # step(float4(0, 1, 2, 3), float4(1, 0, 3, 2))
    out = float4(1, 0, 1, 0)
    >>> step(-10, 5)
    # step(-10, 5)
    out = 1
    >>> step(5.5, -10.5)
    # step(5.5, -10.5)
    out = 0
";
            }
            {
                var descriptor = Descriptors["smoothstep"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns a smooth Hermite interpolation between 0 and 1, if x is in the range [min, max].";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("min", @"The minimum range of the x parameter.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("max", @"The maximum range of the x parameter.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value to be interpolated.")  { IsOptional = false });
                descriptor.Returns = @"Returns 0 if x is less than min; 1 if x is greater than max; otherwise, a value between 0 and 1 if x is in the range [min, max].";
                descriptor.Remarks = @"Use the smoothstep function to create a smooth transition between two values. For example, you can use this function to blend two colors smoothly.";
                descriptor.Example = @"    >>> smoothstep(float4(0), float4(1), float4(-0.5))
    # smoothstep(float4(0), float4(1), float4(-0.5))
    out = float4(0, 0, 0, 0)
    >>> smoothstep(float4(0), float4(1), float4(1.5))
    # smoothstep(float4(0), float4(1), float4(1.5))
    out = float4(1, 1, 1, 1)
    >>> smoothstep(float4(0), float4(1), float4(0.5))
    # smoothstep(float4(0), float4(1), float4(0.5))
    out = float4(0.5, 0.5, 0.5, 0.5)
    >>> smoothstep(float4(0), float4(1), float4(0.9))
    # smoothstep(float4(0), float4(1), float4(0.9))
    out = float4(0.972, 0.972, 0.972, 0.972)
";
            }
            {
                var descriptor = Descriptors["lerp"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Performs a linear interpolation.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The first-floating point value.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("y", @"The second-floating point value.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("s", @"A value that linearly interpolates between the x parameter and the y parameter.")  { IsOptional = false });
                descriptor.Returns = @"The result of the linear interpolation.";
                descriptor.Example = @"    >>> lerp(0, 10, 0.5)
    # lerp(0, 10, 0.5)
    out = 5
    >>> lerp(rgb(""AliceBlue"").xyz, rgb(""Green"").xyz, 0.5)
    # lerp(rgb(""AliceBlue"").xyz, rgb(""Green"").xyz, 0.5)
    out = float3(0.47058824, 0.7372549, 0.5)
";
            }
            {
                var descriptor = Descriptors["clamp"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Clamps the specified value to the specified minimum and maximum range.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"A value to clamp.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("min", @"The specified minimum range.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("max", @"The specified maximum range.")  { IsOptional = false });
                descriptor.Returns = @"The clamped value for the x parameter.";
                descriptor.Remarks = @"For values of -inf or inf, clamp will behave as expected. However for values of `nan`, the results are undefined.";
                descriptor.Example = @"    >>> clamp(-1, 0, 1)
    # clamp(-1, 0, 1)
    out = 0
    >>> clamp(2, 0, 1)
    # clamp(2, 0, 1)
    out = 1
    >>> clamp(0.5, 0, 1)
    # clamp(0.5, 0, 1)
    out = 0.5
    >>> clamp(float4(0, 1, -2, 3), float4(0, -1, 3, 4), float4(1, 2, 5, 6))
    # clamp(float4(0, 1, -2, 3), float4(0, -1, 3, 4), float4(1, 2, 5, 6))
    out = float4(0, 1, 3, 4)
";
            }
            {
                var descriptor = Descriptors["real"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the real part of the complex number.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"A complex number.")  { IsOptional = false });
                descriptor.Returns = @"The real part of the parameter x complex number.";
                descriptor.Example = @"    >>> real(1.5 + 2.5i)
    # real(1.5 + 2.5 * i)
    out = 1.5
";
            }
            {
                var descriptor = Descriptors["imag"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the imaginary part of the complex number.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"A complex number.")  { IsOptional = false });
                descriptor.Returns = @"The imaginary part of the parameter x complex number.";
                descriptor.Example = @"    >>> imag(1.5 + 2.5i)
    # imag(1.5 + 2.5 * i)
    out = 2.5
";
            }
            {
                var descriptor = Descriptors["phase"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Returns the phase of the complex number.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"A complex number.")  { IsOptional = false });
                descriptor.Returns = @"The phase of the parameter x complex number.";
                descriptor.Example = @"    >>> phase(1.5 + 2.5i)
    # phase(1.5 + 2.5 * i)
    out = 1.0303768265243125
";
            }
            {
                var descriptor = Descriptors["isfinite"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Determines if the specified floating-point value is finite.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"Returns a value of the same size as the input, with a value set to `true` if the x parameter is finite; otherwise `false`.";
                descriptor.Example = @"    >>> isfinite(1)
    # isfinite(1)
    out = true
    >>> isfinite(nan)
    # isfinite(nan)
    out = false
    >>> isfinite(inf)
    # isfinite(inf)
    out = false
    >>> isfinite(float4(1, -10.5, inf, nan))
    # isfinite(float4(1, -10.5, inf, nan))
    out = bool4(true, true, false, false)
";
            }
            {
                var descriptor = Descriptors["isinf"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Determines if the specified value is infinite.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"Returns a value of the same size as the input, with a value set to `true` if the x parameter is +inf or -inf. Otherwise, `false`.";
                descriptor.Example = @"    >>> isinf(1)
    # isinf(1)
    out = false
    >>> isinf(inf)
    # isinf(inf)
    out = true
    >>> isinf(float4(1, -10.5, inf, nan))
    # isinf(float4(1, -10.5, inf, nan))
    out = bool4(false, false, true, false)
";
            }
            {
                var descriptor = Descriptors["isnan"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Determines if the specified value is `nan`.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified value.")  { IsOptional = false });
                descriptor.Returns = @"Returns a value of the same size as the input, with a value set to `true` if the x parameter is `nan`. Otherwise, `false`.";
                descriptor.Example = @"    >>> isnan(1)
    # isnan(1)
    out = false
    >>> isnan(inf)
    # isnan(inf)
    out = false
    >>> isnan(nan)
    # isnan(nan)
    out = true
    >>> isnan(float4(1, -10.5, inf, nan))
    # isnan(float4(1, -10.5, inf, nan))
    out = bool4(false, false, false, true)
";
            }
            {
                var descriptor = Descriptors["sum"];
                descriptor.Category = "Math Functions";
                descriptor.Description = @"Performs the summation of the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The specified value.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("values", @"Additional values.")  { IsOptional = false });
                descriptor.Returns = @"The summation of the values.";
                descriptor.Example = @"    >>> sum(1,2,3,4)
    # sum(1, 2, 3, 4)
    out = 10
    >>> sum(float4(1..4))
    # sum(float4(1..4))
    out = 10
    >>> sum(float4(1..4), float4(5..8))
    # sum(float4(1..4), float4(5..8))
    out = float4(15, 16, 17, 18)
    >>> sum(""a"", ""b"", ""c"")
    # sum(""a"", ""b"", ""c"")
    out = ""abc""
    >>> sum([""a"", ""b"", ""c""])
    # sum([""a"", ""b"", ""c""])
    out = ""abc""
";
            }
        }        
    }
}
namespace Kalk.Core.Modules
{
    public partial class MemoryModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("malloc", (Func<int, Kalk.Core.KalkNativeBuffer>)Malloc);
            RegisterFunction("bitcast", (Func<object, object, object>)Bitcast);
            RegisterFunction("asbytes", (Func<object, Kalk.Core.KalkNativeBuffer>)AsBytes);
            RegisterFunction("countbits", (Func<object, object>)CountBits);
            RegisterFunction("firstbithigh", (Func<object, object>)FirstBitHigh);
            RegisterFunction("firstbitlow", (Func<object, object>)FirstBitLow);
            RegisterFunction("reversebits", (Func<object, object>)ReverseBits);
            RegisterFunction("asdouble", (Func<object, double>)AsDouble);
            RegisterFunction("asfloat", (Func<object, float>)AsFloat);
            RegisterFunction("aslong", (Func<object, long>)AsLong);
            RegisterFunction("asulong", (Func<object, ulong>)AsULong);
            RegisterFunction("asint", (Func<object, int>)AsInt);
            RegisterFunction("asuint", (Func<object, uint>)AsUInt);
            RegisterFunction("bytebuffer", (Func<object[], Kalk.Core.KalkNativeBuffer>)ByteBuffer);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["malloc"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Allocates a `bytebuffer` of the specified size.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("size", @"Size of the bytebuffer.")  { IsOptional = false });
                descriptor.Returns = @"A bytebuffer of the specified size.";
                descriptor.Example = @"    >>> buffer = malloc(16)
    # buffer = malloc(16)
    buffer = bytebuffer([0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
    >>> buffer[0] = 5
    >>> buffer
    # buffer
    out = bytebuffer([5, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0])
";
            }
            {
                var descriptor = Descriptors["bitcast"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Binary cast of a value to a target type.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("type", @"The type to cast to.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The value to cast.")  { IsOptional = false });
                descriptor.Returns = @"The binary cast of the input value.";
                descriptor.Remarks = @"The supported types are `byte`, `sbyte`, `short`, `ushort`, `int`, `uint`, `long`, `ulong`, `float`, `double`, `rgb`, `rgba` and all vector and matrix types.";
                descriptor.Example = @"    >>> bitcast(int, 1.5f)
    # bitcast(int, 1.5f)
    out = 1_069_547_520
    >>> bitcast(float, out)
    # bitcast(float, out)
    out = 1.5
    >>> bitcast(long, 2.5)
    # bitcast(long, 2.5)
    out = 4_612_811_918_334_230_528
    >>> bitcast(double, out)
    # bitcast(double, out)
    out = 2.5
    >>> asbytes(float4(1..4))
    # asbytes(float4(1..4))
    out = bytebuffer([0, 0, 128, 63, 0, 0, 0, 64, 0, 0, 64, 64, 0, 0, 128, 64])
    >>> bitcast(float4, out)
    # bitcast(float4, out)
    out = float4(1, 2, 3, 4)
";
            }
            {
                var descriptor = Descriptors["asbytes"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Binary cast the specified value to a bytebuffer.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"An input value.")  { IsOptional = false });
                descriptor.Returns = @"A binary bytebuffer representing the value in binary form. The size of the buffer equals the binary size in memory of the input value.";
                descriptor.Example = @"    >>> asbytes(float4(1..4))
    # asbytes(float4(1..4))
    out = bytebuffer([0, 0, 128, 63, 0, 0, 0, 64, 0, 0, 64, 64, 0, 0, 128, 64])
    >>> asbytes(int(0x01020304))
    # asbytes(int(16909060))
    out = bytebuffer([4, 3, 2, 1])
    >>> asbytes(1.5)
    # asbytes(1.5)
    out = bytebuffer([0, 0, 0, 0, 0, 0, 248, 63])
    >>> asbytes(2.5f)
    # asbytes(2.5f)
    out = bytebuffer([0, 0, 32, 64])
";
            }
            {
                var descriptor = Descriptors["countbits"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Counts the number of bits (per component) of the input value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = false });
                descriptor.Returns = @"The number of bits (per component if the input is an int vector).";
                descriptor.Example = @"    >>> for val in 0..7; countbits(val); end;
    # for val in 0..7; countbits(val); end;
    out = 0
    out = 1
    out = 1
    out = 2
    out = 1
    out = 2
    out = 2
    out = 3
    >>> countbits(int4(1,2,3,4))
    # countbits(int4(1, 2, 3, 4))
    out = int4(1, 1, 2, 1)
    >>> countbits(bytebuffer(1..16))
    # countbits(bytebuffer(1..16))
    out = 33
";
            }
            {
                var descriptor = Descriptors["firstbithigh"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Gets the location of the first set bit starting from the highest order bit and working downward, per component.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = false });
                descriptor.Returns = @"The location of the first set bit.";
                descriptor.Remarks = @"If no bits are sets, this function will return -1.";
                descriptor.Example = @"    >>> firstbithigh 128
    # firstbithigh(128)
    out = 24
    >>> firstbithigh byte(128)
    # firstbithigh(byte(128))
    out = 0
    >>> firstbithigh 0
    # firstbithigh(0)
    out = -1
    >>> firstbithigh(int4(1, -1, 65536, 1 << 20))
    # firstbithigh(int4(1, -1, 65536, 1 << 20))
    out = int4(31, 0, 15, 11)
";
            }
            {
                var descriptor = Descriptors["firstbitlow"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Returns the location of the first set bit starting from the lowest order bit and working upward, per component.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = false });
                descriptor.Returns = @"The location of the first set bit.";
                descriptor.Remarks = @"If no bits are sets, this function will return -1.";
                descriptor.Example = @"    >>> firstbitlow 128
    # firstbitlow(128)
    out = 7
    >>> firstbitlow byte(128)
    # firstbitlow(byte(128))
    out = 7
    >>> firstbitlow 0
    # firstbitlow(0)
    out = -1
    >>> firstbitlow(int4(1, -1, 65536, 1 << 20))
    # firstbitlow(int4(1, -1, 65536, 1 << 20))
    out = int4(0, 0, 16, 20)
";
            }
            {
                var descriptor = Descriptors["reversebits"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Reverses the order of the bits, per component";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = false });
                descriptor.Returns = @"The input value, with the bit order reversed";
                descriptor.Example = @"    >>> reversebits 128
    # reversebits(128)
    out = 16_777_216
    >>> reversebits out
    # reversebits(out)
    out = 128
    >>> reversebits byte(128)
    # reversebits(byte(128))
    out = 1
    >>> reversebits(out)
    # reversebits(out)
    out = 128
    >>> reversebits(int4(1,2,3,4))
    # reversebits(int4(1, 2, 3, 4))
    out = int4(-2_147_483_648, 1_073_741_824, -1_073_741_824, 536_870_912)
    >>> reversebits out
    # reversebits(out)
    out = int4(1, 2, 3, 4)
";
            }
            {
                var descriptor = Descriptors["asdouble"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Reinterprets a 64-bit value into a double.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The input value.")  { IsOptional = false });
                descriptor.Returns = @"The input recast as a double.";
                descriptor.Example = @"    >>> asdouble(1.5)
    # asdouble(1.5)
    out = 1.5
    >>> aslong(1.5)
    # aslong(1.5)
    out = 4_609_434_218_613_702_656
    >>> asdouble(out)
    # asdouble(out)
    out = 1.5
";
            }
            {
                var descriptor = Descriptors["asfloat"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Reinterprets a 32-bit value into a float.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The input value.")  { IsOptional = false });
                descriptor.Returns = @"The input recast as a float.";
                descriptor.Example = @"    >>> asfloat(1.5f)
    # asfloat(1.5f)
    out = 1.5
    >>> asint(1.5f)
    # asint(1.5f)
    out = 1_069_547_520
    >>> asfloat(out)
    # asfloat(out)
    out = 1.5
";
            }
            {
                var descriptor = Descriptors["aslong"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Reinterprets an input value to a 64-bit long.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The input value.")  { IsOptional = false });
                descriptor.Returns = @"The input recast as a 64-bit long.";
                descriptor.Example = @"    >>> aslong(1.5)
    # aslong(1.5)
    out = 4_609_434_218_613_702_656
    >>> asdouble(out)
    # asdouble(out)
    out = 1.5
";
            }
            {
                var descriptor = Descriptors["asulong"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Reinterprets an input value to a 64-bit ulong.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The input value.")  { IsOptional = false });
                descriptor.Returns = @"The input recast as a 64-bit ulong.";
                descriptor.Example = @"    >>> asulong(-1.5)
    # asulong(-1.5)
    out = 13_832_806_255_468_478_464
    >>> asdouble(out)
    # asdouble(out)
    out = -1.5
";
            }
            {
                var descriptor = Descriptors["asint"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Reinterprets an input value into a 32-bit int.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The input value.")  { IsOptional = false });
                descriptor.Returns = @"The input recast as a 32-bit int.";
                descriptor.Example = @"    >>> asint(1.5f)
    # asint(1.5f)
    out = 1_069_547_520
    >>> asfloat(out)
    # asfloat(out)
    out = 1.5
";
            }
            {
                var descriptor = Descriptors["asuint"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Reinterprets an input value into a 32-bit uint.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The input value.")  { IsOptional = false });
                descriptor.Returns = @"The input recast as a 32-bit uint.";
                descriptor.Example = @"    >>> asuint(-1.5f)
    # asuint(-1.5f)
    out = 3_217_031_168
    >>> asfloat(out)
    # asfloat(out)
    out = -1.5
";
            }
            {
                var descriptor = Descriptors["bytebuffer"];
                descriptor.Category = "Misc Memory Functions";
                descriptor.Description = @"Creates a bytebuffer from the specified input.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("values", @"The input values.")  { IsOptional = false });
                descriptor.Returns = @"A bytebuffer from the specified input.";
                descriptor.Example = @"    >>> bytebuffer
    # bytebuffer
    out = bytebuffer([])
    >>> bytebuffer(0,1,2,3,4)
    # bytebuffer(0, 1, 2, 3, 4)
    out = bytebuffer([0, 1, 2, 3, 4])
    >>> bytebuffer(float4(1))
    # bytebuffer(float4(1))
    out = bytebuffer([0, 0, 128, 63, 0, 0, 128, 63, 0, 0, 128, 63, 0, 0, 128, 63])
    >>> bytebuffer([1,2,3,4])
    # bytebuffer([1,2,3,4])
    out = bytebuffer([1, 2, 3, 4])
";
            }
        }        
    }
}
namespace Kalk.Core
{
    public partial class MiscModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("date", (Func<string, object>)Date);
            RegisterFunction("ascii", (Func<object, object>)Ascii);
            RegisterFunction("foreach", (Func<Scriban.TemplateContext, System.Collections.IEnumerable, Scriban.Runtime.IScriptCustomFunction, object>)Foreach);
            RegisterFunction("keys", (Func<object, System.Collections.IEnumerable>)Keys);
            RegisterFunction("guid", (Func<string>)Guid);
            RegisterFunction("size", (Func<object, int>)Size);
            RegisterFunction("values", (Func<Scriban.TemplateContext, object, System.Collections.IEnumerable>)Values);
            RegisterFunction("hex", (Func<object, bool, string, object>)Hexadecimal);
            RegisterFunction("bin", (Func<object, bool, string, object>)Binary);
            RegisterFunction("utf8", (Func<object, object>)GetUtf8);
            RegisterFunction("utf16", (Func<object, object>)GetUtf16);
            RegisterFunction("utf32", (Func<object, object>)GetUtf32);
            RegisterFunction("insert_at", (Func<object, int, object, object>)InsertAt);
            RegisterFunction("remove_at", (Func<object, int, object>)RemoveAt);
            RegisterFunction("contains", (Func<object, object, Kalk.Core.KalkBool>)Contains);
            RegisterFunction("reverse", (Func<object, object>)Reverse);
            RegisterFunction("replace", (Func<object, object, object, object>)Replace);
            RegisterFunction("slice", (Func<object, int, int?, object>)Slice);
            RegisterFunction("lines", (Func<string, Scriban.Runtime.ScriptRange>)Lines);
            RegisterFunction("colors", (Func<object>)Colors);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["date"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Gets the current date, parse the input date or return the date object, depending on use cases.
     - If this function doesn't have any parameter and is not used to index a member, it returns the current date. It is equivalent of `date.now`
    
       The return date object has the following properties:
    
       | Name             | Description
       |--------------    |-----------------
       | `.year`          | Gets the year of a date object
       | `.month`         | Gets the month of a date object
       | `.day`           | Gets the day in the month of a date object
       | `.day_of_year`   | Gets the day within the year
       | `.hour`          | Gets the hour of the date object
       | `.minute`        | Gets the minute of the date object
       | `.second`        | Gets the second of the date object
       | `.millisecond`   | Gets the millisecond of the date object
     
     - If this function has a string parameter, it will try to parse the string as a date
     - Otherwise, if this function provides the following sub functions and members:
       - `date.add_days`: Example `'2016/01/05' |> date |> date.add_days 1`
       - `date.add_months`: Example `'2016/01/05' |> date |> date.add_months 1`
       - `date.add_years`: Example `'2016/01/05' |> date |> date.add_years 1`
       - `date.add_hours`
       - `date.add_minutes`
       - `date.add_seconds`
       - `date.add_milliseconds`
       - `date.to_string`: Converts a datetime object to a textual representation using the specified format string.
     
          By default, if you are using a date, it will use the format specified by `date.format` which defaults to `date.default_format` (readonly) which default to `%d %b %Y`
          
          You can override the format used for formatting all dates by assigning the a new format: `date.format = '%a %b %e %T %Y';`
          
          You can recover the default format by using `date.format = date.default_format;`
          
          By default, the to_string format is using the **current culture**, but you can switch to an invariant culture by using the modifier `%g`
          
          For example, using `%g %d %b %Y` will output the date using an invariant culture.
          
          If you are using `%g` alone, it will output the date with `date.format` using an invariant culture.
          
          Suppose that `date.now` would return the date `2013-09-12 22:49:27 +0530`, the following table explains the format modifiers:
          
          | Format | Result            | Description
          |--------|-------------------|--------------------------------------------
          | `""%a""` |  `""Thu""`          | Name of week day in short form of the
          | `""%A""` |  `""Thursday""`     | Week day in full form of the time
          | `""%b""` |  `""Sep""`          | Month in short form of the time
          | `""%B""` |  `""September""`    | Month in full form of the time
          | `""%c""` |                   | Date and time (%a %b %e %T %Y)
          | `""%C""` |  `""20""`           | Century of the time
          | `""%d""` |  `""12""`           | Day of the month of the time
          | `""%D""` |  `""09/12/13""`     | Date (%m/%d/%y)
          | `""%e""` |  `""12""`           | Day of the month, blank-padded ( 1..31)
          | `""%F""` |  `""2013-09-12""`   | ISO 8601 date (%Y-%m-%d)
          | `""%h""` |  `""Sep""`          | Alias for %b
          | `""%H""` |  `""22""`           | Hour of the time in 24 hour clock format
          | `""%I""` |  `""10""`           | Hour of the time in 12 hour clock format
          | `""%j""` |  `""255""`          | Day of the year (001..366) (3 digits, left padded with zero)
          | `""%k""` |  `""22""`           | Hour of the time in 24 hour clock format, blank-padded ( 0..23)
          | `""%l""` |  `""10""`           | Hour of the time in 12 hour clock format, blank-padded ( 0..12)
          | `""%L""` |  `""000""`          | Millisecond of the time (3 digits, left padded with zero)
          | `""%m""` |  `""09""`           | Month of the time
          | `""%M""` |  `""49""`           | Minutes of the time (2 digits, left padded with zero e.g 01 02)
          | `""%n""` |                   | Newline character (\n)
          | `""%N""` |  `""000000000""`    | Nanoseconds of the time (9 digits, left padded with zero)
          | `""%p""` |  `""PM""`           | Gives AM / PM of the time
          | `""%P""` |  `""pm""`           | Gives am / pm of the time
          | `""%r""` |  `""10:49:27 PM""`  | Long time in 12 hour clock format (%I:%M:%S %p)
          | `""%R""` |  `""22:49""`        | Short time in 24 hour clock format (%H:%M)
          | `""%s""` |                   | Number of seconds since 1970-01-01 00:00:00 +0000
          | `""%S""` |  `""27""`           | Seconds of the time
          | `""%t""` |                   | Tab character (\t)
          | `""%T""` |  `""22:49:27""`     | Long time in 24 hour clock format (%H:%M:%S)
          | `""%u""` |  `""4""`            | Day of week of the time (from 1 for Monday to 7 for Sunday)
          | `""%U""` |  `""36""`           | Week number of the current year, starting with the first Sunday as the first day of the first week (00..53)
          | `""%v""` |  `""12-SEP-2013""`  | VMS date (%e-%b-%Y) (culture invariant)
          | `""%V""` |  `""37""`           | Week number of the current year according to ISO 8601 (01..53)
          | `""%W""` |  `""36""`           | Week number of the current year, starting with the first Monday as the first day of the first week (00..53)
          | `""%w""` |  `""4""`            | Day of week of the time (from 0 for Sunday to 6 for Saturday)
          | `""%x""` |                   | Preferred representation for the date alone, no time
          | `""%X""` |                   | Preferred representation for the time alone, no date
          | `""%y""` |  `""13""`           | Gives year without century of the time
          | `""%Y""` |  `""2013""`         | Year of the time
          | `""%Z""` |  `""IST""`          | Gives Time Zone of the time
          | `""%%""` |  `""%""`            | Output the character `%`
          
          Note that the format is using a good part of the ruby format ([source](http://apidock.com/ruby/DateTime/strftime))";
                descriptor.IsCommand = false;
                descriptor.Returns = @"The current date, parse the input date or return the date object, depending on use cases.";
                descriptor.Example = @"     >>> today = date
     # today = date
     today = 11/22/20 10:13:00
     >>> today.year
     # today.year
     out = 2_020
     >>> today.month
     # today.month
     out = 11
     >>> ""30 Nov 2020"" |> date
     # ""30 Nov 2020"" |> date
     out = 11/30/20 00:00:00
     >>> out |> date.add_days 4
     # out |> date.add_days(4)
     out = 12/04/20 00:00:00
     >>> date.format = ""%F""
     >>> date
     # date
     out = 2020-11-22
";
            }
            {
                var descriptor = Descriptors["ascii"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Prints the ascii table or convert an input string to an ascii array, or an ascii array to a string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("obj", @"An optional input (string or array of numbers or directly an integer).")  { IsOptional = true });
                descriptor.Returns = @"Depending on the input:
    - If no input, it will display the ascii table
    - If the input is an integer, it will convert it to the equivalent ascii char.
    - If the input is a string, it will convert the string to a byte buffer containing the corresponding ascii bytes.
    - If the input is an array of integer, it will convert each element to the equivalent ascii char.";
                descriptor.Example = @"    >>> ascii 65
    # ascii(65)
    out = ""A""
    >>> ascii 97
    # ascii(97)
    out = ""a""
    >>> ascii ""A""
    # ascii(""A"")
    out = 65
    >>> ascii ""kalk""
    # ascii(""kalk"")
    out = bytebuffer([107, 97, 108, 107])
    >>> ascii out
    # ascii(out)
    out = ""kalk""
";
            }
            {
                var descriptor = Descriptors["foreach"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Process each element of the input array with the specified function.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("list", @"A list of element to process.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("func", @"A reference to a function that takes 1 parameters and return a value. The function must be passed via the prefix @ to pass a function pointer.")  { IsOptional = false });
                descriptor.Returns = @"The value transformed.";
                descriptor.Example = @"    >>> foreach([1, 2, 3, 4], @hex)
    # foreach([1, 2, 3, 4], @hex)
    out = [""01"", ""02"", ""03"", ""04""]
";
            }
            {
                var descriptor = Descriptors["keys"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Returns the keys of the specified object.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("obj", @"An object to get the keys from.")  { IsOptional = false });
                descriptor.Returns = @"The keys of the parameter obj.";
                descriptor.Example = @"    >>> obj = {m: 1, n: 2}; keys obj
    # obj = {m: 1, n: 2}; keys(obj)
    obj = {m: 1, n: 2}
    out = [""m"", ""n""]
";
            }
            {
                var descriptor = Descriptors["guid"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Returns a new GUID as a string.";
                descriptor.IsCommand = false;
                descriptor.Returns = @"A new GUID as a string.";
                descriptor.Example = @"    >>> guid
    # guid
    out = ""0deafe30-de4d-47c3-9631-2d3292afbb8e""
";
            }
            {
                var descriptor = Descriptors["size"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Returns the size of the specified object.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("obj", @"The object value.")  { IsOptional = false });
                descriptor.Returns = @"The size of the object.";
                descriptor.Example = @"    >>> size 1
    # size(1)
    out = 0
    >>> size ""kalk""
    # size(""kalk"")
    out = 4
    >>> size float4(1,2,3,4)
    # size(float4(1, 2, 3, 4))
    out = 4
    >>> size [1, 2, 3]
    # size([1, 2, 3])
    out = 3
";
            }
            {
                var descriptor = Descriptors["values"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Returns the values of the specified object.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("obj", @"An object to get the values from.")  { IsOptional = false });
                descriptor.Returns = @"The values of the parameter obj.";
                descriptor.Example = @"    >>> obj = {m: 1, n: 2}; values obj
    # obj = {m: 1, n: 2}; values(obj)
    obj = {m: 1, n: 2}
    out = [1, 2]
";
            }
            {
                var descriptor = Descriptors["hex"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Converts an integral/bytebuffer input to an hexadecimal representation or convert an hexadecimal input string
    to an integral/bytebuffer representation.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("prefix", @"Output the prefix `0x` in front of each hexadecimal bytes when converting
    from integral to hexadecimal.")  { IsOptional = true });
                descriptor.Params.Add(new KalkParamDescriptor("separator", @"The character used to separate hexadecimal bytes when converting
    from integral to hexadecimal.")  { IsOptional = true });
                descriptor.Returns = @"The hexadecimal representation of the input or convert the hexadecimal input string
    to an integral representation.";
                descriptor.Remarks = @"When converting from a hexadecimal string to an integral representation, this method
    will skip any white-space characters, comma `,`, colon `:`, semi-colon `;`, underscore `_` and
    dash `-`.
    When the hexadecimal input string can be converted to an integral less than or equal 8 bytes (64 bits)
    it will convert it to a single integral result, otherwise it will convert to a bytebuffer.
    See the following examples.";
                descriptor.Example = @"    >>> hex 10
    # hex(10)
    out = ""0A""
    >>> hex ""12c""
    # hex(""12c"")
    out = 300
    >>> hex ""0a""
    # hex(""0a"")
    out = 10
    >>> hex ""0xff030201""
    # hex(""0xff030201"")
    out = 4_278_387_201
    >>> hex out
    # hex(out)
    out = ""01 02 03 FF""
    >>> hex ""01:02:03:04:05:06:07:08:09:0A:0B:0C:0D:0E:0F""
    # hex(""01:02:03:04:05:06:07:08:09:0A:0B:0C:0D:0E:0F"")
    out = bytebuffer([1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
    >>> hex(out, true, "","")
    # hex(out, true, "","")
    out = ""0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,0x0E,0x0F""
    >>> hex out
    # hex(out)
    out = bytebuffer([1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15])
    >>> hex(""1a,2b;3c 4d-5e_6f"")
    # hex(""1a,2b;3c 4d-5e_6f"")
    out = 103_832_130_169_626
    >>> hex out
    # hex(out)
    out = ""1A 2B 3C 4D 6F 5E 00 00""
    >>> hex float4(1,2,3,4)
    # hex(float4(1, 2, 3, 4))
    out = ""00 00 80 3F 00 00 00 40 00 00 40 40 00 00 80 40""
";
            }
            {
                var descriptor = Descriptors["bin"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Converts an integral/bytebuffer input to a binary representation or convert a binary input string
    to an integral/bytebuffer representation.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("prefix", @"Output the prefix `0x` in front of each binary bytes when converting
        from integral to binary.")  { IsOptional = true });
                descriptor.Params.Add(new KalkParamDescriptor("separator", @"The character used to separate binary bytes when converting
        from integral to binary.")  { IsOptional = true });
                descriptor.Returns = @"The binary representation of the input or convert the binary input string
    to an integral representation.";
                descriptor.Remarks = @"When converting from a binary string to an integral representation, this method
    will skip any white-space characters, comma `,`, colon `:`, semi-colon `;`, underscore `_` and
    dash `-`.
    When the binary input string can be converted to an integral less than or equal 8 bytes (64 bits)
    it will convert it to a single integral result, otherwise it will convert to a bytebuffer.
    See the following examples.";
                descriptor.Example = @"    >>> bin 13
    # bin(13)
    out = ""00001101 00000000 00000000 00000000""
    >>> bin out
    # bin(out)
    out = 13
    >>> bin ""111111111011""
    # bin(""111111111011"")
    out = 4_091
    >>> bin 0xff030201
    # bin(-16580095)
    out = ""00000001 00000010 00000011 11111111""
    >>> bin out
    # bin(out)
    out = 4_278_387_201
    >>> bin ""11111111000000110000001000000001""
    # bin(""11111111000000110000001000000001"")
    out = 4_278_387_201
    >>> bin(byte(5))
    # bin(byte(5))
    out = ""00000101""
    >>> bin(long(6))
    # bin(long(6))
    out = ""00000110 00000000 00000000 00000000 00000000 00000000 00000000 00000000""
    >>> bin(out)
    # bin(out)
    out = 6
    >>> kind(out)
    # kind(out)
    out = ""long""
";
            }
            {
                var descriptor = Descriptors["utf8"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Converts a string to an UTF8 bytebuffer or convert a bytebuffer of UTF8 bytes to a string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The specified input.")  { IsOptional = false });
                descriptor.Returns = @"The UTF8 bytebuffer representation of the input string or the string representation of the input UTF8 bytebuffer.";
                descriptor.Example = @"    >>> utf8 ""kalk""
    # utf8(""kalk"")
    out = bytebuffer([107, 97, 108, 107])
    >>> utf8 out
    # utf8(out)
    out = ""kalk""
";
            }
            {
                var descriptor = Descriptors["utf16"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Converts a string to an UTF16 bytebuffer or convert a bytebuffer of UTF16 bytes to a string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The specified input.")  { IsOptional = false });
                descriptor.Returns = @"The UTF16 bytebuffer representation of the input string or the string representation of the input UTF16 bytebuffer.";
                descriptor.Example = @"    >>> utf16 ""kalk""
    # utf16(""kalk"")
    out = bytebuffer([107, 0, 97, 0, 108, 0, 107, 0])
    >>> utf16 out
    # utf16(out)
    out = ""kalk""
";
            }
            {
                var descriptor = Descriptors["utf32"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Converts a string to an UTF32 bytebuffer or convert a bytebuffer of UTF32 bytes to a string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The specified input.")  { IsOptional = false });
                descriptor.Returns = @"The UTF32 bytebuffer representation of the input string or the string representation of the input UTF32 bytebuffer.";
                descriptor.Example = @"    >>> utf32 ""kalk""
    # utf32(""kalk"")
    out = bytebuffer([107, 0, 0, 0, 97, 0, 0, 0, 108, 0, 0, 0, 107, 0, 0, 0])
    >>> utf32 out
    # utf32(out)
    out = ""kalk""
";
            }
            {
                var descriptor = Descriptors["insert_at"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Inserts an item into a string or list at the specified index.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("list", @"A string or list to insert an item into.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("index", @"The index at which to insert the item.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("item", @"The item to insert.")  { IsOptional = false });
                descriptor.Returns = @"A new string with the item inserted, or a new list with the item inserted at the specified index.";
                descriptor.Remarks = @"The index is adjusted at the modulo of the length of the input value.
    If the index is < 0, then the index starts from the end of the string/list length + 1. A value of -1 for the index would insert the item at the end, after the last element of the string or list.";
                descriptor.Example = @"    >>> insert_at(""kalk"", 0, ""YES"")
    # insert_at(""kalk"", 0, ""YES"")
    out = ""YESkalk""
    >>> insert_at(""kalk"", -1, ""YES"")
    # insert_at(""kalk"", -1, ""YES"")
    out = ""kalkYES""
    >>> insert_at(0..10, 1, 50)
    # insert_at(0..10, 1, 50)
    out = [0, 50, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10]
    >>> insert_at(0..9, 21, 50) # final index is 21 % 10 = 1
    # insert_at(0..9, 21, 50) # final index is 21 % 10 = 1
    out = [0, 50, 1, 2, 3, 4, 5, 6, 7, 8, 9]
    >>> insert_at([], 3, 1)
    # insert_at([], 3, 1)
    out = [1]
";
            }
            {
                var descriptor = Descriptors["remove_at"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Removes an item from a string or list at the specified index.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("list", @"A string or list to remove an item from.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("index", @"The index at which to remove the item.")  { IsOptional = false });
                descriptor.Returns = @"A new string/list with the item at the specified index removed.";
                descriptor.Remarks = @"The index is adjusted at the modulo of the length of the input value.
    If the index is < 0, then the index starts from the end of the string/list length. A value of -1 for the index would remove the last element.";
                descriptor.Example = @"    >>> remove_at(""kalk"", 0)
    # remove_at(""kalk"", 0)
    out = ""alk""
    >>> remove_at(""kalk"", -1)
    # remove_at(""kalk"", -1)
    out = ""kal""
    >>> remove_at(0..9, 5)
    # remove_at(0..9, 5)
    out = [0, 1, 2, 3, 4, 6, 7, 8, 9]
    >>> remove_at(0..9, -1)
    # remove_at(0..9, -1)
    out = [0, 1, 2, 3, 4, 5, 6, 7, 8]
    >>> remove_at(asbytes(0x04030201), 1)
    # remove_at(asbytes(67305985), 1)
    out = bytebuffer([1, 3, 4])
";
            }
            {
                var descriptor = Descriptors["contains"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Checks if an object (string, list, vector types, bytebuffer...) is containing the specified value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("list", @"The list to search into.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The value to search into the list.")  { IsOptional = false });
                descriptor.Returns = @"true if value was found in the list input; otherwise false.";
                descriptor.Example = @"    >>> contains(""kalk"", ""l"")
    # contains(""kalk"", ""l"")
    out = true
    >>> contains(""kalk"", ""e"")
    # contains(""kalk"", ""e"")
    out = false
    >>> contains([1,2,3,4,5], 3)
    # contains([1,2,3,4,5], 3)
    out = true
    >>> contains([1,2,3,4,5], 6)
    # contains([1,2,3,4,5], 6)
    out = false
    >>> contains(float4(1,2,3,4), 3)
    # contains(float4(1, 2, 3, 4), 3)
    out = true
    >>> contains(float4(1,2,3,4), 6)
    # contains(float4(1, 2, 3, 4), 6)
    out = false
";
            }
            {
                var descriptor = Descriptors["reverse"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Reverse a list of values.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("list", @"The list to reverse.")  { IsOptional = false });
                descriptor.Returns = @"The list of values reversed.";
                descriptor.Example = @"    >>> reverse([1,2,3,4,5])
    # reverse([1,2,3,4,5])
    out = [5, 4, 3, 2, 1]
    >>> reverse(""abc"")
    # reverse(""abc"")
    out = ""cba""
    >>> reverse(asbytes(0x04030201))
    # reverse(asbytes(67305985))
    out = bytebuffer([4, 3, 2, 1])
";
            }
            {
                var descriptor = Descriptors["replace"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Replaces in an object (string, list, vector types, bytebuffer...) an item of the specified value by another value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("list", @"The list to search into to replace an element.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The item to replace.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("by", @"The value to replace with.")  { IsOptional = false });
                descriptor.Returns = @"The modified object.";
                descriptor.Example = @"    >>> replace(""kalk"", ""k"", ""woo"")
    # replace(""kalk"", ""k"", ""woo"")
    out = ""wooalwoo""
    >>> replace([1,2,3,4], 3, 5)
    # replace([1,2,3,4], 3, 5)
    out = [1, 2, 5, 4]
    >>> replace(float4(1,2,3,4), 3, 5)
    # replace(float4(1, 2, 3, 4), 3, 5)
    out = float4(1, 2, 5, 4)
";
            }
            {
                var descriptor = Descriptors["slice"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Creates a slice of an object (string, list, vector types, bytebuffer...) starting at the specified index and with the specified length;";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("list", @"The object to create a slice from.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("index", @"The index into the object.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("length", @"The optional length of the slice. If the length is not defined, the length will start from index with the remaining elements.")  { IsOptional = true });
                descriptor.Returns = @"A slice of the input object.";
                descriptor.Remarks = @"The index is adjusted at the modulo of the specified length of the input object.
    If the index is < 0, then the index starts from the end of the input object length. A value of -1 for the index would take a slice with the only the last element.";
                descriptor.Example = @"    >>> slice(""kalk"", 1)
    # slice(""kalk"", 1)
    out = ""alk""
    >>> slice(""kalk"", -2)
    # slice(""kalk"", -2)
    out = ""lk""
    >>> slice(""kalk"", 1, 2)
    # slice(""kalk"", 1, 2)
    out = ""al""
    >>> slice([1,2,3,4], 1)
    # slice([1,2,3,4], 1)
    out = [2, 3, 4]
    >>> slice([1,2,3,4], -1)
    # slice([1,2,3,4], -1)
    out = [4]
    >>> slice([1,2,3,4], -1, 3) # length is bigger than expected, no errors
    # slice([1,2,3,4], -1, 3) # length is bigger than expected, no errors
    out = [4]
    >>> slice(asbytes(0x04030201), 1, 2)
    # slice(asbytes(67305985), 1, 2)
    out = slice(bytebuffer([2, 3]), 1, 2)
";
            }
            {
                var descriptor = Descriptors["lines"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Extract lines from the specified string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"A string to extract lines from.")  { IsOptional = false });
                descriptor.Returns = @"Lines extracted from the input string.";
                descriptor.Example = @"    >>> lines(""k\na\nl\nk"")
    # lines(""k\na\nl\nk"")
    out = [""k"", ""a"", ""l"", ""k""]
";
            }
            {
                var descriptor = Descriptors["colors"];
                descriptor.Category = "Misc Functions";
                descriptor.Description = @"Display or returns the known CSS colors.";
                descriptor.IsCommand = false;
                descriptor.Returns = @"Prints known CSS colors or return a list if this function is used in an expression.";
                descriptor.Example = @"    >>> colors[0]
    # colors[0]
    out = rgb(240, 248, 255) ## F0F8FF AliceBlue ##
    >>> mycolor = colors[""AliceBlue""]; mycolor.name
    # mycolor = colors[""AliceBlue""]; mycolor.name
    mycolor = rgb(240, 248, 255) ## F0F8FF AliceBlue ##
    out = ""AliceBlue""
";
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.Arm
{
    public partial class Sha1IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("vsha1cq_u32", (Func<object, object, object, object>)vsha1cq_u32);
            RegisterFunction("vsha1h_u32", (Func<object, object>)vsha1h_u32);
            RegisterFunction("vsha1mq_u32", (Func<object, object, object, object>)vsha1mq_u32);
            RegisterFunction("vsha1pq_u32", (Func<object, object, object, object>)vsha1pq_u32);
            RegisterFunction("vsha1su0q_u32", (Func<object, object, object, object>)vsha1su0q_u32);
            RegisterFunction("vsha1su1q_u32", (Func<object, object, object>)vsha1su1q_u32);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["vsha1cq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / SHA1";
                descriptor.Description = @"uint32x4_t vsha1cq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
    A32: SHA1C.32 Qd, Qn, Qm
    A64: SHA1C Qd, Sn, Vm.4S
    
    
    Instruction Documentation: [vsha1cq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1cq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsha1h_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / SHA1";
                descriptor.Description = @"uint32_t vsha1h_u32 (uint32_t hash_e)
    A32: SHA1H.32 Qd, Qm
    A64: SHA1H Sd, Sn
    
    
    Instruction Documentation: [vsha1h_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1h_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsha1mq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / SHA1";
                descriptor.Description = @"uint32x4_t vsha1mq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
    A32: SHA1M.32 Qd, Qn, Qm
    A64: SHA1M Qd, Sn, Vm.4S
    
    
    Instruction Documentation: [vsha1mq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1mq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsha1pq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / SHA1";
                descriptor.Description = @"uint32x4_t vsha1pq_u32 (uint32x4_t hash_abcd, uint32_t hash_e, uint32x4_t wk)
    A32: SHA1P.32 Qd, Qn, Qm
    A64: SHA1P Qd, Sn, Vm.4S
    
    
    Instruction Documentation: [vsha1pq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1pq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsha1su0q_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / SHA1";
                descriptor.Description = @"uint32x4_t vsha1su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7, uint32x4_t w8_11)
    A32: SHA1SU0.32 Qd, Qn, Qm
    A64: SHA1SU0 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vsha1su0q_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su0q_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsha1su1q_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / SHA1";
                descriptor.Description = @"uint32x4_t vsha1su1q_u32 (uint32x4_t tw0_3, uint32x4_t w12_15)
    A32: SHA1SU1.32 Qd, Qm
    A64: SHA1SU1 Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vsha1su1q_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha1su1q_u32)";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.Arm
{
    public partial class Sha256IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("vsha256h2q_u32", (Func<object, object, object, object>)vsha256h2q_u32);
            RegisterFunction("vsha256hq_u32", (Func<object, object, object, object>)vsha256hq_u32);
            RegisterFunction("vsha256su0q_u32", (Func<object, object, object>)vsha256su0q_u32);
            RegisterFunction("vsha256su1q_u32", (Func<object, object, object, object>)vsha256su1q_u32);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["vsha256h2q_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / SHA256";
                descriptor.Description = @"uint32x4_t vsha256h2q_u32 (uint32x4_t hash_efgh, uint32x4_t hash_abcd, uint32x4_t wk)
    A32: SHA256H2.32 Qd, Qn, Qm
    A64: SHA256H2 Qd, Qn, Vm.4S
    
    
    Instruction Documentation: [vsha256h2q_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256h2q_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsha256hq_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / SHA256";
                descriptor.Description = @"uint32x4_t vsha256hq_u32 (uint32x4_t hash_abcd, uint32x4_t hash_efgh, uint32x4_t wk)
    A32: SHA256H.32 Qd, Qn, Qm
    A64: SHA256H Qd, Qn, Vm.4S
    
    
    Instruction Documentation: [vsha256hq_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256hq_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsha256su0q_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / SHA256";
                descriptor.Description = @"uint32x4_t vsha256su0q_u32 (uint32x4_t w0_3, uint32x4_t w4_7)
    A32: SHA256SU0.32 Qd, Qm
    A64: SHA256SU0 Vd.4S, Vn.4S
    
    
    Instruction Documentation: [vsha256su0q_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su0q_u32)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["vsha256su1q_u32"];
                descriptor.Category = "Vector Hardware Intrinsics Arm / SHA256";
                descriptor.Description = @"uint32x4_t vsha256su1q_u32 (uint32x4_t w0_3, uint32x4_t w8_11, uint32x4_t w12_15)
    A32: SHA256SU1.32 Qd, Qn, Qm
    A64: SHA256SU1 Vd.4S, Vn.4S, Vm.4S
    
    
    Instruction Documentation: [vsha256su1q_u32](https://developer.arm.com/architectures/instruction-sets/intrinsics/vsha256su1q_u32)";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Sse2IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_add_epi16", (Func<object, object, object>)mm_add_epi16);
            RegisterFunction("mm_add_epi32", (Func<object, object, object>)mm_add_epi32);
            RegisterFunction("mm_add_epi64", (Func<object, object, object>)mm_add_epi64);
            RegisterFunction("mm_add_epi8", (Func<object, object, object>)mm_add_epi8);
            RegisterFunction("mm_add_pd", (Func<object, object, object>)mm_add_pd);
            RegisterFunction("mm_add_sd", (Func<object, object, object>)mm_add_sd);
            RegisterFunction("mm_adds_epi16", (Func<object, object, object>)mm_adds_epi16);
            RegisterFunction("mm_adds_epi8", (Func<object, object, object>)mm_adds_epi8);
            RegisterFunction("mm_adds_epu16", (Func<object, object, object>)mm_adds_epu16);
            RegisterFunction("mm_adds_epu8", (Func<object, object, object>)mm_adds_epu8);
            RegisterFunction("mm_and_pd", (Func<object, object, object>)mm_and_pd);
            RegisterFunction("mm_and_si128", (Func<object, object, object>)mm_and_si128);
            RegisterFunction("mm_andnot_pd", (Func<object, object, object>)mm_andnot_pd);
            RegisterFunction("mm_andnot_si128", (Func<object, object, object>)mm_andnot_si128);
            RegisterFunction("mm_avg_epu16", (Func<object, object, object>)mm_avg_epu16);
            RegisterFunction("mm_avg_epu8", (Func<object, object, object>)mm_avg_epu8);
            RegisterFunction("mm_bslli_si128", (Func<object, byte, object>)mm_bslli_si128);
            RegisterFunction("mm_bsrli_si128", (Func<object, byte, object>)mm_bsrli_si128);
            RegisterFunction("mm_cmpeq_epi16", (Func<object, object, object>)mm_cmpeq_epi16);
            RegisterFunction("mm_cmpeq_epi32", (Func<object, object, object>)mm_cmpeq_epi32);
            RegisterFunction("mm_cmpeq_epi8", (Func<object, object, object>)mm_cmpeq_epi8);
            RegisterFunction("mm_cmpeq_pd", (Func<object, object, object>)mm_cmpeq_pd);
            RegisterFunction("mm_cmpeq_sd", (Func<object, object, object>)mm_cmpeq_sd);
            RegisterFunction("mm_cmpge_pd", (Func<object, object, object>)mm_cmpge_pd);
            RegisterFunction("mm_cmpge_sd", (Func<object, object, object>)mm_cmpge_sd);
            RegisterFunction("mm_cmpgt_epi16", (Func<object, object, object>)mm_cmpgt_epi16);
            RegisterFunction("mm_cmpgt_epi32", (Func<object, object, object>)mm_cmpgt_epi32);
            RegisterFunction("mm_cmpgt_epi8", (Func<object, object, object>)mm_cmpgt_epi8);
            RegisterFunction("mm_cmpgt_pd", (Func<object, object, object>)mm_cmpgt_pd);
            RegisterFunction("mm_cmpgt_sd", (Func<object, object, object>)mm_cmpgt_sd);
            RegisterFunction("mm_cmple_pd", (Func<object, object, object>)mm_cmple_pd);
            RegisterFunction("mm_cmple_sd", (Func<object, object, object>)mm_cmple_sd);
            RegisterFunction("mm_cmplt_epi16", (Func<object, object, object>)mm_cmplt_epi16);
            RegisterFunction("mm_cmplt_epi32", (Func<object, object, object>)mm_cmplt_epi32);
            RegisterFunction("mm_cmplt_epi8", (Func<object, object, object>)mm_cmplt_epi8);
            RegisterFunction("mm_cmplt_pd", (Func<object, object, object>)mm_cmplt_pd);
            RegisterFunction("mm_cmplt_sd", (Func<object, object, object>)mm_cmplt_sd);
            RegisterFunction("mm_cmpneq_pd", (Func<object, object, object>)mm_cmpneq_pd);
            RegisterFunction("mm_cmpneq_sd", (Func<object, object, object>)mm_cmpneq_sd);
            RegisterFunction("mm_cmpnge_pd", (Func<object, object, object>)mm_cmpnge_pd);
            RegisterFunction("mm_cmpnge_sd", (Func<object, object, object>)mm_cmpnge_sd);
            RegisterFunction("mm_cmpngt_pd", (Func<object, object, object>)mm_cmpngt_pd);
            RegisterFunction("mm_cmpngt_sd", (Func<object, object, object>)mm_cmpngt_sd);
            RegisterFunction("mm_cmpnle_pd", (Func<object, object, object>)mm_cmpnle_pd);
            RegisterFunction("mm_cmpnle_sd", (Func<object, object, object>)mm_cmpnle_sd);
            RegisterFunction("mm_cmpnlt_pd", (Func<object, object, object>)mm_cmpnlt_pd);
            RegisterFunction("mm_cmpnlt_sd", (Func<object, object, object>)mm_cmpnlt_sd);
            RegisterFunction("mm_cmpord_pd", (Func<object, object, object>)mm_cmpord_pd);
            RegisterFunction("mm_cmpord_sd", (Func<object, object, object>)mm_cmpord_sd);
            RegisterFunction("mm_cmpunord_pd", (Func<object, object, object>)mm_cmpunord_pd);
            RegisterFunction("mm_cmpunord_sd", (Func<object, object, object>)mm_cmpunord_sd);
            RegisterFunction("mm_comieq_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_comieq_sd);
            RegisterFunction("mm_comige_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_comige_sd);
            RegisterFunction("mm_comigt_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_comigt_sd);
            RegisterFunction("mm_comile_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_comile_sd);
            RegisterFunction("mm_comilt_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_comilt_sd);
            RegisterFunction("mm_comineq_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_comineq_sd);
            RegisterFunction("mm_cvtepi32_pd", (Func<object, object>)mm_cvtepi32_pd);
            RegisterFunction("mm_cvtepi32_ps", (Func<object, object>)mm_cvtepi32_ps);
            RegisterFunction("mm_cvtpd_epi32", (Func<object, object>)mm_cvtpd_epi32);
            RegisterFunction("mm_cvtpd_ps", (Func<object, object>)mm_cvtpd_ps);
            RegisterFunction("mm_cvtps_epi32", (Func<object, object>)mm_cvtps_epi32);
            RegisterFunction("mm_cvtps_pd", (Func<object, object>)mm_cvtps_pd);
            RegisterFunction("mm_cvtsd_si32", (Func<object, int>)mm_cvtsd_si32);
            RegisterFunction("mm_cvtsd_ss", (Func<object, object, object>)mm_cvtsd_ss);
            RegisterFunction("mm_cvtsi128_si32", (Func<object, int>)mm_cvtsi128_si32);
            RegisterFunction("mm_cvtsi32_sd", (Func<object, int, object>)mm_cvtsi32_sd);
            RegisterFunction("mm_cvtsi32_si128", (Func<int, object>)mm_cvtsi32_si128);
            RegisterFunction("mm_cvtss_sd", (Func<object, object, object>)mm_cvtss_sd);
            RegisterFunction("mm_cvttpd_epi32", (Func<object, object>)mm_cvttpd_epi32);
            RegisterFunction("mm_cvttps_epi32", (Func<object, object>)mm_cvttps_epi32);
            RegisterFunction("mm_cvttsd_si32", (Func<object, int>)mm_cvttsd_si32);
            RegisterFunction("mm_div_pd", (Func<object, object, object>)mm_div_pd);
            RegisterFunction("mm_div_sd", (Func<object, object, object>)mm_div_sd);
            RegisterFunction("mm_extract_epi16", (Func<object, byte, ushort>)mm_extract_epi16);
            RegisterFunction("mm_insert_epi16", (Func<object, short, byte, object>)mm_insert_epi16);
            RegisterFunction("mm_load_pd", (Func<object, object>)mm_load_pd);
            RegisterFunction("mm_load_sd", (Func<object, object>)mm_load_sd);
            RegisterFunction("mm_load_si128", (Func<object, object>)mm_load_si128);
            RegisterFunction("mm_loadh_pd", (Func<object, object, object>)mm_loadh_pd);
            RegisterFunction("mm_loadl_epi32", (Func<object, object>)mm_loadl_epi32);
            RegisterFunction("mm_loadl_epi64", (Func<object, object>)mm_loadl_epi64);
            RegisterFunction("mm_loadl_pd", (Func<object, object, object>)mm_loadl_pd);
            RegisterFunction("mm_loadu_pd", (Func<object, object>)mm_loadu_pd);
            RegisterFunction("mm_loadu_si128", (Func<object, object>)mm_loadu_si128);
            RegisterFunction("mm_madd_epi16", (Func<object, object, object>)mm_madd_epi16);
            RegisterAction("mm_maskmoveu_si128", (Action<object, object, object>)mm_maskmoveu_si128);
            RegisterFunction("mm_max_epi16", (Func<object, object, object>)mm_max_epi16);
            RegisterFunction("mm_max_epu8", (Func<object, object, object>)mm_max_epu8);
            RegisterFunction("mm_max_pd", (Func<object, object, object>)mm_max_pd);
            RegisterFunction("mm_max_sd", (Func<object, object, object>)mm_max_sd);
            RegisterFunction("mm_min_epi16", (Func<object, object, object>)mm_min_epi16);
            RegisterFunction("mm_min_epu8", (Func<object, object, object>)mm_min_epu8);
            RegisterFunction("mm_min_pd", (Func<object, object, object>)mm_min_pd);
            RegisterFunction("mm_min_sd", (Func<object, object, object>)mm_min_sd);
            RegisterFunction("mm_move_epi64", (Func<object, object>)mm_move_epi64);
            RegisterFunction("mm_move_sd", (Func<object, object, object>)mm_move_sd);
            RegisterFunction("mm_movemask_epi8", (Func<object, int>)mm_movemask_epi8);
            RegisterFunction("mm_movemask_pd", (Func<object, int>)mm_movemask_pd);
            RegisterFunction("mm_mul_epu32", (Func<object, object, object>)mm_mul_epu32);
            RegisterFunction("mm_mul_pd", (Func<object, object, object>)mm_mul_pd);
            RegisterFunction("mm_mul_sd", (Func<object, object, object>)mm_mul_sd);
            RegisterFunction("mm_mulhi_epi16", (Func<object, object, object>)mm_mulhi_epi16);
            RegisterFunction("mm_mulhi_epu16", (Func<object, object, object>)mm_mulhi_epu16);
            RegisterFunction("mm_mullo_epi16", (Func<object, object, object>)mm_mullo_epi16);
            RegisterFunction("mm_or_pd", (Func<object, object, object>)mm_or_pd);
            RegisterFunction("mm_or_si128", (Func<object, object, object>)mm_or_si128);
            RegisterFunction("mm_packs_epi16", (Func<object, object, object>)mm_packs_epi16);
            RegisterFunction("mm_packs_epi32", (Func<object, object, object>)mm_packs_epi32);
            RegisterFunction("mm_packus_epi16", (Func<object, object, object>)mm_packus_epi16);
            RegisterFunction("mm_sad_epu8", (Func<object, object, object>)mm_sad_epu8);
            RegisterFunction("mm_shuffle_epi32", (Func<object, byte, object>)mm_shuffle_epi32);
            RegisterFunction("mm_shuffle_pd", (Func<object, object, byte, object>)mm_shuffle_pd);
            RegisterFunction("mm_shufflehi_epi16", (Func<object, byte, object>)mm_shufflehi_epi16);
            RegisterFunction("mm_shufflelo_epi16", (Func<object, byte, object>)mm_shufflelo_epi16);
            RegisterFunction("mm_sll_epi16", (Func<object, object, object>)mm_sll_epi16);
            RegisterFunction("mm_sll_epi32", (Func<object, object, object>)mm_sll_epi32);
            RegisterFunction("mm_sll_epi64", (Func<object, object, object>)mm_sll_epi64);
            RegisterFunction("mm_slli_epi16", (Func<object, byte, object>)mm_slli_epi16);
            RegisterFunction("mm_slli_epi32", (Func<object, byte, object>)mm_slli_epi32);
            RegisterFunction("mm_slli_epi64", (Func<object, byte, object>)mm_slli_epi64);
            RegisterFunction("mm_sqrt_pd", (Func<object, object>)mm_sqrt_pd);
            RegisterFunction("mm_sqrt_sd", (Func<object, object, object>)mm_sqrt_sd);
            RegisterFunction("mm_sqrt_sd1", (Func<object, object>)mm_sqrt_sd1);
            RegisterFunction("mm_sra_epi16", (Func<object, object, object>)mm_sra_epi16);
            RegisterFunction("mm_sra_epi32", (Func<object, object, object>)mm_sra_epi32);
            RegisterFunction("mm_srai_epi16", (Func<object, byte, object>)mm_srai_epi16);
            RegisterFunction("mm_srai_epi32", (Func<object, byte, object>)mm_srai_epi32);
            RegisterFunction("mm_srl_epi16", (Func<object, object, object>)mm_srl_epi16);
            RegisterFunction("mm_srl_epi32", (Func<object, object, object>)mm_srl_epi32);
            RegisterFunction("mm_srl_epi64", (Func<object, object, object>)mm_srl_epi64);
            RegisterFunction("mm_srli_epi16", (Func<object, byte, object>)mm_srli_epi16);
            RegisterFunction("mm_srli_epi32", (Func<object, byte, object>)mm_srli_epi32);
            RegisterFunction("mm_srli_epi64", (Func<object, byte, object>)mm_srli_epi64);
            RegisterAction("mm_store_pd", (Action<object, object>)mm_store_pd);
            RegisterAction("mm_store_sd", (Action<object, object>)mm_store_sd);
            RegisterAction("mm_store_si128", (Action<object, object>)mm_store_si128);
            RegisterAction("mm_storeh_pd", (Action<object, object>)mm_storeh_pd);
            RegisterAction("mm_storel_epi64", (Action<object, object>)mm_storel_epi64);
            RegisterAction("mm_storel_pd", (Action<object, object>)mm_storel_pd);
            RegisterAction("mm_storeu_pd", (Action<object, object>)mm_storeu_pd);
            RegisterAction("mm_storeu_si128", (Action<object, object>)mm_storeu_si128);
            RegisterAction("mm_storeu_si32", (Action<object, object>)mm_storeu_si32);
            RegisterAction("mm_stream_pd", (Action<object, object>)mm_stream_pd);
            RegisterAction("mm_stream_si128", (Action<object, object>)mm_stream_si128);
            RegisterAction("mm_stream_si32", (Action<object, int>)mm_stream_si32);
            RegisterFunction("mm_sub_epi16", (Func<object, object, object>)mm_sub_epi16);
            RegisterFunction("mm_sub_epi32", (Func<object, object, object>)mm_sub_epi32);
            RegisterFunction("mm_sub_epi64", (Func<object, object, object>)mm_sub_epi64);
            RegisterFunction("mm_sub_epi8", (Func<object, object, object>)mm_sub_epi8);
            RegisterFunction("mm_sub_pd", (Func<object, object, object>)mm_sub_pd);
            RegisterFunction("mm_sub_sd", (Func<object, object, object>)mm_sub_sd);
            RegisterFunction("mm_subs_epi16", (Func<object, object, object>)mm_subs_epi16);
            RegisterFunction("mm_subs_epi8", (Func<object, object, object>)mm_subs_epi8);
            RegisterFunction("mm_subs_epu16", (Func<object, object, object>)mm_subs_epu16);
            RegisterFunction("mm_subs_epu8", (Func<object, object, object>)mm_subs_epu8);
            RegisterFunction("mm_ucomieq_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomieq_sd);
            RegisterFunction("mm_ucomige_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomige_sd);
            RegisterFunction("mm_ucomigt_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomigt_sd);
            RegisterFunction("mm_ucomile_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomile_sd);
            RegisterFunction("mm_ucomilt_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomilt_sd);
            RegisterFunction("mm_ucomineq_sd", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomineq_sd);
            RegisterFunction("mm_unpackhi_epi16", (Func<object, object, object>)mm_unpackhi_epi16);
            RegisterFunction("mm_unpackhi_epi32", (Func<object, object, object>)mm_unpackhi_epi32);
            RegisterFunction("mm_unpackhi_epi64", (Func<object, object, object>)mm_unpackhi_epi64);
            RegisterFunction("mm_unpackhi_epi8", (Func<object, object, object>)mm_unpackhi_epi8);
            RegisterFunction("mm_unpackhi_pd", (Func<object, object, object>)mm_unpackhi_pd);
            RegisterFunction("mm_unpacklo_epi16", (Func<object, object, object>)mm_unpacklo_epi16);
            RegisterFunction("mm_unpacklo_epi32", (Func<object, object, object>)mm_unpacklo_epi32);
            RegisterFunction("mm_unpacklo_epi64", (Func<object, object, object>)mm_unpacklo_epi64);
            RegisterFunction("mm_unpacklo_epi8", (Func<object, object, object>)mm_unpacklo_epi8);
            RegisterFunction("mm_unpacklo_pd", (Func<object, object, object>)mm_unpacklo_pd);
            RegisterFunction("mm_xor_pd", (Func<object, object, object>)mm_xor_pd);
            RegisterFunction("mm_xor_si128", (Func<object, object, object>)mm_xor_si128);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_add_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Add packed 16-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_add_epi16 (__m128i a,  __m128i b)
    PADDW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_add_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Add packed 32-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_add_epi32 (__m128i a,  __m128i b)
    PADDD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_add_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Add packed 64-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_add_epi64 (__m128i a,  __m128i b)
    PADDQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_add_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Add packed 8-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_add_epi8 (__m128i a,  __m128i b)
    PADDB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_add_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Add packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128d _mm_add_pd (__m128d a,  __m128d b)
    ADDPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_add_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Add the lower double-precision (64-bit) floating-point element in ""a"" and ""b"", store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_add_sd (__m128d a,  __m128d b)
    ADDSD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_adds_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Add packed 16-bit integers in ""a"" and ""b"" using saturation, and store the results in ""dst"".
    
    __m128i _mm_adds_epi16 (__m128i a,  __m128i b)
    PADDSW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_adds_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Add packed 8-bit integers in ""a"" and ""b"" using saturation, and store the results in ""dst"".
    
    __m128i _mm_adds_epi8 (__m128i a,  __m128i b)
    PADDSB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_adds_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Add packed unsigned 16-bit integers in ""a"" and ""b"" using saturation, and store the results in ""dst"".
    
    __m128i _mm_adds_epu16 (__m128i a,  __m128i b)
    PADDUSW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_adds_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Add packed unsigned 8-bit integers in ""a"" and ""b"" using saturation, and store the results in ""dst"".
    
    __m128i _mm_adds_epu8 (__m128i a,  __m128i b)
    PADDUSB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_and_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the bitwise AND of packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128d _mm_and_pd (__m128d a, __m128d b)
    ANDPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_and_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the bitwise AND of 128 bits (representing integer data) in ""a"" and ""b"", and store the result in ""dst"".
    
    __m128i _mm_and_si128 (__m128i a,  __m128i b)
    PAND xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_andnot_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the bitwise NOT of packed double-precision (64-bit) floating-point elements in ""a"" and then AND with ""b"", and store the results in ""dst"".
    
    __m128d _mm_andnot_pd (__m128d a, __m128d b)
    ADDNPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_andnot_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the bitwise NOT of 128 bits (representing integer data) in ""a"" and then AND with ""b"", and store the result in ""dst"".
    
    __m128i _mm_andnot_si128 (__m128i a,  __m128i b)
    PANDN xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_avg_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Average packed unsigned 16-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_avg_epu16 (__m128i a,  __m128i b)
    PAVGW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_avg_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Average packed unsigned 8-bit integers in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_avg_epu8 (__m128i a,  __m128i b)
    PAVGB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_bslli_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift ""a"" left by ""imm8"" bytes while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_bslli_si128 (__m128i a, int imm8)
    PSLLDQ xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_bsrli_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift ""a"" right by ""imm8"" bytes while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_bsrli_si128 (__m128i a, int imm8)
    PSRLDQ xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpeq_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed 16-bit integers in ""a"" and ""b"" for equality, and store the results in ""dst"".
    
    __m128i _mm_cmpeq_epi16 (__m128i a,  __m128i b)
    PCMPEQW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpeq_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed 32-bit integers in ""a"" and ""b"" for equality, and store the results in ""dst"".
    
    __m128i _mm_cmpeq_epi32 (__m128i a,  __m128i b)
    PCMPEQD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpeq_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed 8-bit integers in ""a"" and ""b"" for equality, and store the results in ""dst"".
    
    __m128i _mm_cmpeq_epi8 (__m128i a,  __m128i b)
    PCMPEQB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpeq_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" for equality, and store the results in ""dst"".
    
    __m128d _mm_cmpeq_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(0)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpeq_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" for equality, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmpeq_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(0)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpge_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" for greater-than-or-equal, and store the results in ""dst"".
    
    __m128d _mm_cmpge_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(5)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpge_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" for greater-than-or-equal, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmpge_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(5)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpgt_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed 16-bit integers in ""a"" and ""b"" for greater-than, and store the results in ""dst"".
    
    __m128i _mm_cmpgt_epi16 (__m128i a,  __m128i b)
    PCMPGTW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpgt_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed 32-bit integers in ""a"" and ""b"" for greater-than, and store the results in ""dst"".
    
    __m128i _mm_cmpgt_epi32 (__m128i a,  __m128i b)
    PCMPGTD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpgt_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed 8-bit integers in ""a"" and ""b"" for greater-than, and store the results in ""dst"".
    
    __m128i _mm_cmpgt_epi8 (__m128i a,  __m128i b)
    PCMPGTB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpgt_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" for greater-than, and store the results in ""dst"".
    
    __m128d _mm_cmpgt_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(6)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpgt_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" for greater-than, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmpgt_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(6)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmple_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" for less-than-or-equal, and store the results in ""dst"".
    
    __m128d _mm_cmple_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(2)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmple_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" for less-than-or-equal, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmple_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(2)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmplt_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed 16-bit integers in ""a"" and ""b"" for less-than, and store the results in ""dst"". Note: This intrinsic emits the pcmpgtw instruction with the order of the operands switched.
    
    __m128i _mm_cmplt_epi16 (__m128i a,  __m128i b)
    PCMPGTW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmplt_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed 32-bit integers in ""a"" and ""b"" for less-than, and store the results in ""dst"". Note: This intrinsic emits the pcmpgtd instruction with the order of the operands switched.
    
    __m128i _mm_cmplt_epi32 (__m128i a,  __m128i b)
    PCMPGTD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmplt_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed 8-bit integers in ""a"" and ""b"" for less-than, and store the results in ""dst"". Note: This intrinsic emits the pcmpgtb instruction with the order of the operands switched.
    
    __m128i _mm_cmplt_epi8 (__m128i a,  __m128i b)
    PCMPGTB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmplt_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" for less-than, and store the results in ""dst"".
    
    __m128d _mm_cmplt_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(1)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmplt_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" for less-than, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmplt_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(1)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpneq_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" for not-equal, and store the results in ""dst"".
    
    __m128d _mm_cmpneq_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpneq_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" for not-equal, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmpneq_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnge_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" for not-greater-than-or-equal, and store the results in ""dst"".
    
    __m128d _mm_cmpnge_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(1)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnge_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" for not-greater-than-or-equal, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmpnge_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(1)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpngt_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" for not-greater-than, and store the results in ""dst"".
    
    __m128d _mm_cmpngt_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(2)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpngt_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" for not-greater-than, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmpngt_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(2)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnle_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" for not-less-than-or-equal, and store the results in ""dst"".
    
    __m128d _mm_cmpnle_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(6)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnle_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" for not-less-than-or-equal, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmpnle_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(6)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnlt_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" for not-less-than, and store the results in ""dst"".
    
    __m128d _mm_cmpnlt_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(5)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnlt_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" for not-less-than, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmpnlt_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(5)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpord_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" to see if neither is NaN, and store the results in ""dst"".
    
    __m128d _mm_cmpord_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(7)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpord_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" to see if neither is NaN, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmpord_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(7)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpunord_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" to see if either is NaN, and store the results in ""dst"".
    
    __m128d _mm_cmpunord_pd (__m128d a,  __m128d b)
    CMPPD xmm, xmm/m128, imm8(3)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpunord_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"" to see if either is NaN, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cmpunord_sd (__m128d a,  __m128d b)
    CMPSD xmm, xmm/m64, imm8(3)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comieq_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for equality, and return the boolean result (0 or 1).
    
    int _mm_comieq_sd (__m128d a, __m128d b)
    COMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comige_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for greater-than-or-equal, and return the boolean result (0 or 1).
    
    int _mm_comige_sd (__m128d a, __m128d b)
    COMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comigt_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for greater-than, and return the boolean result (0 or 1).
    
    int _mm_comigt_sd (__m128d a, __m128d b)
    COMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comile_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for less-than-or-equal, and return the boolean result (0 or 1).
    
    int _mm_comile_sd (__m128d a, __m128d b)
    COMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comilt_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for less-than, and return the boolean result (0 or 1).
    
    int _mm_comilt_sd (__m128d a, __m128d b)
    COMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comineq_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for not-equal, and return the boolean result (0 or 1).
    
    int _mm_comineq_sd (__m128d a, __m128d b)
    COMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepi32_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert packed 32-bit integers in ""a"" to packed double-precision (64-bit) floating-point elements, and store the results in ""dst"".
    
    __m128d _mm_cvtepi32_pd (__m128i a)
    CVTDQ2PD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepi32_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert packed 32-bit integers in ""a"" to packed single-precision (32-bit) floating-point elements, and store the results in ""dst"".
    
    __m128 _mm_cvtepi32_ps (__m128i a)
    CVTDQ2PS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtpd_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert packed double-precision (64-bit) floating-point elements in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtpd_epi32 (__m128d a)
    CVTPD2DQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtpd_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert packed double-precision (64-bit) floating-point elements in ""a"" to packed single-precision (32-bit) floating-point elements, and store the results in ""dst"".
    
    __m128 _mm_cvtpd_ps (__m128d a)
    CVTPD2PS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtps_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert packed single-precision (32-bit) floating-point elements in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtps_epi32 (__m128 a)
    CVTPS2DQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtps_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert packed single-precision (32-bit) floating-point elements in ""a"" to packed double-precision (64-bit) floating-point elements, and store the results in ""dst"".
    
    __m128d _mm_cvtps_pd (__m128 a)
    CVTPS2PD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtsd_si32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert the lower double-precision (64-bit) floating-point element in ""a"" to a 32-bit integer, and store the result in ""dst"".
    
    int _mm_cvtsd_si32 (__m128d a)
    CVTSD2SI r32, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtsd_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert the lower double-precision (64-bit) floating-point element in ""b"" to a single-precision (32-bit) floating-point element, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128 _mm_cvtsd_ss (__m128 a, __m128d b)
    CVTSD2SS xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtsi128_si32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Copy the lower 32-bit integer in ""a"" to ""dst"".
    
    int _mm_cvtsi128_si32 (__m128i a)
    MOVD reg/m32, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtsi32_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert the 32-bit integer ""b"" to a double-precision (64-bit) floating-point element, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cvtsi32_sd (__m128d a, int b)
    CVTSI2SD xmm, reg/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtsi32_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Copy 32-bit integer ""a"" to the lower elements of ""dst"", and zero the upper elements of ""dst"".
    
    __m128i _mm_cvtsi32_si128 (int a)
    MOVD xmm, reg/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtss_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert the lower single-precision (32-bit) floating-point element in ""b"" to a double-precision (64-bit) floating-point element, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cvtss_sd (__m128d a, __m128 b)
    CVTSS2SD xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvttpd_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert packed double-precision (64-bit) floating-point elements in ""a"" to packed 32-bit integers with truncation, and store the results in ""dst"".
    
    __m128i _mm_cvttpd_epi32 (__m128d a)
    CVTTPD2DQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvttps_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert packed single-precision (32-bit) floating-point elements in ""a"" to packed 32-bit integers with truncation, and store the results in ""dst"".
    
    __m128i _mm_cvttps_epi32 (__m128 a)
    CVTTPS2DQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvttsd_si32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert the lower double-precision (64-bit) floating-point element in ""a"" to a 32-bit integer with truncation, and store the result in ""dst"".
    
    int _mm_cvttsd_si32 (__m128d a)
    CVTTSD2SI reg, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_div_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Divide packed double-precision (64-bit) floating-point elements in ""a"" by packed elements in ""b"", and store the results in ""dst"".
    
    __m128d _mm_div_pd (__m128d a,  __m128d b)
    DIVPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_div_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Divide the lower double-precision (64-bit) floating-point element in ""a"" by the lower double-precision (64-bit) floating-point element in ""b"", store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_div_sd (__m128d a,  __m128d b)
    DIVSD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_extract_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Extract a 16-bit integer from ""a"", selected with ""imm8"", and store the result in the lower element of ""dst"".
    
    int _mm_extract_epi16 (__m128i a,  int immediate)
    PEXTRW reg, xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_insert_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Copy ""a"" to ""dst"", and insert the 16-bit integer ""i"" into ""dst"" at the location specified by ""imm8"".
    
    __m128i _mm_insert_epi16 (__m128i a,  int i, int immediate)
    PINSRW xmm, reg/m16, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_load_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into ""dst"".
    	""mem_addr"" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
    
    __m128d _mm_load_pd (double const* mem_address)
    MOVAPD xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_load_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Load a double-precision (64-bit) floating-point element from memory into the lower of ""dst"", and zero the upper element. ""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m128d _mm_load_sd (double const* mem_address)
    MOVSD xmm, m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_load_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Load 128-bits of integer data from memory into ""dst"". 
    	""mem_addr"" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
    
    __m128i _mm_load_si128 (__m128i const* mem_address)
    MOVDQA xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_loadh_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Load a double-precision (64-bit) floating-point element from memory into the upper element of ""dst"", and copy the lower element from ""a"" to ""dst"". ""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m128d _mm_loadh_pd (__m128d a, double const* mem_addr)
    MOVHPD xmm, m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_loadl_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"__m128i _mm_loadl_epi32 (__m128i const* mem_addr)
    MOVD xmm, reg/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_loadl_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Load 64-bit integer from memory into the first element of ""dst"".
    
    __m128i _mm_loadl_epi64 (__m128i const* mem_addr)
    MOVQ xmm, reg/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_loadl_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Load a double-precision (64-bit) floating-point element from memory into the lower element of ""dst"", and copy the upper element from ""a"" to ""dst"". ""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m128d _mm_loadl_pd (__m128d a, double const* mem_addr)
    MOVLPD xmm, m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_loadu_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Load 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from memory into ""dst"".
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m128d _mm_loadu_pd (double const* mem_address)
    MOVUPD xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_loadu_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Load 128-bits of integer data from memory into ""dst"".
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m128i _mm_loadu_si128 (__m128i const* mem_address)
    MOVDQU xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_madd_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Multiply packed signed 16-bit integers in ""a"" and ""b"", producing intermediate signed 32-bit integers. Horizontally add adjacent pairs of intermediate 32-bit integers, and pack the results in ""dst"".
    
    __m128i _mm_madd_epi16 (__m128i a,  __m128i b)
    PMADDWD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_maskmoveu_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Conditionally store 8-bit integer elements from ""a"" into memory using ""mask"" (elements are not stored when the highest bit is not set in the corresponding element) and a non-temporal memory hint. ""mem_addr"" does not need to be aligned on any particular boundary.
    
    void _mm_maskmoveu_si128 (__m128i a,  __m128i mask, char* mem_address)
    MASKMOVDQU xmm, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_max_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed 16-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m128i _mm_max_epi16 (__m128i a,  __m128i b)
    PMAXSW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_max_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed unsigned 8-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m128i _mm_max_epu8 (__m128i a,  __m128i b)
    PMAXUB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_max_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m128d _mm_max_pd (__m128d a,  __m128d b)
    MAXPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_max_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"", store the maximum value in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_max_sd (__m128d a,  __m128d b)
    MAXSD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_min_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed 16-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m128i _mm_min_epi16 (__m128i a,  __m128i b)
    PMINSW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_min_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed unsigned 8-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m128i _mm_min_epu8 (__m128i a,  __m128i b)
    PMINUB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_min_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m128d _mm_min_pd (__m128d a,  __m128d b)
    MINPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_min_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point elements in ""a"" and ""b"", store the minimum value in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_min_sd (__m128d a,  __m128d b)
    MINSD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_move_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Copy the lower 64-bit integer in ""a"" to the lower element of ""dst"", and zero the upper element.
    
    __m128i _mm_move_epi64 (__m128i a)
    MOVQ xmm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_move_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Move the lower double-precision (64-bit) floating-point element from ""b"" to the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_move_sd (__m128d a, __m128d b)
    MOVSD xmm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_movemask_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Create mask from the most significant bit of each 8-bit element in ""a"", and store the result in ""dst"".
    
    int _mm_movemask_epi8 (__m128i a)
    PMOVMSKB reg, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_movemask_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Set each bit of mask ""dst"" based on the most significant bit of the corresponding packed double-precision (64-bit) floating-point element in ""a"".
    
    int _mm_movemask_pd (__m128d a)
    MOVMSKPD reg, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mul_epu32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Multiply the low unsigned 32-bit integers from each packed 64-bit element in ""a"" and ""b"", and store the unsigned 64-bit results in ""dst"".
    
    __m128i _mm_mul_epu32 (__m128i a,  __m128i b)
    PMULUDQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mul_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Multiply packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128d _mm_mul_pd (__m128d a,  __m128d b)
    MULPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mul_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Multiply the lower double-precision (64-bit) floating-point element in ""a"" and ""b"", store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_mul_sd (__m128d a,  __m128d b)
    MULSD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mulhi_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Multiply the packed 16-bit integers in ""a"" and ""b"", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in ""dst"".
    
    __m128i _mm_mulhi_epi16 (__m128i a,  __m128i b)
    PMULHW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mulhi_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Multiply the packed unsigned 16-bit integers in ""a"" and ""b"", producing intermediate 32-bit integers, and store the high 16 bits of the intermediate integers in ""dst"".
    
    __m128i _mm_mulhi_epu16 (__m128i a,  __m128i b)
    PMULHUW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mullo_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Multiply the packed 16-bit integers in ""a"" and ""b"", producing intermediate 32-bit integers, and store the low 16 bits of the intermediate integers in ""dst"".
    
    __m128i _mm_mullo_epi16 (__m128i a,  __m128i b)
    PMULLW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_or_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the bitwise OR of packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128d _mm_or_pd (__m128d a,  __m128d b)
    ORPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_or_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the bitwise OR of 128 bits (representing integer data) in ""a"" and ""b"", and store the result in ""dst"".
    
    __m128i _mm_or_si128 (__m128i a,  __m128i b)
    POR xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_packs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert packed 16-bit integers from ""a"" and ""b"" to packed 8-bit integers using signed saturation, and store the results in ""dst"".
    
    __m128i _mm_packs_epi16 (__m128i a,  __m128i b)
    PACKSSWB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_packs_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert packed 32-bit integers from ""a"" and ""b"" to packed 16-bit integers using signed saturation, and store the results in ""dst"".
    
    __m128i _mm_packs_epi32 (__m128i a,  __m128i b)
    PACKSSDW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_packus_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert packed 16-bit integers from ""a"" and ""b"" to packed 8-bit integers using unsigned saturation, and store the results in ""dst"".
    
    __m128i _mm_packus_epi16 (__m128i a,  __m128i b)
    PACKUSWB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sad_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the absolute differences of packed unsigned 8-bit integers in ""a"" and ""b"", then horizontally sum each consecutive 8 differences to produce two unsigned 16-bit integers, and pack these unsigned 16-bit integers in the low 16 bits of 64-bit elements in ""dst"".
    
    __m128i _mm_sad_epu8 (__m128i a,  __m128i b)
    PSADBW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_shuffle_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shuffle 32-bit integers in ""a"" using the control in ""imm8"", and store the results in ""dst"".
    
    __m128i _mm_shuffle_epi32 (__m128i a,  int immediate)
    PSHUFD xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_shuffle_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shuffle double-precision (64-bit) floating-point elements using the control in ""imm8"", and store the results in ""dst"".
    
    __m128d _mm_shuffle_pd (__m128d a,  __m128d b, int immediate)
    SHUFPD xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_shufflehi_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shuffle 16-bit integers in the high 64 bits of ""a"" using the control in ""imm8"". Store the results in the high 64 bits of ""dst"", with the low 64 bits being copied from from ""a"" to ""dst"".
    
    __m128i _mm_shufflehi_epi16 (__m128i a,  int immediate)
    PSHUFHW xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_shufflelo_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shuffle 16-bit integers in the low 64 bits of ""a"" using the control in ""imm8"". Store the results in the low 64 bits of ""dst"", with the high 64 bits being copied from from ""a"" to ""dst"".
    
    __m128i _mm_shufflelo_epi16 (__m128i a,  int control)
    PSHUFLW xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sll_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 16-bit integers in ""a"" left by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_sll_epi16 (__m128i a, __m128i count)
    PSLLW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sll_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" left by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_sll_epi32 (__m128i a, __m128i count)
    PSLLD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sll_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" left by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_sll_epi64 (__m128i a, __m128i count)
    PSLLQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_slli_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 16-bit integers in ""a"" left by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_slli_epi16 (__m128i a,  int immediate)
    PSLLW xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_slli_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" left by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_slli_epi32 (__m128i a,  int immediate)
    PSLLD xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_slli_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" left by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_slli_epi64 (__m128i a,  int immediate)
    PSLLQ xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sqrt_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the square root of packed double-precision (64-bit) floating-point elements in ""a"", and store the results in ""dst"".
    
    __m128d _mm_sqrt_pd (__m128d a)
    SQRTPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sqrt_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the square root of the lower double-precision (64-bit) floating-point element in ""b"", store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_sqrt_sd (__m128d a, __m128d b)
    SQRTSD xmm, xmm/64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sqrt_sd1"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the square root of the lower double-precision (64-bit) floating-point element in ""b"", store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_sqrt_sd (__m128d a)
    SQRTSD xmm, xmm/64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sra_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 16-bit integers in ""a"" right by ""count"" while shifting in sign bits, and store the results in ""dst"".
    
    __m128i _mm_sra_epi16 (__m128i a, __m128i count)
    PSRAW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sra_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" right by ""count"" while shifting in sign bits, and store the results in ""dst"".
    
    __m128i _mm_sra_epi32 (__m128i a, __m128i count)
    PSRAD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_srai_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 16-bit integers in ""a"" right by ""imm8"" while shifting in sign bits, and store the results in ""dst"".
    
    __m128i _mm_srai_epi16 (__m128i a,  int immediate)
    PSRAW xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_srai_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" right by ""imm8"" while shifting in sign bits, and store the results in ""dst"".
    
    __m128i _mm_srai_epi32 (__m128i a,  int immediate)
    PSRAD xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_srl_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 16-bit integers in ""a"" right by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_srl_epi16 (__m128i a, __m128i count)
    PSRLW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_srl_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" right by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_srl_epi32 (__m128i a, __m128i count)
    PSRLD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_srl_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" right by ""count"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_srl_epi64 (__m128i a, __m128i count)
    PSRLQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_srli_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 16-bit integers in ""a"" right by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_srli_epi16 (__m128i a,  int immediate)
    PSRLW xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_srli_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 32-bit integers in ""a"" right by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_srli_epi32 (__m128i a,  int immediate)
    PSRLD xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_srli_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Shift packed 64-bit integers in ""a"" right by ""imm8"" while shifting in zeros, and store the results in ""dst"".
    
    __m128i _mm_srli_epi64 (__m128i a,  int immediate)
    PSRLQ xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_store_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from ""a"" into memory.
    	""mem_addr"" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
    
    void _mm_store_pd (double* mem_addr, __m128d a)
    MOVAPD m128, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_store_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store the lower double-precision (64-bit) floating-point element from ""a"" into memory. ""mem_addr"" does not need to be aligned on any particular boundary.
    
    void _mm_store_sd (double* mem_addr, __m128d a)
    MOVSD m64, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_store_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store 128-bits of integer data from ""a"" into memory. 
    	""mem_addr"" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
    
    void _mm_store_si128 (__m128i* mem_addr, __m128i a)
    MOVDQA m128, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_storeh_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store the upper double-precision (64-bit) floating-point element from ""a"" into memory.
    
    void _mm_storeh_pd (double* mem_addr, __m128d a)
    MOVHPD m64, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_storel_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store 64-bit integer from the first element of ""a"" into memory.
    
    void _mm_storel_epi64 (__m128i* mem_addr, __m128i a)
    MOVQ m64, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_storel_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store the lower double-precision (64-bit) floating-point element from ""a"" into memory.
    
    void _mm_storel_pd (double* mem_addr, __m128d a)
    MOVLPD m64, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_storeu_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from ""a"" into memory.
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    void _mm_storeu_pd (double* mem_addr, __m128d a)
    MOVUPD m128, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_storeu_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store 128-bits of integer data from ""a"" into memory.
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    void _mm_storeu_si128 (__m128i* mem_addr, __m128i a)
    MOVDQU m128, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_storeu_si32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store 32-bit integer from the first element of ""a"" into memory. ""mem_addr"" does not need to be aligned on any particular boundary.
    
    void _mm_storeu_si32 (void* mem_addr, __m128i a) MOVD m32, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_stream_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store 128-bits (composed of 2 packed double-precision (64-bit) floating-point elements) from ""a"" into memory using a non-temporal memory hint.
    	""mem_addr"" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
    
    void _mm_stream_pd (double* mem_addr, __m128d a)
    MOVNTPD m128, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_stream_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store 128-bits of integer data from ""a"" into memory using a non-temporal memory hint. 
    	""mem_addr"" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
    
    void _mm_stream_si128 (__m128i* mem_addr, __m128i a)
    MOVNTDQ m128, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_stream_si32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store 32-bit integer ""a"" into memory using a non-temporal hint to minimize cache pollution. If the cache line containing address ""mem_addr"" is already in the cache, the cache will be updated.
    
    void _mm_stream_si32(int *p, int a)
    MOVNTI m32, r32";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_sub_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Subtract packed 16-bit integers in ""b"" from packed 16-bit integers in ""a"", and store the results in ""dst"".
    
    __m128i _mm_sub_epi16 (__m128i a,  __m128i b)
    PSUBW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sub_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Subtract packed 32-bit integers in ""b"" from packed 32-bit integers in ""a"", and store the results in ""dst"".
    
    __m128i _mm_sub_epi32 (__m128i a,  __m128i b)
    PSUBD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sub_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Subtract packed 64-bit integers in ""b"" from packed 64-bit integers in ""a"", and store the results in ""dst"".
    
    __m128i _mm_sub_epi64 (__m128i a,  __m128i b)
    PSUBQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sub_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Subtract packed 8-bit integers in ""b"" from packed 8-bit integers in ""a"", and store the results in ""dst"".
    
    __m128i _mm_sub_epi8 (__m128i a,  __m128i b)
    PSUBB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sub_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Subtract packed double-precision (64-bit) floating-point elements in ""b"" from packed double-precision (64-bit) floating-point elements in ""a"", and store the results in ""dst"".
    
    __m128d _mm_sub_pd (__m128d a, __m128d b)
    SUBPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sub_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Subtract the lower double-precision (64-bit) floating-point element in ""b"" from the lower double-precision (64-bit) floating-point element in ""a"", store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_sub_sd (__m128d a, __m128d b)
    SUBSD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_subs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Subtract packed 16-bit integers in ""b"" from packed 16-bit integers in ""a"" using saturation, and store the results in ""dst"".
    
    __m128i _mm_subs_epi16 (__m128i a,  __m128i b)
    PSUBSW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_subs_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Subtract packed 8-bit integers in ""b"" from packed 8-bit integers in ""a"" using saturation, and store the results in ""dst"".
    
    __m128i _mm_subs_epi8 (__m128i a,  __m128i b)
    PSUBSB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_subs_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Subtract packed unsigned 16-bit integers in ""b"" from packed unsigned 16-bit integers in ""a"" using saturation, and store the results in ""dst"".
    
    __m128i _mm_subs_epu16 (__m128i a,  __m128i b)
    PSUBUSW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_subs_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Subtract packed unsigned 8-bit integers in ""b"" from packed unsigned 8-bit integers in ""a"" using saturation, and store the results in ""dst"".
    
    __m128i _mm_subs_epu8 (__m128i a,  __m128i b)
    PSUBUSB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomieq_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for equality, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomieq_sd (__m128d a, __m128d b)
    UCOMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomige_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for greater-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomige_sd (__m128d a, __m128d b)
    UCOMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomigt_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for greater-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomigt_sd (__m128d a, __m128d b)
    UCOMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomile_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for less-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomile_sd (__m128d a, __m128d b)
    UCOMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomilt_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for less-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomilt_sd (__m128d a, __m128d b)
    UCOMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomineq_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compare the lower double-precision (64-bit) floating-point element in ""a"" and ""b"" for not-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomineq_sd (__m128d a, __m128d b)
    UCOMISD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpackhi_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Unpack and interleave 16-bit integers from the high half of ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_unpackhi_epi16 (__m128i a,  __m128i b)
    PUNPCKHWD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpackhi_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Unpack and interleave 32-bit integers from the high half of ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_unpackhi_epi32 (__m128i a,  __m128i b)
    PUNPCKHDQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpackhi_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Unpack and interleave 64-bit integers from the high half of ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_unpackhi_epi64 (__m128i a,  __m128i b)
    PUNPCKHQDQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpackhi_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Unpack and interleave 8-bit integers from the high half of ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_unpackhi_epi8 (__m128i a,  __m128i b)
    PUNPCKHBW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpackhi_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Unpack and interleave double-precision (64-bit) floating-point elements from the high half of ""a"" and ""b"", and store the results in ""dst"".
    
    __m128d _mm_unpackhi_pd (__m128d a,  __m128d b)
    UNPCKHPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpacklo_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Unpack and interleave 16-bit integers from the low half of ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_unpacklo_epi16 (__m128i a,  __m128i b)
    PUNPCKLWD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpacklo_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Unpack and interleave 32-bit integers from the low half of ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_unpacklo_epi32 (__m128i a,  __m128i b)
    PUNPCKLDQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpacklo_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Unpack and interleave 64-bit integers from the low half of ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_unpacklo_epi64 (__m128i a,  __m128i b)
    PUNPCKLQDQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpacklo_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Unpack and interleave 8-bit integers from the low half of ""a"" and ""b"", and store the results in ""dst"".
    
    __m128i _mm_unpacklo_epi8 (__m128i a,  __m128i b)
    PUNPCKLBW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpacklo_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Unpack and interleave double-precision (64-bit) floating-point elements from the low half of ""a"" and ""b"", and store the results in ""dst"".
    
    __m128d _mm_unpacklo_pd (__m128d a,  __m128d b)
    UNPCKLPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_xor_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the bitwise XOR of packed double-precision (64-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128d _mm_xor_pd (__m128d a,  __m128d b)
    XORPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_xor_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Compute the bitwise XOR of 128 bits (representing integer data) in ""a"" and ""b"", and store the result in ""dst"".
    
    __m128i _mm_xor_si128 (__m128i a,  __m128i b)
    PXOR xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Sse2X64IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_cvtsd_si64", (Func<object, long>)mm_cvtsd_si64);
            RegisterFunction("mm_cvtsi128_si64", (Func<object, long>)mm_cvtsi128_si64);
            RegisterFunction("mm_cvtsi64_sd", (Func<object, long, object>)mm_cvtsi64_sd);
            RegisterFunction("mm_cvtsi64_si128", (Func<long, object>)mm_cvtsi64_si128);
            RegisterFunction("mm_cvttsd_si64", (Func<object, long>)mm_cvttsd_si64);
            RegisterAction("mm_stream_si64", (Action<object, long>)mm_stream_si64);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_cvtsd_si64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert the lower double-precision (64-bit) floating-point element in ""a"" to a 64-bit integer, and store the result in ""dst"".
    
    __int64 _mm_cvtsd_si64 (__m128d a)
    CVTSD2SI r64, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtsi128_si64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Copy the lower 64-bit integer in ""a"" to ""dst"".
    
    __int64 _mm_cvtsi128_si64 (__m128i a)
    MOVQ reg/m64, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtsi64_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert the 64-bit integer ""b"" to a double-precision (64-bit) floating-point element, store the result in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_cvtsi64_sd (__m128d a, __int64 b)
    CVTSI2SD xmm, reg/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtsi64_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Copy 64-bit integer ""a"" to the lower element of ""dst"", and zero the upper element.
    
    __m128i _mm_cvtsi64_si128 (__int64 a)
    MOVQ xmm, reg/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvttsd_si64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Convert the lower double-precision (64-bit) floating-point element in ""a"" to a 64-bit integer with truncation, and store the result in ""dst"".
    
    __int64 _mm_cvttsd_si64 (__m128d a)
    CVTTSD2SI reg, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_stream_si64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE2";
                descriptor.Description = @"Store 64-bit integer ""a"" into memory using a non-temporal hint to minimize cache pollution. If the cache line containing address ""mem_addr"" is already in the cache, the cache will be updated.
    
    void _mm_stream_si64(__int64 *p, __int64 a)
    MOVNTI m64, r64";
                descriptor.IsCommand = true;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Sse3IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_addsub_pd", (Func<object, object, object>)mm_addsub_pd);
            RegisterFunction("mm_addsub_ps", (Func<object, object, object>)mm_addsub_ps);
            RegisterFunction("mm_hadd_pd", (Func<object, object, object>)mm_hadd_pd);
            RegisterFunction("mm_hadd_ps", (Func<object, object, object>)mm_hadd_ps);
            RegisterFunction("mm_hsub_pd", (Func<object, object, object>)mm_hsub_pd);
            RegisterFunction("mm_hsub_ps", (Func<object, object, object>)mm_hsub_ps);
            RegisterFunction("mm_lddqu_si128", (Func<object, object>)mm_lddqu_si128);
            RegisterFunction("mm_loaddup_pd", (Func<object, object>)mm_loaddup_pd);
            RegisterFunction("mm_movedup_pd", (Func<object, object>)mm_movedup_pd);
            RegisterFunction("mm_movehdup_ps", (Func<object, object>)mm_movehdup_ps);
            RegisterFunction("mm_moveldup_ps", (Func<object, object>)mm_moveldup_ps);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_addsub_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE3";
                descriptor.Description = @"Alternatively add and subtract packed double-precision (64-bit) floating-point elements in ""a"" to/from packed elements in ""b"", and store the results in ""dst"".
    
    __m128d _mm_addsub_pd (__m128d a, __m128d b)
    ADDSUBPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_addsub_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE3";
                descriptor.Description = @"Alternatively add and subtract packed single-precision (32-bit) floating-point elements in ""a"" to/from packed elements in ""b"", and store the results in ""dst"".
    
    __m128 _mm_addsub_ps (__m128 a, __m128 b)
    ADDSUBPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_hadd_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE3";
                descriptor.Description = @"Horizontally add adjacent pairs of double-precision (64-bit) floating-point elements in ""a"" and ""b"", and pack the results in ""dst"".
    
    __m128d _mm_hadd_pd (__m128d a, __m128d b)
    HADDPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_hadd_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE3";
                descriptor.Description = @"Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in ""a"" and ""b"", and pack the results in ""dst"".
    
    __m128 _mm_hadd_ps (__m128 a, __m128 b)
    HADDPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_hsub_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE3";
                descriptor.Description = @"Horizontally subtract adjacent pairs of double-precision (64-bit) floating-point elements in ""a"" and ""b"", and pack the results in ""dst"".
    
    __m128d _mm_hsub_pd (__m128d a, __m128d b)
    HSUBPD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_hsub_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE3";
                descriptor.Description = @"Horizontally add adjacent pairs of single-precision (32-bit) floating-point elements in ""a"" and ""b"", and pack the results in ""dst"".
    
    __m128 _mm_hsub_ps (__m128 a, __m128 b)
    HSUBPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_lddqu_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE3";
                descriptor.Description = @"Load 128-bits of integer data from unaligned memory into ""dst"". This intrinsic may perform better than ""_mm_loadu_si128"" when the data crosses a cache line boundary.
    
    __m128i _mm_lddqu_si128 (__m128i const* mem_addr)
    LDDQU xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_loaddup_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE3";
                descriptor.Description = @"Load a double-precision (64-bit) floating-point element from memory into both elements of ""dst"".
    
    __m128d _mm_loaddup_pd (double const* mem_addr)
    MOVDDUP xmm, m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_movedup_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE3";
                descriptor.Description = @"Duplicate the low double-precision (64-bit) floating-point element from ""a"", and store the results in ""dst"".
    
    __m128d _mm_movedup_pd (__m128d a)
    MOVDDUP xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_movehdup_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE3";
                descriptor.Description = @"Duplicate odd-indexed single-precision (32-bit) floating-point elements from ""a"", and store the results in ""dst"".
    
    __m128 _mm_movehdup_ps (__m128 a)
    MOVSHDUP xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_moveldup_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE3";
                descriptor.Description = @"Duplicate even-indexed single-precision (32-bit) floating-point elements from ""a"", and store the results in ""dst"".
    
    __m128 _mm_moveldup_ps (__m128 a)
    MOVSLDUP xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Sse41IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_blend_epi16", (Func<object, object, byte, object>)mm_blend_epi16);
            RegisterFunction("mm_blend_pd", (Func<object, object, byte, object>)mm_blend_pd);
            RegisterFunction("mm_blend_ps", (Func<object, object, byte, object>)mm_blend_ps);
            RegisterFunction("mm_blendv_epi8", (Func<object, object, object, object>)mm_blendv_epi8);
            RegisterFunction("mm_blendv_pd", (Func<object, object, object, object>)mm_blendv_pd);
            RegisterFunction("mm_blendv_ps", (Func<object, object, object, object>)mm_blendv_ps);
            RegisterFunction("mm_ceil_pd", (Func<object, object>)mm_ceil_pd);
            RegisterFunction("mm_ceil_ps", (Func<object, object>)mm_ceil_ps);
            RegisterFunction("mm_ceil_sd", (Func<object, object, object>)mm_ceil_sd);
            RegisterFunction("mm_ceil_sd1", (Func<object, object>)mm_ceil_sd1);
            RegisterFunction("mm_ceil_ss", (Func<object, object, object>)mm_ceil_ss);
            RegisterFunction("mm_cmpeq_epi64", (Func<object, object, object>)mm_cmpeq_epi64);
            RegisterFunction("mm_cvtepi16_epi32", (Func<object, object>)mm_cvtepi16_epi32);
            RegisterFunction("mm_cvtepi16_epi64", (Func<object, object>)mm_cvtepi16_epi64);
            RegisterFunction("mm_cvtepi32_epi64", (Func<object, object>)mm_cvtepi32_epi64);
            RegisterFunction("mm_cvtepi8_epi16", (Func<object, object>)mm_cvtepi8_epi16);
            RegisterFunction("mm_cvtepi8_epi32", (Func<object, object>)mm_cvtepi8_epi32);
            RegisterFunction("mm_cvtepi8_epi64", (Func<object, object>)mm_cvtepi8_epi64);
            RegisterFunction("mm_cvtepu16_epi32", (Func<object, object>)mm_cvtepu16_epi32);
            RegisterFunction("mm_cvtepu16_epi64", (Func<object, object>)mm_cvtepu16_epi64);
            RegisterFunction("mm_cvtepu32_epi64", (Func<object, object>)mm_cvtepu32_epi64);
            RegisterFunction("mm_cvtepu8_epi16", (Func<object, object>)mm_cvtepu8_epi16);
            RegisterFunction("mm_cvtepu8_epi32", (Func<object, object>)mm_cvtepu8_epi32);
            RegisterFunction("mm_cvtepu8_epi64", (Func<object, object>)mm_cvtepu8_epi64);
            RegisterFunction("mm_dp_pd", (Func<object, object, byte, object>)mm_dp_pd);
            RegisterFunction("mm_dp_ps", (Func<object, object, byte, object>)mm_dp_ps);
            RegisterFunction("mm_extract_epi32", (Func<object, byte, int>)mm_extract_epi32);
            RegisterFunction("mm_extract_epi8", (Func<object, byte, byte>)mm_extract_epi8);
            RegisterFunction("mm_extract_ps", (Func<object, byte, float>)mm_extract_ps);
            RegisterFunction("mm_floor_pd", (Func<object, object>)mm_floor_pd);
            RegisterFunction("mm_floor_ps", (Func<object, object>)mm_floor_ps);
            RegisterFunction("mm_floor_sd", (Func<object, object, object>)mm_floor_sd);
            RegisterFunction("mm_floor_sd1", (Func<object, object>)mm_floor_sd1);
            RegisterFunction("mm_floor_ss", (Func<object, object, object>)mm_floor_ss);
            RegisterFunction("mm_insert_epi32", (Func<object, int, byte, object>)mm_insert_epi32);
            RegisterFunction("mm_insert_epi8", (Func<object, byte, byte, object>)mm_insert_epi8);
            RegisterFunction("mm_insert_ps", (Func<object, object, byte, object>)mm_insert_ps);
            RegisterFunction("mm_max_epi32", (Func<object, object, object>)mm_max_epi32);
            RegisterFunction("mm_max_epi8", (Func<object, object, object>)mm_max_epi8);
            RegisterFunction("mm_max_epu16", (Func<object, object, object>)mm_max_epu16);
            RegisterFunction("mm_max_epu32", (Func<object, object, object>)mm_max_epu32);
            RegisterFunction("mm_min_epi32", (Func<object, object, object>)mm_min_epi32);
            RegisterFunction("mm_min_epi8", (Func<object, object, object>)mm_min_epi8);
            RegisterFunction("mm_min_epu16", (Func<object, object, object>)mm_min_epu16);
            RegisterFunction("mm_min_epu32", (Func<object, object, object>)mm_min_epu32);
            RegisterFunction("mm_minpos_epu16", (Func<object, object>)mm_minpos_epu16);
            RegisterFunction("mm_mpsadbw_epu8", (Func<object, object, byte, object>)mm_mpsadbw_epu8);
            RegisterFunction("mm_mul_epi32", (Func<object, object, object>)mm_mul_epi32);
            RegisterFunction("mm_mullo_epi32", (Func<object, object, object>)mm_mullo_epi32);
            RegisterFunction("mm_packus_epi32", (Func<object, object, object>)mm_packus_epi32);
            RegisterFunction("mm_round_pd1", (Func<object, object>)mm_round_pd1);
            RegisterFunction("mm_round_pd1_to_nearest_integer", (Func<object, object>)mm_round_pd1_to_nearest_integer);
            RegisterFunction("mm_round_pd1_to_negative_infinity", (Func<object, object>)mm_round_pd1_to_negative_infinity);
            RegisterFunction("mm_round_pd1_to_positive_infinity", (Func<object, object>)mm_round_pd1_to_positive_infinity);
            RegisterFunction("mm_round_pd1_to_zero", (Func<object, object>)mm_round_pd1_to_zero);
            RegisterFunction("mm_round_ps", (Func<object, object>)mm_round_ps);
            RegisterFunction("mm_round_ps_to_nearest_integer", (Func<object, object>)mm_round_ps_to_nearest_integer);
            RegisterFunction("mm_round_ps_to_negative_infinity", (Func<object, object>)mm_round_ps_to_negative_infinity);
            RegisterFunction("mm_round_ps_to_positive_infinity", (Func<object, object>)mm_round_ps_to_positive_infinity);
            RegisterFunction("mm_round_ps_to_zero", (Func<object, object>)mm_round_ps_to_zero);
            RegisterFunction("mm_round_sd", (Func<object, object, object>)mm_round_sd);
            RegisterFunction("mm_round_sd_to_nearest_integer_scalar", (Func<object, object, object>)mm_round_sd_to_nearest_integer_scalar);
            RegisterFunction("mm_round_sd_to_negative_infinity_scalar", (Func<object, object, object>)mm_round_sd_to_negative_infinity_scalar);
            RegisterFunction("mm_round_sd_to_positive_infinity_scalar", (Func<object, object, object>)mm_round_sd_to_positive_infinity_scalar);
            RegisterFunction("mm_round_sd_to_zero_scalar", (Func<object, object, object>)mm_round_sd_to_zero_scalar);
            RegisterFunction("mm_round_sd1", (Func<object, object>)mm_round_sd1);
            RegisterFunction("mm_round_sd1_to_nearest_integer_scalar", (Func<object, object>)mm_round_sd1_to_nearest_integer_scalar);
            RegisterFunction("mm_round_sd1_to_negative_infinity_scalar", (Func<object, object>)mm_round_sd1_to_negative_infinity_scalar);
            RegisterFunction("mm_round_sd1_to_positive_infinity_scalar", (Func<object, object>)mm_round_sd1_to_positive_infinity_scalar);
            RegisterFunction("mm_round_sd1_to_zero_scalar", (Func<object, object>)mm_round_sd1_to_zero_scalar);
            RegisterFunction("mm_round_ss", (Func<object, object, object>)mm_round_ss);
            RegisterFunction("mm_round_ss_to_nearest_integer_scalar", (Func<object, object, object>)mm_round_ss_to_nearest_integer_scalar);
            RegisterFunction("mm_round_ss_to_negative_infinity_scalar", (Func<object, object, object>)mm_round_ss_to_negative_infinity_scalar);
            RegisterFunction("mm_round_ss_to_positive_infinity_scalar", (Func<object, object, object>)mm_round_ss_to_positive_infinity_scalar);
            RegisterFunction("mm_round_ss_to_zero_scalar", (Func<object, object, object>)mm_round_ss_to_zero_scalar);
            RegisterFunction("mm_round_ss1", (Func<object, object>)mm_round_ss1);
            RegisterFunction("mm_round_ss1_to_nearest_integer_scalar", (Func<object, object>)mm_round_ss1_to_nearest_integer_scalar);
            RegisterFunction("mm_round_ss1_to_negative_infinity_scalar", (Func<object, object>)mm_round_ss1_to_negative_infinity_scalar);
            RegisterFunction("mm_round_ss1_to_positive_infinity_scalar", (Func<object, object>)mm_round_ss1_to_positive_infinity_scalar);
            RegisterFunction("mm_round_ss1_to_zero_scalar", (Func<object, object>)mm_round_ss1_to_zero_scalar);
            RegisterFunction("mm_stream_load_si128", (Func<object, object>)mm_stream_load_si128);
            RegisterFunction("mm_testc_si128", (Func<object, object, Kalk.Core.KalkBool>)mm_testc_si128);
            RegisterFunction("mm_testnzc_si128", (Func<object, object, Kalk.Core.KalkBool>)mm_testnzc_si128);
            RegisterFunction("mm_testz_si128", (Func<object, object, Kalk.Core.KalkBool>)mm_testz_si128);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_blend_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Blend packed 16-bit integers from ""a"" and ""b"" using control mask ""imm8"", and store the results in ""dst"".
    
    __m128i _mm_blend_epi16 (__m128i a, __m128i b, const int imm8)
    PBLENDW xmm, xmm/m128 imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_blend_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Blend packed double-precision (64-bit) floating-point elements from ""a"" and ""b"" using control mask ""imm8"", and store the results in ""dst"".
    
    __m128d _mm_blend_pd (__m128d a, __m128d b, const int imm8)
    BLENDPD xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_blend_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Blend packed single-precision (32-bit) floating-point elements from ""a"" and ""b"" using control mask ""imm8"", and store the results in ""dst"".
    
    __m128 _mm_blend_ps (__m128 a, __m128 b, const int imm8)
    BLENDPS xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_blendv_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Blend packed 8-bit integers from ""a"" and ""b"" using ""mask"", and store the results in ""dst"".
    
    __m128i _mm_blendv_epi8 (__m128i a, __m128i b, __m128i mask)
    PBLENDVB xmm, xmm/m128, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_blendv_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Blend packed double-precision (64-bit) floating-point elements from ""a"" and ""b"" using ""mask"", and store the results in ""dst"".
    
    __m128d _mm_blendv_pd (__m128d a, __m128d b, __m128d mask)
    BLENDVPD xmm, xmm/m128, xmm0";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_blendv_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Blend packed single-precision (32-bit) floating-point elements from ""a"" and ""b"" using ""mask"", and store the results in ""dst"".
    
    __m128 _mm_blendv_ps (__m128 a, __m128 b, __m128 mask)
    BLENDVPS xmm, xmm/m128, xmm0";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ceil_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" up to an integer value, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m128d _mm_ceil_pd (__m128d a)
    ROUNDPD xmm, xmm/m128, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ceil_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" up to an integer value, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m128 _mm_ceil_ps (__m128 a)
    ROUNDPS xmm, xmm/m128, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ceil_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" up to an integer value, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_ceil_sd (__m128d a, __m128d b)
    ROUNDSD xmm, xmm/m128, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ceil_sd1"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" up to an integer value, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_ceil_sd (__m128d a)
    ROUNDSD xmm, xmm/m128, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ceil_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" up to an integer value, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_ceil_ss (__m128 a, __m128 b)
    ROUNDSS xmm, xmm/m128, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpeq_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compare packed 64-bit integers in ""a"" and ""b"" for equality, and store the results in ""dst"".
    
    __m128i _mm_cmpeq_epi64 (__m128i a, __m128i b)
    PCMPEQQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepi16_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Sign extend packed 16-bit integers in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepi16_epi32 (__m128i a)
    PMOVSXWD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepi16_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Sign extend packed 16-bit integers in ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepi16_epi64 (__m128i a)
    PMOVSXWQ xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepi32_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Sign extend packed 32-bit integers in ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepi32_epi64 (__m128i a)
    PMOVSXDQ xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepi8_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Sign extend packed 8-bit integers in ""a"" to packed 16-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepi8_epi16 (__m128i a)
    PMOVSXBW xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepi8_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Sign extend packed 8-bit integers in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepi8_epi32 (__m128i a)
    PMOVSXBD xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepi8_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Sign extend packed 8-bit integers in the low 8 bytes of ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepi8_epi64 (__m128i a)
    PMOVSXBQ xmm, xmm/m16";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepu16_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Zero extend packed unsigned 16-bit integers in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepu16_epi32 (__m128i a)
    PMOVZXWD xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepu16_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Zero extend packed unsigned 16-bit integers in ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepu16_epi64 (__m128i a)
    PMOVZXWQ xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepu32_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Zero extend packed unsigned 32-bit integers in ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepu32_epi64 (__m128i a)
    PMOVZXDQ xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepu8_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Zero extend packed unsigned 8-bit integers in ""a"" to packed 16-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepu8_epi16 (__m128i a)
    PMOVZXBW xmm, xmm/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepu8_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Zero extend packed unsigned 8-bit integers in ""a"" to packed 32-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepu8_epi32 (__m128i a)
    PMOVZXBD xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtepu8_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Zero extend packed unsigned 8-bit integers in the low 8 byte sof ""a"" to packed 64-bit integers, and store the results in ""dst"".
    
    __m128i _mm_cvtepu8_epi64 (__m128i a)
    PMOVZXBQ xmm, xmm/m16";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_dp_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Conditionally multiply the packed double-precision (64-bit) floating-point elements in ""a"" and ""b"" using the high 4 bits in ""imm8"", sum the four products, and conditionally store the sum in ""dst"" using the low 4 bits of ""imm8"".
    
    __m128d _mm_dp_pd (__m128d a, __m128d b, const int imm8)
    DPPD xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_dp_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Conditionally multiply the packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" using the high 4 bits in ""imm8"", sum the four products, and conditionally store the sum in ""dst"" using the low 4 bits of ""imm8"".
    
    __m128 _mm_dp_ps (__m128 a, __m128 b, const int imm8)
    DPPS xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_extract_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Extract a 32-bit integer from ""a"", selected with ""imm8"", and store the result in ""dst"".
    
    int _mm_extract_epi32 (__m128i a, const int imm8)
    PEXTRD reg/m32, xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_extract_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Extract an 8-bit integer from ""a"", selected with ""imm8"", and store the result in the lower element of ""dst"".
    
    int _mm_extract_epi8 (__m128i a, const int imm8)
    PEXTRB reg/m8, xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_extract_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Extract a single-precision (32-bit) floating-point element from ""a"", selected with ""imm8"", and store the result in ""dst"".
    
    int _mm_extract_ps (__m128 a, const int imm8)
    EXTRACTPS xmm, xmm/m32, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_floor_pd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" down to an integer value, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m128d _mm_floor_pd (__m128d a)
    ROUNDPD xmm, xmm/m128, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_floor_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" down to an integer value, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m128 _mm_floor_ps (__m128 a)
    ROUNDPS xmm, xmm/m128, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_floor_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" down to an integer value, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_floor_sd (__m128d a, __m128d b)
    ROUNDSD xmm, xmm/m128, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_floor_sd1"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" down to an integer value, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_floor_sd (__m128d a)
    ROUNDSD xmm, xmm/m128, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_floor_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" down to an integer value, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_floor_ss (__m128 a, __m128 b)
    ROUNDSS xmm, xmm/m128, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_insert_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Copy ""a"" to ""dst"", and insert the 32-bit integer ""i"" into ""dst"" at the location specified by ""imm8"".
    
    __m128i _mm_insert_epi32 (__m128i a, int i, const int imm8)
    PINSRD xmm, reg/m32, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_insert_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Copy ""a"" to ""dst"", and insert the lower 8-bit integer from ""i"" into ""dst"" at the location specified by ""imm8"".
    
    __m128i _mm_insert_epi8 (__m128i a, int i, const int imm8)
    PINSRB xmm, reg/m8, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_insert_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Copy ""a"" to ""tmp"", then insert a single-precision (32-bit) floating-point element from ""b"" into ""tmp"" using the control in ""imm8"". Store ""tmp"" to ""dst"" using the mask in ""imm8"" (elements are zeroed out when the corresponding bit is set).
    
    __m128 _mm_insert_ps (__m128 a, __m128 b, const int imm8)
    INSERTPS xmm, xmm/m32, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_max_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compare packed 32-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m128i _mm_max_epi32 (__m128i a, __m128i b)
    PMAXSD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_max_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compare packed 8-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m128i _mm_max_epi8 (__m128i a, __m128i b)
    PMAXSB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_max_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compare packed unsigned 16-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m128i _mm_max_epu16 (__m128i a, __m128i b)
    PMAXUW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_max_epu32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compare packed unsigned 32-bit integers in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m128i _mm_max_epu32 (__m128i a, __m128i b)
    PMAXUD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_min_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compare packed 32-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m128i _mm_min_epi32 (__m128i a, __m128i b)
    PMINSD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_min_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compare packed 8-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m128i _mm_min_epi8 (__m128i a, __m128i b)
    PMINSB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_min_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compare packed unsigned 16-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m128i _mm_min_epu16 (__m128i a, __m128i b)
    PMINUW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_min_epu32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compare packed unsigned 32-bit integers in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m128i _mm_min_epu32 (__m128i a, __m128i b)
    PMINUD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_minpos_epu16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Horizontally compute the minimum amongst the packed unsigned 16-bit integers in ""a"", store the minimum and index in ""dst"", and zero the remaining bits in ""dst"".
    
    __m128i _mm_minpos_epu16 (__m128i a)
    PHMINPOSUW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mpsadbw_epu8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compute the sum of absolute differences (SADs) of quadruplets of unsigned 8-bit integers in ""a"" compared to those in ""b"", and store the 16-bit results in ""dst"".
    	Eight SADs are performed using one quadruplet from ""b"" and eight quadruplets from ""a"". One quadruplet is selected from ""b"" starting at on the offset specified in ""imm8"". Eight quadruplets are formed from sequential 8-bit integers selected from ""a"" starting at the offset specified in ""imm8"".
    
    __m128i _mm_mpsadbw_epu8 (__m128i a, __m128i b, const int imm8)
    MPSADBW xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mul_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Multiply the low 32-bit integers from each packed 64-bit element in ""a"" and ""b"", and store the signed 64-bit results in ""dst"".
    
    __m128i _mm_mul_epi32 (__m128i a, __m128i b)
    PMULDQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mullo_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Multiply the packed 32-bit integers in ""a"" and ""b"", producing intermediate 64-bit integers, and store the low 32 bits of the intermediate integers in ""dst"".
    
    __m128i _mm_mullo_epi32 (__m128i a, __m128i b)
    PMULLD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_packus_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Convert packed 32-bit integers from ""a"" and ""b"" to packed 16-bit integers using unsigned saturation, and store the results in ""dst"".
    
    __m128i _mm_packus_epi32 (__m128i a, __m128i b)
    PACKUSDW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_pd1"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m128d _mm_round_pd (__m128d a, _MM_FROUND_CUR_DIRECTION); ROUNDPD xmm, xmm/m128, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_pd1_to_nearest_integer"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m128d _mm_round_pd (__m128d a, int rounding)
    ROUNDPD xmm, xmm/m128, imm8(8)
                _MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_pd1_to_negative_infinity"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m128d _mm_round_pd (__m128d a, _MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC); ROUNDPD xmm, xmm/m128, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_pd1_to_positive_infinity"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m128d _mm_round_pd (__m128d a, _MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC); ROUNDPD xmm, xmm/m128, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_pd1_to_zero"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed double-precision (64-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed double-precision floating-point elements in ""dst"".
    
    __m128d _mm_round_pd (__m128d a, _MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC); ROUNDPD xmm, xmm/m128, imm8(11)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m128 _mm_round_ps (__m128 a, _MM_FROUND_CUR_DIRECTION); ROUNDPS xmm, xmm/m128, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ps_to_nearest_integer"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m128 _mm_round_ps (__m128 a, int rounding)
    ROUNDPS xmm, xmm/m128, imm8(8)
                _MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ps_to_negative_infinity"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m128 _mm_round_ps (__m128 a, _MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC); ROUNDPS xmm, xmm/m128, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ps_to_positive_infinity"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m128 _mm_round_ps (__m128 a, _MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC); ROUNDPS xmm, xmm/m128, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ps_to_zero"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the packed single-precision (32-bit) floating-point elements in ""a"" using the ""rounding"" parameter, and store the results as packed single-precision floating-point elements in ""dst"".
    
    __m128 _mm_round_ps (__m128 a, _MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC); ROUNDPS xmm, xmm/m128, imm8(11)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_sd"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_round_sd (__m128d a, __m128d b, _MM_FROUND_CUR_DIRECTION)
    ROUNDSD xmm, xmm/m128, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_sd_to_nearest_integer_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_round_sd (__m128d a, __m128d b, _MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC)
    ROUNDSD xmm, xmm/m128, imm8(8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_sd_to_negative_infinity_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_round_sd (__m128d a, __m128d b, _MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)
    ROUNDSD xmm, xmm/m128, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_sd_to_positive_infinity_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_round_sd (__m128d a, __m128d b, _MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)
    ROUNDSD xmm, xmm/m128, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_sd_to_zero_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_round_sd (__m128d a, __m128d b, _MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)
    ROUNDSD xmm, xmm/m128, imm8(11)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_sd1"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_round_sd (__m128d a, _MM_FROUND_CUR_DIRECTION)
    ROUNDSD xmm, xmm/m128, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_sd1_to_nearest_integer_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_round_sd (__m128d a, _MM_FROUND_TO_NEAREST_INT |_MM_FROUND_NO_EXC)
    ROUNDSD xmm, xmm/m128, imm8(8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_sd1_to_negative_infinity_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_round_sd (__m128d a, _MM_FROUND_TO_NEG_INF |_MM_FROUND_NO_EXC)
    ROUNDSD xmm, xmm/m128, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_sd1_to_positive_infinity_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_round_sd (__m128d a, _MM_FROUND_TO_POS_INF |_MM_FROUND_NO_EXC)
    ROUNDSD xmm, xmm/m128, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_sd1_to_zero_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower double-precision (64-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a double-precision floating-point element in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128d _mm_round_sd (__m128d a, _MM_FROUND_TO_ZERO |_MM_FROUND_NO_EXC)
    ROUNDSD xmm, xmm/m128, imm8(11)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_round_ss (__m128 a, __m128 b, _MM_FROUND_CUR_DIRECTION)
    ROUNDSS xmm, xmm/m128, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ss_to_nearest_integer_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_round_ss (__m128 a, __m128 b, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC)
    ROUNDSS xmm, xmm/m128, imm8(8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ss_to_negative_infinity_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_round_ss (__m128 a, __m128 b, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC)
    ROUNDSS xmm, xmm/m128, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ss_to_positive_infinity_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_round_ss (__m128 a, __m128 b, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC)
    ROUNDSS xmm, xmm/m128, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ss_to_zero_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_round_ss (__m128 a, __m128 b, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC)
    ROUNDSS xmm, xmm/m128, imm8(11)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ss1"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_round_ss (__m128 a, _MM_FROUND_CUR_DIRECTION)
    ROUNDSS xmm, xmm/m128, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ss1_to_nearest_integer_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_round_ss (__m128 a, _MM_FROUND_TO_NEAREST_INT | _MM_FROUND_NO_EXC)
    ROUNDSS xmm, xmm/m128, imm8(8)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ss1_to_negative_infinity_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_round_ss (__m128 a, _MM_FROUND_TO_NEG_INF | _MM_FROUND_NO_EXC)
    ROUNDSS xmm, xmm/m128, imm8(9)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ss1_to_positive_infinity_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_round_ss (__m128 a, _MM_FROUND_TO_POS_INF | _MM_FROUND_NO_EXC)
    ROUNDSS xmm, xmm/m128, imm8(10)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_round_ss1_to_zero_scalar"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Round the lower single-precision (32-bit) floating-point element in ""b"" using the ""rounding"" parameter, store the result as a single-precision floating-point element in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_round_ss (__m128 a, _MM_FROUND_TO_ZERO | _MM_FROUND_NO_EXC)
    ROUNDSS xmm, xmm/m128, imm8(11)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_stream_load_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Load 128-bits of integer data from memory into ""dst"" using a non-temporal memory hint.
    	""mem_addr"" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
    
    __m128i _mm_stream_load_si128 (const __m128i* mem_addr)
    MOVNTDQA xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_testc_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compute the bitwise AND of 128 bits (representing integer data) in ""a"" and ""b"", and set ""ZF"" to 1 if the result is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", and set ""CF"" to 1 if the result is zero, otherwise set ""CF"" to 0. Return the ""CF"" value.
    
    int _mm_testc_si128 (__m128i a, __m128i b)
    PTEST xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_testnzc_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compute the bitwise AND of 128 bits (representing integer data) in ""a"" and ""b"", and set ""ZF"" to 1 if the result is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", and set ""CF"" to 1 if the result is zero, otherwise set ""CF"" to 0. Return 1 if both the ""ZF"" and ""CF"" values are zero, otherwise return 0.
    
    int _mm_testnzc_si128 (__m128i a, __m128i b)
    PTEST xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_testz_si128"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Compute the bitwise AND of 128 bits (representing integer data) in ""a"" and ""b"", and set ""ZF"" to 1 if the result is zero, otherwise set ""ZF"" to 0. Compute the bitwise NOT of ""a"" and then AND with ""b"", and set ""CF"" to 1 if the result is zero, otherwise set ""CF"" to 0. Return the ""ZF"" value.
    
    int _mm_testz_si128 (__m128i a, __m128i b)
    PTEST xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Sse41X64IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_extract_epi64", (Func<object, byte, long>)mm_extract_epi64);
            RegisterFunction("mm_insert_epi64", (Func<object, long, byte, object>)mm_insert_epi64);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_extract_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Extract a 64-bit integer from ""a"", selected with ""imm8"", and store the result in ""dst"".
    
    __int64 _mm_extract_epi64 (__m128i a, const int imm8)
    PEXTRQ reg/m64, xmm, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_insert_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE41";
                descriptor.Description = @"Copy ""a"" to ""dst"", and insert the 64-bit integer ""i"" into ""dst"" at the location specified by ""imm8"".
    
    __m128i _mm_insert_epi64 (__m128i a, __int64 i, const int imm8)
    PINSRQ xmm, reg/m64, imm8";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Sse42IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_cmpgt_epi64", (Func<object, object, object>)mm_cmpgt_epi64);
            RegisterFunction("mm_crc32_u16", (Func<uint, ushort, uint>)mm_crc32_u16);
            RegisterFunction("mm_crc32_u32", (Func<uint, uint, uint>)mm_crc32_u32);
            RegisterFunction("mm_crc32_u8", (Func<uint, byte, uint>)mm_crc32_u8);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_cmpgt_epi64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE42";
                descriptor.Description = @"Compare packed 64-bit integers in ""a"" and ""b"" for greater-than, and store the results in ""dst"".
    
    __m128i _mm_cmpgt_epi64 (__m128i a, __m128i b)
    PCMPGTQ xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_crc32_u16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE42";
                descriptor.Description = @"Starting with the initial value in ""crc"", accumulates a CRC32 value for unsigned 16-bit integer ""v"", and stores the result in ""dst"".
    
    unsigned int _mm_crc32_u16 (unsigned int crc, unsigned short v)
    CRC32 reg, reg/m16";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_crc32_u32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE42";
                descriptor.Description = @"Starting with the initial value in ""crc"", accumulates a CRC32 value for unsigned 32-bit integer ""v"", and stores the result in ""dst"".
    
    unsigned int _mm_crc32_u32 (unsigned int crc, unsigned int v)
    CRC32 reg, reg/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_crc32_u8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE42";
                descriptor.Description = @"Starting with the initial value in ""crc"", accumulates a CRC32 value for unsigned 8-bit integer ""v"", and stores the result in ""dst"".
    
    unsigned int _mm_crc32_u8 (unsigned int crc, unsigned char v)
    CRC32 reg, reg/m8";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Sse42X64IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_crc32_u64", (Func<ulong, ulong, ulong>)mm_crc32_u64);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_crc32_u64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE42";
                descriptor.Description = @"Starting with the initial value in ""crc"", accumulates a CRC32 value for unsigned 64-bit integer ""v"", and stores the result in ""dst"".
    
    unsigned __int64 _mm_crc32_u64 (unsigned __int64 crc, unsigned __int64 v)
    CRC32 reg, reg/m64";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class SseIntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_add_ps", (Func<object, object, object>)mm_add_ps);
            RegisterFunction("mm_add_ss", (Func<object, object, object>)mm_add_ss);
            RegisterFunction("mm_and_ps", (Func<object, object, object>)mm_and_ps);
            RegisterFunction("mm_andnot_ps", (Func<object, object, object>)mm_andnot_ps);
            RegisterFunction("mm_cmpeq_ps", (Func<object, object, object>)mm_cmpeq_ps);
            RegisterFunction("mm_cmpeq_ss", (Func<object, object, object>)mm_cmpeq_ss);
            RegisterFunction("mm_cmpge_ps", (Func<object, object, object>)mm_cmpge_ps);
            RegisterFunction("mm_cmpge_ss", (Func<object, object, object>)mm_cmpge_ss);
            RegisterFunction("mm_cmpgt_ps", (Func<object, object, object>)mm_cmpgt_ps);
            RegisterFunction("mm_cmpgt_ss", (Func<object, object, object>)mm_cmpgt_ss);
            RegisterFunction("mm_cmple_ps", (Func<object, object, object>)mm_cmple_ps);
            RegisterFunction("mm_cmple_ss", (Func<object, object, object>)mm_cmple_ss);
            RegisterFunction("mm_cmplt_ps", (Func<object, object, object>)mm_cmplt_ps);
            RegisterFunction("mm_cmplt_ss", (Func<object, object, object>)mm_cmplt_ss);
            RegisterFunction("mm_cmpneq_ps", (Func<object, object, object>)mm_cmpneq_ps);
            RegisterFunction("mm_cmpneq_ss", (Func<object, object, object>)mm_cmpneq_ss);
            RegisterFunction("mm_cmpnge_ps", (Func<object, object, object>)mm_cmpnge_ps);
            RegisterFunction("mm_cmpnge_ss", (Func<object, object, object>)mm_cmpnge_ss);
            RegisterFunction("mm_cmpngt_ps", (Func<object, object, object>)mm_cmpngt_ps);
            RegisterFunction("mm_cmpngt_ss", (Func<object, object, object>)mm_cmpngt_ss);
            RegisterFunction("mm_cmpnle_ps", (Func<object, object, object>)mm_cmpnle_ps);
            RegisterFunction("mm_cmpnle_ss", (Func<object, object, object>)mm_cmpnle_ss);
            RegisterFunction("mm_cmpnlt_ps", (Func<object, object, object>)mm_cmpnlt_ps);
            RegisterFunction("mm_cmpnlt_ss", (Func<object, object, object>)mm_cmpnlt_ss);
            RegisterFunction("mm_cmpord_ps", (Func<object, object, object>)mm_cmpord_ps);
            RegisterFunction("mm_cmpord_ss", (Func<object, object, object>)mm_cmpord_ss);
            RegisterFunction("mm_cmpunord_ps", (Func<object, object, object>)mm_cmpunord_ps);
            RegisterFunction("mm_cmpunord_ss", (Func<object, object, object>)mm_cmpunord_ss);
            RegisterFunction("mm_comieq_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_comieq_ss);
            RegisterFunction("mm_comige_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_comige_ss);
            RegisterFunction("mm_comigt_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_comigt_ss);
            RegisterFunction("mm_comile_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_comile_ss);
            RegisterFunction("mm_comilt_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_comilt_ss);
            RegisterFunction("mm_comineq_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_comineq_ss);
            RegisterFunction("mm_cvtsi32_ss", (Func<object, int, object>)mm_cvtsi32_ss);
            RegisterFunction("mm_cvtss_si32", (Func<object, int>)mm_cvtss_si32);
            RegisterFunction("mm_cvttss_si32", (Func<object, int>)mm_cvttss_si32);
            RegisterFunction("mm_div_ps", (Func<object, object, object>)mm_div_ps);
            RegisterFunction("mm_div_ss", (Func<object, object, object>)mm_div_ss);
            RegisterFunction("mm_load_ps", (Func<object, object>)mm_load_ps);
            RegisterFunction("mm_load_ss", (Func<object, object>)mm_load_ss);
            RegisterFunction("mm_loadh_pi", (Func<object, object, object>)mm_loadh_pi);
            RegisterFunction("mm_loadl_pi", (Func<object, object, object>)mm_loadl_pi);
            RegisterFunction("mm_loadu_ps", (Func<object, object>)mm_loadu_ps);
            RegisterFunction("mm_max_ps", (Func<object, object, object>)mm_max_ps);
            RegisterFunction("mm_max_ss", (Func<object, object, object>)mm_max_ss);
            RegisterFunction("mm_min_ps", (Func<object, object, object>)mm_min_ps);
            RegisterFunction("mm_min_ss", (Func<object, object, object>)mm_min_ss);
            RegisterFunction("mm_move_ss", (Func<object, object, object>)mm_move_ss);
            RegisterFunction("mm_movehl_ps", (Func<object, object, object>)mm_movehl_ps);
            RegisterFunction("mm_movelh_ps", (Func<object, object, object>)mm_movelh_ps);
            RegisterFunction("mm_movemask_ps", (Func<object, int>)mm_movemask_ps);
            RegisterFunction("mm_mul_ps", (Func<object, object, object>)mm_mul_ps);
            RegisterFunction("mm_mul_ss", (Func<object, object, object>)mm_mul_ss);
            RegisterFunction("mm_or_ps", (Func<object, object, object>)mm_or_ps);
            RegisterAction("mm_prefetch0", (Action<object>)mm_prefetch0);
            RegisterAction("mm_prefetch1", (Action<object>)mm_prefetch1);
            RegisterAction("mm_prefetch2", (Action<object>)mm_prefetch2);
            RegisterAction("mm_prefetchnta", (Action<object>)mm_prefetchnta);
            RegisterFunction("mm_rcp_ps", (Func<object, object>)mm_rcp_ps);
            RegisterFunction("mm_rcp_ss", (Func<object, object, object>)mm_rcp_ss);
            RegisterFunction("mm_rcp_ss1", (Func<object, object>)mm_rcp_ss1);
            RegisterFunction("mm_rsqrt_ps", (Func<object, object>)mm_rsqrt_ps);
            RegisterFunction("mm_rsqrt_ss", (Func<object, object, object>)mm_rsqrt_ss);
            RegisterFunction("mm_rsqrt_ss1", (Func<object, object>)mm_rsqrt_ss1);
            RegisterFunction("mm_shuffle_ps", (Func<object, object, byte, object>)mm_shuffle_ps);
            RegisterFunction("mm_sqrt_ps", (Func<object, object>)mm_sqrt_ps);
            RegisterFunction("mm_sqrt_ss", (Func<object, object, object>)mm_sqrt_ss);
            RegisterFunction("mm_sqrt_ss1", (Func<object, object>)mm_sqrt_ss1);
            RegisterAction("mm_store_ps", (Action<object, object>)mm_store_ps);
            RegisterAction("mm_store_ss", (Action<object, object>)mm_store_ss);
            RegisterAction("mm_storeh_pi", (Action<object, object>)mm_storeh_pi);
            RegisterAction("mm_storel_pi", (Action<object, object>)mm_storel_pi);
            RegisterAction("mm_storeu_ps", (Action<object, object>)mm_storeu_ps);
            RegisterAction("mm_stream_ps", (Action<object, object>)mm_stream_ps);
            RegisterFunction("mm_sub_ps", (Func<object, object, object>)mm_sub_ps);
            RegisterFunction("mm_sub_ss", (Func<object, object, object>)mm_sub_ss);
            RegisterFunction("mm_ucomieq_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomieq_ss);
            RegisterFunction("mm_ucomige_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomige_ss);
            RegisterFunction("mm_ucomigt_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomigt_ss);
            RegisterFunction("mm_ucomile_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomile_ss);
            RegisterFunction("mm_ucomilt_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomilt_ss);
            RegisterFunction("mm_ucomineq_ss", (Func<object, object, Kalk.Core.KalkBool>)mm_ucomineq_ss);
            RegisterFunction("mm_unpackhi_ps", (Func<object, object, object>)mm_unpackhi_ps);
            RegisterFunction("mm_unpacklo_ps", (Func<object, object, object>)mm_unpacklo_ps);
            RegisterFunction("mm_xor_ps", (Func<object, object, object>)mm_xor_ps);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_add_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Add packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128 _mm_add_ps (__m128 a,  __m128 b)
    ADDPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_add_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Add the lower single-precision (32-bit) floating-point element in ""a"" and ""b"", store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_add_ss (__m128 a,  __m128 b)
    ADDSS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_and_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the bitwise AND of packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128 _mm_and_ps (__m128 a, __m128 b)
    ANDPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_andnot_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the bitwise NOT of packed single-precision (32-bit) floating-point elements in ""a"" and then AND with ""b"", and store the results in ""dst"".
    
    __m128 _mm_andnot_ps (__m128 a, __m128 b)
    ANDNPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpeq_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" for equality, and store the results in ""dst"".
    
    __m128 _mm_cmpeq_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(0)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpeq_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" for equality, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmpeq_ss (__m128 a,  __m128 b)
    CMPSS xmm, xmm/m32, imm8(0)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpge_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" for greater-than-or-equal, and store the results in ""dst"".
    
    __m128 _mm_cmpge_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(5)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpge_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" for greater-than-or-equal, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmpge_ss (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m32, imm8(5)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpgt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" for greater-than, and store the results in ""dst"".
    
    __m128 _mm_cmpgt_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(6)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpgt_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" for greater-than, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmpgt_ss (__m128 a,  __m128 b)
    CMPSS xmm, xmm/m32, imm8(6)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmple_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" for less-than-or-equal, and store the results in ""dst"".
    
    __m128 _mm_cmple_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(2)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmple_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" for less-than-or-equal, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmple_ss (__m128 a,  __m128 b)
    CMPSS xmm, xmm/m32, imm8(2)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmplt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" for less-than, and store the results in ""dst"".
    
    __m128 _mm_cmplt_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(1)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmplt_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" for less-than, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmplt_ss (__m128 a,  __m128 b)
    CMPSS xmm, xmm/m32, imm8(1)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpneq_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" for not-equal, and store the results in ""dst"".
    
    __m128 _mm_cmpneq_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpneq_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" for not-equal, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmpneq_ss (__m128 a,  __m128 b)
    CMPSS xmm, xmm/m32, imm8(4)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnge_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" for not-greater-than-or-equal, and store the results in ""dst"".
    
    __m128 _mm_cmpnge_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(1)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnge_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" for not-greater-than-or-equal, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmpnge_ss (__m128 a,  __m128 b)
    CMPSS xmm, xmm/m32, imm8(1)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpngt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" for not-greater-than, and store the results in ""dst"".
    
    __m128 _mm_cmpngt_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(2)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpngt_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" for not-greater-than, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmpngt_ss (__m128 a,  __m128 b)
    CMPSS xmm, xmm/m32, imm8(2)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnle_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" for not-less-than-or-equal, and store the results in ""dst"".
    
    __m128 _mm_cmpnle_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(6)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnle_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" for not-less-than-or-equal, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmpnle_ss (__m128 a,  __m128 b)
    CMPSS xmm, xmm/m32, imm8(6)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnlt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" for not-less-than, and store the results in ""dst"".
    
    __m128 _mm_cmpnlt_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(5)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpnlt_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" for not-less-than, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmpnlt_ss (__m128 a,  __m128 b)
    CMPSS xmm, xmm/m32, imm8(5)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpord_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" to see if neither is NaN, and store the results in ""dst"".
    
    __m128 _mm_cmpord_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(7)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpord_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" to see if neither is NaN, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmpord_ss (__m128 a,  __m128 b)
    CMPSS xmm, xmm/m32, imm8(7)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpunord_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"" to see if either is NaN, and store the results in ""dst"".
    
    __m128 _mm_cmpunord_ps (__m128 a,  __m128 b)
    CMPPS xmm, xmm/m128, imm8(3)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cmpunord_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"" to see if either is NaN, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cmpunord_ss (__m128 a,  __m128 b)
    CMPSS xmm, xmm/m32, imm8(3)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comieq_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for equality, and return the boolean result (0 or 1).
    
    int _mm_comieq_ss (__m128 a, __m128 b)
    COMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comige_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for greater-than-or-equal, and return the boolean result (0 or 1).
    
    int _mm_comige_ss (__m128 a, __m128 b)
    COMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comigt_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for greater-than, and return the boolean result (0 or 1).
    
    int _mm_comigt_ss (__m128 a, __m128 b)
    COMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comile_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for less-than-or-equal, and return the boolean result (0 or 1).
    
    int _mm_comile_ss (__m128 a, __m128 b)
    COMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comilt_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for less-than, and return the boolean result (0 or 1).
    
    int _mm_comilt_ss (__m128 a, __m128 b)
    COMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_comineq_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for not-equal, and return the boolean result (0 or 1).
    
    int _mm_comineq_ss (__m128 a, __m128 b)
    COMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtsi32_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Convert the 32-bit integer ""b"" to a single-precision (32-bit) floating-point element, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cvtsi32_ss (__m128 a, int b)
    CVTSI2SS xmm, reg/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtss_si32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Convert the lower single-precision (32-bit) floating-point element in ""a"" to a 32-bit integer, and store the result in ""dst"".
    
    int _mm_cvtss_si32 (__m128 a)
    CVTSS2SI r32, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvttss_si32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Convert the lower single-precision (32-bit) floating-point element in ""a"" to a 32-bit integer with truncation, and store the result in ""dst"".
    
    int _mm_cvttss_si32 (__m128 a)
    CVTTSS2SI r32, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_div_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Divide packed single-precision (32-bit) floating-point elements in ""a"" by packed elements in ""b"", and store the results in ""dst"".
    
    __m128 _mm_div_ps (__m128 a,  __m128 b)
    DIVPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_div_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Divide the lower single-precision (32-bit) floating-point element in ""a"" by the lower single-precision (32-bit) floating-point element in ""b"", store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_div_ss (__m128 a,  __m128 b)
    DIVSS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_load_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into ""dst"".
    	""mem_addr"" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
    
    __m128 _mm_load_ps (float const* mem_address)
    MOVAPS xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_load_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Load a single-precision (32-bit) floating-point element from memory into the lower of ""dst"", and zero the upper 3 elements. ""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m128 _mm_load_ss (float const* mem_address)
    MOVSS xmm, m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_loadh_pi"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Load 2 single-precision (32-bit) floating-point elements from memory into the upper 2 elements of ""dst"", and copy the lower 2 elements from ""a"" to ""dst"". ""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m128 _mm_loadh_pi (__m128 a, __m64 const* mem_addr)
    MOVHPS xmm, m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_loadl_pi"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Load 2 single-precision (32-bit) floating-point elements from memory into the lower 2 elements of ""dst"", and copy the upper 2 elements from ""a"" to ""dst"". ""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m128 _mm_loadl_pi (__m128 a, __m64 const* mem_addr)
    MOVLPS xmm, m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_loadu_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Load 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from memory into ""dst"".
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    __m128 _mm_loadu_ps (float const* mem_address)
    MOVUPS xmm, m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_max_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store packed maximum values in ""dst"".
    
    __m128 _mm_max_ps (__m128 a,  __m128 b)
    MAXPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_max_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"", store the maximum value in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128 _mm_max_ss (__m128 a,  __m128 b)
    MAXSS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_min_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store packed minimum values in ""dst"".
    
    __m128 _mm_min_ps (__m128 a,  __m128 b)
    MINPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_min_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point elements in ""a"" and ""b"", store the minimum value in the lower element of ""dst"", and copy the upper element from ""a"" to the upper element of ""dst"".
    
    __m128 _mm_min_ss (__m128 a,  __m128 b)
    MINSS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_move_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Move the lower single-precision (32-bit) floating-point element from ""b"" to the lower element of ""dst"", and copy the upper 3 elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_move_ss (__m128 a, __m128 b)
    MOVSS xmm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_movehl_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Move the upper 2 single-precision (32-bit) floating-point elements from ""b"" to the lower 2 elements of ""dst"", and copy the upper 2 elements from ""a"" to the upper 2 elements of ""dst"".
    
    __m128 _mm_movehl_ps (__m128 a,  __m128 b)
    MOVHLPS xmm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_movelh_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Move the lower 2 single-precision (32-bit) floating-point elements from ""b"" to the upper 2 elements of ""dst"", and copy the lower 2 elements from ""a"" to the lower 2 elements of ""dst"".
    
    __m128 _mm_movelh_ps (__m128 a,  __m128 b)
    MOVLHPS xmm, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_movemask_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Set each bit of mask ""dst"" based on the most significant bit of the corresponding packed single-precision (32-bit) floating-point element in ""a"".
    
    int _mm_movemask_ps (__m128 a)
    MOVMSKPS reg, xmm";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mul_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Multiply packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128 _mm_mul_ps (__m128 a, __m128 b)
    MULPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mul_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Multiply the lower single-precision (32-bit) floating-point element in ""a"" and ""b"", store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_mul_ss (__m128 a, __m128 b)
    MULPS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_or_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the bitwise OR of packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128 _mm_or_ps (__m128 a,  __m128 b)
    ORPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_prefetch0"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Fetch the line of data from memory that contains address ""p"" to a location in the cache heirarchy specified by the locality hint ""i"".
    
    void _mm_prefetch(char* p, int i)
    PREFETCHT0 m8";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_prefetch1"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Fetch the line of data from memory that contains address ""p"" to a location in the cache heirarchy specified by the locality hint ""i"".
    
    void _mm_prefetch(char* p, int i)
    PREFETCHT1 m8";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_prefetch2"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Fetch the line of data from memory that contains address ""p"" to a location in the cache heirarchy specified by the locality hint ""i"".
    
    void _mm_prefetch(char* p, int i)
    PREFETCHT2 m8";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_prefetchnta"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Fetch the line of data from memory that contains address ""p"" to a location in the cache heirarchy specified by the locality hint ""i"".
    
    void _mm_prefetch(char* p, int i)
    PREFETCHNTA m8";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_rcp_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the approximate reciprocal of packed single-precision (32-bit) floating-point elements in ""a"", and store the results in ""dst"". The maximum relative error for this approximation is less than 1.5*2^-12.
    
    __m128 _mm_rcp_ps (__m128 a)
    RCPPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_rcp_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in ""a"", store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"". The maximum relative error for this approximation is less than 1.5*2^-12.
    
    __m128 _mm_rcp_ss (__m128 a, __m128 b)
    RCPSS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_rcp_ss1"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the approximate reciprocal of the lower single-precision (32-bit) floating-point element in ""a"", store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"". The maximum relative error for this approximation is less than 1.5*2^-12.
    
    __m128 _mm_rcp_ss (__m128 a)
    RCPSS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_rsqrt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the approximate reciprocal square root of packed single-precision (32-bit) floating-point elements in ""a"", and store the results in ""dst"". The maximum relative error for this approximation is less than 1.5*2^-12.
    
    __m128 _mm_rsqrt_ps (__m128 a)
    RSQRTPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_rsqrt_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in ""a"", store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"". The maximum relative error for this approximation is less than 1.5*2^-12.
    
    __m128 _mm_rsqrt_ss (__m128 a, __m128 b)
    RSQRTSS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_rsqrt_ss1"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the approximate reciprocal square root of the lower single-precision (32-bit) floating-point element in ""a"", store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"". The maximum relative error for this approximation is less than 1.5*2^-12.
    
    __m128 _mm_rsqrt_ss (__m128 a)
    RSQRTSS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_shuffle_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Shuffle single-precision (32-bit) floating-point elements in ""a"" using the control in ""imm8"", and store the results in ""dst"".
    
    __m128 _mm_shuffle_ps (__m128 a,  __m128 b, unsigned int control)
    SHUFPS xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sqrt_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the square root of packed single-precision (32-bit) floating-point elements in ""a"", and store the results in ""dst"".
    
    __m128 _mm_sqrt_ps (__m128 a)
    SQRTPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sqrt_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the square root of the lower single-precision (32-bit) floating-point element in ""a"", store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_sqrt_ss (__m128 a, __m128 b)
    SQRTSS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sqrt_ss1"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the square root of the lower single-precision (32-bit) floating-point element in ""a"", store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_sqrt_ss (__m128 a)
    SQRTSS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_store_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from ""a"" into memory.
    	""mem_addr"" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
    
    void _mm_store_ps (float* mem_addr, __m128 a)
    MOVAPS m128, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_store_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Store the lower single-precision (32-bit) floating-point element from ""a"" into memory. ""mem_addr"" does not need to be aligned on any particular boundary.
    
    void _mm_store_ss (float* mem_addr, __m128 a)
    MOVSS m32, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_storeh_pi"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Store the upper 2 single-precision (32-bit) floating-point elements from ""a"" into memory.
    
    void _mm_storeh_pi (__m64* mem_addr, __m128 a)
    MOVHPS m64, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_storel_pi"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Store the lower 2 single-precision (32-bit) floating-point elements from ""a"" into memory.
    
    void _mm_storel_pi (__m64* mem_addr, __m128 a)
    MOVLPS m64, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_storeu_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from ""a"" into memory.
    	""mem_addr"" does not need to be aligned on any particular boundary.
    
    void _mm_storeu_ps (float* mem_addr, __m128 a)
    MOVUPS m128, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_stream_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Store 128-bits (composed of 4 packed single-precision (32-bit) floating-point elements) from ""a"" into memory using a non-temporal memory hint.
    	""mem_addr"" must be aligned on a 16-byte boundary or a general-protection exception may be generated.
    
    void _mm_stream_ps (float* mem_addr, __m128 a)
    MOVNTPS m128, xmm";
                descriptor.IsCommand = true;
            }
            {
                var descriptor = Descriptors["mm_sub_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Subtract packed single-precision (32-bit) floating-point elements in ""b"" from packed single-precision (32-bit) floating-point elements in ""a"", and store the results in ""dst"".
    
    __m128d _mm_sub_ps (__m128d a, __m128d b)
    SUBPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sub_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Subtract the lower single-precision (32-bit) floating-point element in ""b"" from the lower single-precision (32-bit) floating-point element in ""a"", store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_sub_ss (__m128 a, __m128 b)
    SUBSS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomieq_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for equality, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomieq_ss (__m128 a, __m128 b)
    UCOMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomige_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for greater-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomige_ss (__m128 a, __m128 b)
    UCOMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomigt_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for greater-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomigt_ss (__m128 a, __m128 b)
    UCOMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomile_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for less-than-or-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomile_ss (__m128 a, __m128 b)
    UCOMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomilt_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for less-than, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomilt_ss (__m128 a, __m128 b)
    UCOMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_ucomineq_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compare the lower single-precision (32-bit) floating-point element in ""a"" and ""b"" for not-equal, and return the boolean result (0 or 1). This instruction will not signal an exception for QNaNs.
    
    int _mm_ucomineq_ss (__m128 a, __m128 b)
    UCOMISS xmm, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpackhi_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Unpack and interleave single-precision (32-bit) floating-point elements from the high half ""a"" and ""b"", and store the results in ""dst"".
    
    __m128 _mm_unpackhi_ps (__m128 a,  __m128 b)
    UNPCKHPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_unpacklo_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Unpack and interleave single-precision (32-bit) floating-point elements from the low half of ""a"" and ""b"", and store the results in ""dst"".
    
    __m128 _mm_unpacklo_ps (__m128 a,  __m128 b)
    UNPCKLPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_xor_ps"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Compute the bitwise XOR of packed single-precision (32-bit) floating-point elements in ""a"" and ""b"", and store the results in ""dst"".
    
    __m128 _mm_xor_ps (__m128 a,  __m128 b)
    XORPS xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class SseX64IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_cvtsi64_ss", (Func<object, long, object>)mm_cvtsi64_ss);
            RegisterFunction("mm_cvtss_si64", (Func<object, long>)mm_cvtss_si64);
            RegisterFunction("mm_cvttss_si64", (Func<object, long>)mm_cvttss_si64);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_cvtsi64_ss"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Convert the 64-bit integer ""b"" to a single-precision (32-bit) floating-point element, store the result in the lower element of ""dst"", and copy the upper 3 packed elements from ""a"" to the upper elements of ""dst"".
    
    __m128 _mm_cvtsi64_ss (__m128 a, __int64 b)
    CVTSI2SS xmm, reg/m64";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvtss_si64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Convert the lower single-precision (32-bit) floating-point element in ""a"" to a 64-bit integer, and store the result in ""dst"".
    
    __int64 _mm_cvtss_si64 (__m128 a)
    CVTSS2SI r64, xmm/m32";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_cvttss_si64"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSE";
                descriptor.Description = @"Convert the lower single-precision (32-bit) floating-point element in ""a"" to a 64-bit integer with truncation, and store the result in ""dst"".
    
    __int64 _mm_cvttss_si64 (__m128 a)
    CVTTSS2SI r64, xmm/m32";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules.HardwareIntrinsics.X86
{
    public partial class Ssse3IntrinsicsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("mm_abs_epi16", (Func<object, object>)mm_abs_epi16);
            RegisterFunction("mm_abs_epi32", (Func<object, object>)mm_abs_epi32);
            RegisterFunction("mm_abs_epi8", (Func<object, object>)mm_abs_epi8);
            RegisterFunction("mm_alignr_epi8", (Func<object, object, byte, object>)mm_alignr_epi8);
            RegisterFunction("mm_hadd_epi16", (Func<object, object, object>)mm_hadd_epi16);
            RegisterFunction("mm_hadd_epi32", (Func<object, object, object>)mm_hadd_epi32);
            RegisterFunction("mm_hadds_epi16", (Func<object, object, object>)mm_hadds_epi16);
            RegisterFunction("mm_hsub_epi16", (Func<object, object, object>)mm_hsub_epi16);
            RegisterFunction("mm_hsub_epi32", (Func<object, object, object>)mm_hsub_epi32);
            RegisterFunction("mm_hsubs_epi16", (Func<object, object, object>)mm_hsubs_epi16);
            RegisterFunction("mm_maddubs_epi16", (Func<object, object, object>)mm_maddubs_epi16);
            RegisterFunction("mm_mulhrs_epi16", (Func<object, object, object>)mm_mulhrs_epi16);
            RegisterFunction("mm_shuffle_epi8", (Func<object, object, object>)mm_shuffle_epi8);
            RegisterFunction("mm_sign_epi16", (Func<object, object, object>)mm_sign_epi16);
            RegisterFunction("mm_sign_epi32", (Func<object, object, object>)mm_sign_epi32);
            RegisterFunction("mm_sign_epi8", (Func<object, object, object>)mm_sign_epi8);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["mm_abs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Compute the absolute value of packed 16-bit integers in ""a"", and store the unsigned results in ""dst"".
    
    __m128i _mm_abs_epi16 (__m128i a)
    PABSW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_abs_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Compute the absolute value of packed 32-bit integers in ""a"", and store the unsigned results in ""dst"".
    
    __m128i _mm_abs_epi32 (__m128i a)
    PABSD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_abs_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Compute the absolute value of packed 8-bit integers in ""a"", and store the unsigned results in ""dst"".
    
    __m128i _mm_abs_epi8 (__m128i a)
    PABSB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_alignr_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Concatenate 16-byte blocks in ""a"" and ""b"" into a 32-byte temporary result, shift the result right by ""count"" bytes, and store the low 16 bytes in ""dst"".
    
    __m128i _mm_alignr_epi8 (__m128i a, __m128i b, int count)
    PALIGNR xmm, xmm/m128, imm8";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_hadd_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Horizontally add adjacent pairs of 16-bit integers in ""a"" and ""b"", and pack the signed 16-bit results in ""dst"".
    
    __m128i _mm_hadd_epi16 (__m128i a, __m128i b)
    PHADDW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_hadd_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Horizontally add adjacent pairs of 32-bit integers in ""a"" and ""b"", and pack the signed 32-bit results in ""dst"".
    
    __m128i _mm_hadd_epi32 (__m128i a, __m128i b)
    PHADDD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_hadds_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Horizontally add adjacent pairs of 16-bit integers in ""a"" and ""b"" using saturation, and pack the signed 16-bit results in ""dst"".
    
    __m128i _mm_hadds_epi16 (__m128i a, __m128i b)
    PHADDSW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_hsub_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Horizontally subtract adjacent pairs of 16-bit integers in ""a"" and ""b"", and pack the signed 16-bit results in ""dst"".
    
    __m128i _mm_hsub_epi16 (__m128i a, __m128i b)
    PHSUBW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_hsub_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Horizontally subtract adjacent pairs of 32-bit integers in ""a"" and ""b"", and pack the signed 32-bit results in ""dst"".
    
    __m128i _mm_hsub_epi32 (__m128i a, __m128i b)
    PHSUBD xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_hsubs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Horizontally subtract adjacent pairs of 16-bit integers in ""a"" and ""b"" using saturation, and pack the signed 16-bit results in ""dst"".
    
    __m128i _mm_hsubs_epi16 (__m128i a, __m128i b)
    PHSUBSW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_maddubs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Vertically multiply each unsigned 8-bit integer from ""a"" with the corresponding signed 8-bit integer from ""b"", producing intermediate signed 16-bit integers. Horizontally add adjacent pairs of intermediate signed 16-bit integers, and pack the saturated results in ""dst"".
    
    __m128i _mm_maddubs_epi16 (__m128i a, __m128i b)
    PMADDUBSW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_mulhrs_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Multiply packed 16-bit integers in ""a"" and ""b"", producing intermediate signed 32-bit integers. Truncate each intermediate integer to the 18 most significant bits, round by adding 1, and store bits [16:1] to ""dst"".
    
    __m128i _mm_mulhrs_epi16 (__m128i a, __m128i b)
    PMULHRSW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_shuffle_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Shuffle packed 8-bit integers in ""a"" according to shuffle control mask in the corresponding 8-bit element of ""b"", and store the results in ""dst"".
    
    __m128i _mm_shuffle_epi8 (__m128i a, __m128i b)
    PSHUFB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sign_epi16"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Negate packed 16-bit integers in ""a"" when the corresponding signed 16-bit integer in ""b"" is negative, and store the results in ""dst"". Element in ""dst"" are zeroed out when the corresponding element in ""b"" is zero.
    
    __m128i _mm_sign_epi16 (__m128i a, __m128i b)
    PSIGNW xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sign_epi32"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Negate packed 32-bit integers in ""a"" when the corresponding signed 32-bit integer in ""b"" is negative, and store the results in ""dst"". Element in ""dst"" are zeroed out when the corresponding element in ""b"" is zero.
    
    __m128i _mm_sign_epi32 (__m128i a, __m128i b)
    PSIGND xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["mm_sign_epi8"];
                descriptor.Category = "Vector Hardware Intrinsics X86 / SSSE3";
                descriptor.Description = @"Negate packed 8-bit integers in ""a"" when the corresponding signed 8-bit integer in ""b"" is negative, and store the results in ""dst"". Element in ""dst"" are zeroed out when the corresponding element in ""b"" is zero.
    
    __m128i _mm_sign_epi8 (__m128i a, __m128i b)
    PSIGNB xmm, xmm/m128";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules
{
    public partial class StandardUnitsModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptor;
                descriptor.Category = "Modules (e.g `import Files`)";
                descriptor.Description = @"Modules that contains standard units.";
                descriptor.IsCommand = false;
            }
        }        
    }
}
namespace Kalk.Core.Modules
{
    public partial class StringModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("escape", (Func<string, string>)StringEscape);
            RegisterFunction("capitalize", (Func<string, string>)StringCapitalize);
            RegisterFunction("capitalize_words", (Func<string, string>)StringCapitalizeWords);
            RegisterFunction("downcase", (Func<string, string>)StringDowncase);
            RegisterFunction("upcase", (Func<string, string>)StringUpcase);
            RegisterFunction("endswith", (Func<string, string, Kalk.Core.KalkBool>)StringEndsWith);
            RegisterFunction("handleize", (Func<string, string>)StringHandleize);
            RegisterFunction("lstrip", (Func<string, string>)StringLeftStrip);
            RegisterFunction("pluralize", (Func<int, string, string, string>)StringPluralize);
            RegisterFunction("rstrip", (Func<string, string>)StringRightStrip);
            RegisterFunction("split", (Func<string, string, System.Collections.IEnumerable>)StringSplit);
            RegisterFunction("startswith", (Func<string, string, Kalk.Core.KalkBool>)StringStartsWith);
            RegisterFunction("strip", (Func<string, string>)StringStrip);
            RegisterFunction("strip_newlines", (Func<string, string>)StringStripNewlines);
            RegisterFunction("pad_left", (Func<string, int, string>)StringPadLeft);
            RegisterFunction("pad_right", (Func<string, int, string>)StringPadRight);
            RegisterFunction("regex_escape", (Func<string, string>)RegexEscape);
            RegisterFunction("regex_match", (Func<string, string, string, Scriban.Runtime.ScriptArray>)RegexMatch);
            RegisterFunction("regex_matches", (Func<string, string, string, Scriban.Runtime.ScriptArray>)RegexMatches);
            RegisterFunction("regex_replace", (Func<string, string, string, string, string>)RegexReplace);
            RegisterFunction("regex_split", (Func<string, string, string, Scriban.Runtime.ScriptArray>)RegexSplit);
            RegisterFunction("regex_unescape", (Func<string, string>)RegexUnescape);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptor;
                descriptor.Category = "Modules (e.g `import Files`)";
                descriptor.Description = @"Modules that provides string functions (e.g `upcase`, `downcase`, `regex_escape`...).";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["escape"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Escapes a string with escape characters.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The two strings concatenated";
                descriptor.Example = @"    >>> ""Hel\tlo\n\""W\\orld"" |> escape
    # ""Hel\tlo\n\""W\\orld"" |> escape
    out = ""Hel\\tlo\\n\\\""W\\\\orld""
";
            }
            {
                var descriptor = Descriptors["capitalize"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Converts the first character of the passed string to a upper case character.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The capitalized input string";
                descriptor.Example = @"    >>> ""test"" |> capitalize
    # ""test"" |> capitalize
    out = ""Test""
";
            }
            {
                var descriptor = Descriptors["capitalize_words"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Converts the first character of each word in the passed string to a upper case character.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The capitalized input string";
                descriptor.Example = @"    >>> ""This is easy"" |> capitalize_words
    # ""This is easy"" |> capitalize_words
    out = ""This Is Easy""
";
            }
            {
                var descriptor = Descriptors["downcase"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Converts the string to lower case.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The input string lower case";
                descriptor.Example = @"    >>> ""TeSt"" |> downcase
    # ""TeSt"" |> downcase
    out = ""test""
";
            }
            {
                var descriptor = Descriptors["upcase"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Converts the string to uppercase";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The input string upper case";
                descriptor.Example = @"    >>> ""test"" |> upcase
    # ""test"" |> upcase
    out = ""TEST""
";
            }
            {
                var descriptor = Descriptors["endswith"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Returns a boolean indicating whether the input string ends with the specified string `value`.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("end", @"The string to look for")  { IsOptional = false });
                descriptor.Returns = @"true if `text` ends with the specified string `value`";
                descriptor.Example = @"    >>> ""This is easy"" |> endswith ""easy""
    # ""This is easy"" |> endswith(""easy"")
    out = true
    >>> ""This is easy"" |> endswith ""none""
    # ""This is easy"" |> endswith(""none"")
    out = false
";
            }
            {
                var descriptor = Descriptors["handleize"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Returns a url handle from the input string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"A url handle";
                descriptor.Example = @"    >>> '100% M @ Ms!!!' |> handleize
    # '100% M @ Ms!!!' |> handleize
    out = ""100-m-ms""
";
            }
            {
                var descriptor = Descriptors["lstrip"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Removes any whitespace characters on the **left** side of the input string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The input string without any left whitespace characters";
                descriptor.Example = @"    >>> '   too many spaces' |> lstrip
    # '   too many spaces' |> lstrip
    out = ""too many spaces""
";
            }
            {
                var descriptor = Descriptors["pluralize"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Outputs the singular or plural version of a string based on the value of a number.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("number", @"The number to check")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("singular", @"The singular string to return if number is == 1")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("plural", @"The plural string to return if number is != 1")  { IsOptional = false });
                descriptor.Returns = @"The singular or plural string based on number";
                descriptor.Example = @"    >>> 3 |> pluralize('product', 'products')
    # 3 |> pluralize('product', 'products')
    out = ""products""
";
            }
            {
                var descriptor = Descriptors["rstrip"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Removes any whitespace characters on the **right** side of the input string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The input string without any left whitespace characters";
                descriptor.Example = @"    >>> '   too many spaces           ' |> rstrip
    # '   too many spaces           ' |> rstrip
    out = ""   too many spaces""
";
            }
            {
                var descriptor = Descriptors["split"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"The `split` function takes on a substring as a parameter.
    The substring is used as a delimiter to divide a string into an array. You can output different parts of an array using `array` functions.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("match", @"The string used to split the input `text` string")  { IsOptional = false });
                descriptor.Returns = @"An enumeration of the substrings";
                descriptor.Example = @"    >>> ""Hi, how are you today?"" |> split ' '
    # ""Hi, how are you today?"" |> split(' ')
    out = [""Hi,"", ""how"", ""are"", ""you"", ""today?""]
";
            }
            {
                var descriptor = Descriptors["startswith"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Returns a boolean indicating whether the input string starts with the specified string `value`.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("start", @"The string to look for")  { IsOptional = false });
                descriptor.Returns = @"true if `text` starts with the specified string `value`";
                descriptor.Example = @"    >>> ""This is easy"" |> startswith ""This""
    # ""This is easy"" |> startswith(""This"")
    out = true
    >>> ""This is easy"" |> startswith ""easy""
    # ""This is easy"" |> startswith(""easy"")
    out = false
";
            }
            {
                var descriptor = Descriptors["strip"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Removes any whitespace characters on the **left** and **right** side of the input string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The input string without any left and right whitespace characters";
                descriptor.Example = @"    >>> '   too many spaces           ' |> strip
    # '   too many spaces           ' |> strip
    out = ""too many spaces""
";
            }
            {
                var descriptor = Descriptors["strip_newlines"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Removes any line breaks/newlines from a string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The input string without any breaks/newlines characters";
                descriptor.Example = @"    >>> ""This is a string.\r\n With \nanother \rstring"" |> strip_newlines
    # ""This is a string.\r\n With \nanother \rstring"" |> strip_newlines
    out = ""This is a string. With another string""
";
            }
            {
                var descriptor = Descriptors["pad_left"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Pads a string with leading spaces to a specified total length.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("width", @"The number of characters in the resulting string")  { IsOptional = false });
                descriptor.Returns = @"The input string padded";
                descriptor.Example = @"    >>> ""world"" |> pad_left 10
    # ""world"" |> pad_left(10)
    out = ""     world""
";
            }
            {
                var descriptor = Descriptors["pad_right"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Pads a string with trailing spaces to a specified total length.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("width", @"The number of characters in the resulting string")  { IsOptional = false });
                descriptor.Returns = @"The input string padded";
                descriptor.Example = @"    >>> ""hello"" |> pad_right 10
    # ""hello"" |> pad_right(10)
    out = ""hello     ""
";
            }
            {
                var descriptor = Descriptors["regex_escape"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Escapes a minimal set of characters (`\`, `*`, `+`, `?`, `|`, `{`, `[`, `(`,`)`, `^`, `$`,`.`, `#`, and white space)
    by replacing them with their escape codes.
    This instructs the regular expression engine to interpret these characters literally rather than as metacharacters.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string that contains the text to convert.")  { IsOptional = false });
                descriptor.Returns = @"A string of characters with metacharacters converted to their escaped form.";
                descriptor.Example = @"    >>> ""(abc.*)"" |> regex_escape
    # ""(abc.*)"" |> regex_escape
    out = ""\\(abc\\.\\*\\)""
";
            }
            {
                var descriptor = Descriptors["regex_match"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Searches an input string for a substring that matches a regular expression pattern and returns an array with the match occurences.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The string to search for a match.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("pattern", @"The regular expression pattern to match.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("options", @"A string with regex options, that can contain the following option characters (default is `null`):
    - `i`: Specifies case-insensitive matching.
    - `m`: Multiline mode. Changes the meaning of `^` and `$` so they match at the beginning and end, respectively, of any line, and not just the beginning and end of the entire string.
    - `s`: Specifies single-line mode. Changes the meaning of the dot `.` so it matches every character (instead of every character except `\n`).
    - `x`: Eliminates unescaped white space from the pattern and enables comments marked with `#`.")  { IsOptional = true });
                descriptor.Returns = @"An array that contains all the match groups. The first group contains the entire match. The other elements contain regex matched groups `(..)`. An empty array returned means no match.";
                descriptor.Example = @"    >>> ""this is a text123"" |> regex_match `(\w+) a ([a-z]+\d+)`
    # ""this is a text123"" |> regex_match(`(\w+) a ([a-z]+\d+)`)
    out = [""is a text123"", ""is"", ""text123""]
";
            }
            {
                var descriptor = Descriptors["regex_matches"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Searches an input string for multiple substrings that matches a regular expression pattern and returns an array with the match occurences.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The string to search for a match.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("pattern", @"The regular expression pattern to match.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("options", @"A string with regex options, that can contain the following option characters (default is `null`):
    - `i`: Specifies case-insensitive matching.
    - `m`: Multiline mode. Changes the meaning of `^` and `$` so they match at the beginning and end, respectively, of any line, and not just the beginning and end of the entire string.
    - `s`: Specifies single-line mode. Changes the meaning of the dot `.` so it matches every character (instead of every character except `\n`).
    - `x`: Eliminates unescaped white space from the pattern and enables comments marked with `#`.")  { IsOptional = true });
                descriptor.Returns = @"An array of matches that contains all the match groups. The first group contains the entire match. The other elements contain regex matched groups `(..)`. An empty array returned means no match.";
                descriptor.Example = @"    >>> ""this is a text123"" |> regex_matches `(\w+)`
    # ""this is a text123"" |> regex_matches(`(\w+)`)
    out = [[""this"", ""this""], [""is"", ""is""], [""a"", ""a""], [""text123"", ""text123""]]
";
            }
            {
                var descriptor = Descriptors["regex_replace"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"In a specified input string, replaces strings that match a regular expression pattern with a specified replacement string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The string to search for a match.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("pattern", @"The regular expression pattern to match.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("replace", @"The replacement string.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("options", @"A string with regex options, that can contain the following option characters (default is `null`):
    - `i`: Specifies case-insensitive matching.
    - `m`: Multiline mode. Changes the meaning of `^` and `$` so they match at the beginning and end, respectively, of any line, and not just the beginning and end of the entire string.
    - `s`: Specifies single-line mode. Changes the meaning of the dot `.` so it matches every character (instead of every character except `\n`).
    - `x`: Eliminates unescaped white space from the pattern and enables comments marked with `#`.")  { IsOptional = true });
                descriptor.Returns = @"A new string that is identical to the input string, except that the replacement string takes the place of each matched string. If pattern is not matched in the current instance, the method returns the current instance unchanged.";
                descriptor.Example = @"    >>> ""abbbbcccd"" |> regex_replace(""b+c+"",""-Yo-"")
    # ""abbbbcccd"" |> regex_replace(""b+c+"", ""-Yo-"")
    out = ""a-Yo-d""
";
            }
            {
                var descriptor = Descriptors["regex_split"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Splits an input string into an array of substrings at the positions defined by a regular expression match.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The string to split.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("pattern", @"The regular expression pattern to match.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("options", @"A string with regex options, that can contain the following option characters (default is `null`):
    - `i`: Specifies case-insensitive matching.
    - `m`: Multiline mode. Changes the meaning of `^` and `$` so they match at the beginning and end, respectively, of any line, and not just the beginning and end of the entire string.
    - `s`: Specifies single-line mode. Changes the meaning of the dot `.` so it matches every character (instead of every character except `\n`).
    - `x`: Eliminates unescaped white space from the pattern and enables comments marked with `#`.")  { IsOptional = true });
                descriptor.Returns = @"A string array.";
                descriptor.Example = @"    >>> ""a, b   , c,    d"" |> regex_split `\s*,\s*`
    # ""a, b   , c,    d"" |> regex_split(`\s*,\s*`)
    out = [""a"", ""b"", ""c"", ""d""]
";
            }
            {
                var descriptor = Descriptors["regex_unescape"];
                descriptor.Category = "Text Functions";
                descriptor.Description = @"Converts any escaped characters in the input string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string containing the text to convert.")  { IsOptional = false });
                descriptor.Returns = @"A string of characters with any escaped characters converted to their unescaped form.";
                descriptor.Example = @"    >>> ""\\(abc\\.\\*\\)"" |> regex_unescape
    # ""\\(abc\\.\\*\\)"" |> regex_unescape
    out = ""(abc.*)""
";
            }
        }        
    }
}
namespace Kalk.Core.Modules
{
    public partial class TypesModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("byte", (Func<object, byte>)CreateByte);
            RegisterFunction("sbyte", (Func<object, sbyte>)CreateSByte);
            RegisterFunction("short", (Func<object, short>)CreateShort);
            RegisterFunction("ushort", (Func<object, ushort>)CreateUShort);
            RegisterFunction("uint", (Func<object, uint>)CreateUInt);
            RegisterFunction("int", (Func<object, int>)CreateInt);
            RegisterFunction("ulong", (Func<object, ulong>)CreateULong);
            RegisterFunction("long", (Func<object, long>)CreateLong);
            RegisterFunction("bool", (Func<object, Kalk.Core.KalkBool>)CreateBool);
            RegisterFunction("float", (Func<object, float>)CreateFloat);
            RegisterFunction("half", (Func<object, Kalk.Core.KalkHalf>)CreateHalf);
            RegisterFunction("double", (Func<object, double>)CreateDouble);
            RegisterFunction("vector", (Func<Scriban.Syntax.ScriptVariable, int, object[], object>)CreateVector);
            RegisterFunction("rgb", (Func<object[], Kalk.Core.KalkColorRgb>)CreateRgb);
            RegisterFunction("rgba", (Func<object[], Kalk.Core.KalkColorRgba>)CreateRgba);
            RegisterFunction("matrix", (Func<Scriban.Syntax.ScriptVariable, int, int, object[], object>)CreateMatrix);
            RegisterFunction("byte16", (Func<object[], Kalk.Core.KalkVector<byte>>)CreateByte16);
            RegisterFunction("byte32", (Func<object[], Kalk.Core.KalkVector<byte>>)CreateByte32);
            RegisterFunction("byte64", (Func<object[], Kalk.Core.KalkVector<byte>>)CreateByte64);
            RegisterFunction("sbyte16", (Func<object[], Kalk.Core.KalkVector<sbyte>>)CreateSByte16);
            RegisterFunction("sbyte32", (Func<object[], Kalk.Core.KalkVector<sbyte>>)CreateSByte32);
            RegisterFunction("sbyte64", (Func<object[], Kalk.Core.KalkVector<sbyte>>)CreateSByte64);
            RegisterFunction("short2", (Func<object[], Kalk.Core.KalkVector<short>>)CreateShort2);
            RegisterFunction("short4", (Func<object[], Kalk.Core.KalkVector<short>>)CreateShort4);
            RegisterFunction("short8", (Func<object[], Kalk.Core.KalkVector<short>>)CreateShort8);
            RegisterFunction("short16", (Func<object[], Kalk.Core.KalkVector<short>>)CreateShort16);
            RegisterFunction("short32", (Func<object[], Kalk.Core.KalkVector<short>>)CreateShort32);
            RegisterFunction("ushort2", (Func<object[], Kalk.Core.KalkVector<ushort>>)CreateUShort2);
            RegisterFunction("ushort4", (Func<object[], Kalk.Core.KalkVector<ushort>>)CreateUShort4);
            RegisterFunction("ushort8", (Func<object[], Kalk.Core.KalkVector<ushort>>)CreateUShort8);
            RegisterFunction("ushort16", (Func<object[], Kalk.Core.KalkVector<ushort>>)CreateUShort16);
            RegisterFunction("ushort32", (Func<object[], Kalk.Core.KalkVector<ushort>>)CreateUShort32);
            RegisterFunction("int2", (Func<object[], Kalk.Core.KalkVector<int>>)CreateInt2);
            RegisterFunction("int3", (Func<object[], Kalk.Core.KalkVector<int>>)CreateInt3);
            RegisterFunction("int4", (Func<object[], Kalk.Core.KalkVector<int>>)CreateInt4);
            RegisterFunction("int8", (Func<object[], Kalk.Core.KalkVector<int>>)CreateInt8);
            RegisterFunction("int16", (Func<object[], Kalk.Core.KalkVector<int>>)CreateInt16);
            RegisterFunction("uint2", (Func<object[], Kalk.Core.KalkVector<uint>>)CreateUInt2);
            RegisterFunction("uint3", (Func<object[], Kalk.Core.KalkVector<uint>>)CreateUInt3);
            RegisterFunction("uint4", (Func<object[], Kalk.Core.KalkVector<uint>>)CreateUInt4);
            RegisterFunction("uint8", (Func<object[], Kalk.Core.KalkVector<uint>>)CreateUInt8);
            RegisterFunction("uint16", (Func<object[], Kalk.Core.KalkVector<uint>>)CreateUInt16);
            RegisterFunction("long2", (Func<object[], Kalk.Core.KalkVector<long>>)CreateLong2);
            RegisterFunction("long3", (Func<object[], Kalk.Core.KalkVector<long>>)CreateLong3);
            RegisterFunction("long4", (Func<object[], Kalk.Core.KalkVector<long>>)CreateLong4);
            RegisterFunction("long8", (Func<object[], Kalk.Core.KalkVector<long>>)CreateLong8);
            RegisterFunction("ulong2", (Func<object[], Kalk.Core.KalkVector<ulong>>)CreateULong2);
            RegisterFunction("ulong3", (Func<object[], Kalk.Core.KalkVector<ulong>>)CreateULong3);
            RegisterFunction("ulong4", (Func<object[], Kalk.Core.KalkVector<ulong>>)CreateULong4);
            RegisterFunction("ulong8", (Func<object[], Kalk.Core.KalkVector<ulong>>)CreateULong8);
            RegisterFunction("bool2", (Func<object[], Kalk.Core.KalkVector<Kalk.Core.KalkBool>>)CreateBool2);
            RegisterFunction("bool3", (Func<object[], Kalk.Core.KalkVector<Kalk.Core.KalkBool>>)CreateBool3);
            RegisterFunction("bool4", (Func<object[], Kalk.Core.KalkVector<Kalk.Core.KalkBool>>)CreateBool4);
            RegisterFunction("bool8", (Func<object[], Kalk.Core.KalkVector<Kalk.Core.KalkBool>>)CreateBool8);
            RegisterFunction("bool16", (Func<object[], Kalk.Core.KalkVector<Kalk.Core.KalkBool>>)CreateBool16);
            RegisterFunction("float2", (Func<object[], Kalk.Core.KalkVector<float>>)CreateFloat2);
            RegisterFunction("float3", (Func<object[], Kalk.Core.KalkVector<float>>)CreateFloat3);
            RegisterFunction("float4", (Func<object[], Kalk.Core.KalkVector<float>>)CreateFloat4);
            RegisterFunction("float8", (Func<object[], Kalk.Core.KalkVector<float>>)CreateFloat8);
            RegisterFunction("float16", (Func<object[], Kalk.Core.KalkVector<float>>)CreateFloat16);
            RegisterFunction("double2", (Func<object[], Kalk.Core.KalkVector<double>>)CreateDouble2);
            RegisterFunction("double3", (Func<object[], Kalk.Core.KalkVector<double>>)CreateDouble3);
            RegisterFunction("double4", (Func<object[], Kalk.Core.KalkVector<double>>)CreateDouble4);
            RegisterFunction("double8", (Func<object[], Kalk.Core.KalkVector<double>>)CreateDouble8);
            RegisterFunction("half2", (Func<object[], Kalk.Core.KalkVector<Kalk.Core.KalkHalf>>)CreateHalf2);
            RegisterFunction("half3", (Func<object[], Kalk.Core.KalkVector<Kalk.Core.KalkHalf>>)CreateHalf3);
            RegisterFunction("half4", (Func<object[], Kalk.Core.KalkVector<Kalk.Core.KalkHalf>>)CreateHalf4);
            RegisterFunction("half8", (Func<object[], Kalk.Core.KalkVector<Kalk.Core.KalkHalf>>)CreateHalf8);
            RegisterFunction("half16", (Func<object[], Kalk.Core.KalkVector<Kalk.Core.KalkHalf>>)CreateHalf16);
            RegisterFunction("half32", (Func<object[], Kalk.Core.KalkVector<Kalk.Core.KalkHalf>>)CreateHalf32);
            RegisterFunction("bool2x2", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkBool>>)CreateBool2x2);
            RegisterFunction("bool2x3", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkBool>>)CreateBool2x3);
            RegisterFunction("bool2x4", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkBool>>)CreateBool2x4);
            RegisterFunction("bool3x2", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkBool>>)CreateBool3x2);
            RegisterFunction("bool3x3", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkBool>>)CreateBool3x3);
            RegisterFunction("bool3x4", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkBool>>)CreateBool3x4);
            RegisterFunction("bool4x2", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkBool>>)CreateBool4x2);
            RegisterFunction("bool4x3", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkBool>>)CreateBool4x3);
            RegisterFunction("bool4x4", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkBool>>)CreateBool4x4);
            RegisterFunction("int2x2", (Func<object[], Kalk.Core.KalkMatrix<int>>)CreateInt2x2);
            RegisterFunction("int2x3", (Func<object[], Kalk.Core.KalkMatrix<int>>)CreateInt2x3);
            RegisterFunction("int2x4", (Func<object[], Kalk.Core.KalkMatrix<int>>)CreateInt2x4);
            RegisterFunction("int3x2", (Func<object[], Kalk.Core.KalkMatrix<int>>)CreateInt3x2);
            RegisterFunction("int3x3", (Func<object[], Kalk.Core.KalkMatrix<int>>)CreateInt3x3);
            RegisterFunction("int3x4", (Func<object[], Kalk.Core.KalkMatrix<int>>)CreateInt3x4);
            RegisterFunction("int4x2", (Func<object[], Kalk.Core.KalkMatrix<int>>)CreateInt4x2);
            RegisterFunction("int4x3", (Func<object[], Kalk.Core.KalkMatrix<int>>)CreateInt4x3);
            RegisterFunction("int4x4", (Func<object[], Kalk.Core.KalkMatrix<int>>)CreateInt4x4);
            RegisterFunction("float2x2", (Func<object[], Kalk.Core.KalkMatrix<float>>)CreateFloat2x2);
            RegisterFunction("float2x3", (Func<object[], Kalk.Core.KalkMatrix<float>>)CreateFloat2x3);
            RegisterFunction("float2x4", (Func<object[], Kalk.Core.KalkMatrix<float>>)CreateFloat2x4);
            RegisterFunction("float3x2", (Func<object[], Kalk.Core.KalkMatrix<float>>)CreateFloat3x2);
            RegisterFunction("float3x3", (Func<object[], Kalk.Core.KalkMatrix<float>>)CreateFloat3x3);
            RegisterFunction("float3x4", (Func<object[], Kalk.Core.KalkMatrix<float>>)CreateFloat3x4);
            RegisterFunction("float4x2", (Func<object[], Kalk.Core.KalkMatrix<float>>)CreateFloat4x2);
            RegisterFunction("float4x3", (Func<object[], Kalk.Core.KalkMatrix<float>>)CreateFloat4x3);
            RegisterFunction("float4x4", (Func<object[], Kalk.Core.KalkMatrix<float>>)CreateFloat4x4);
            RegisterFunction("double2x2", (Func<object[], Kalk.Core.KalkMatrix<double>>)CreateDouble2x2);
            RegisterFunction("double2x3", (Func<object[], Kalk.Core.KalkMatrix<double>>)CreateDouble2x3);
            RegisterFunction("double2x4", (Func<object[], Kalk.Core.KalkMatrix<double>>)CreateDouble2x4);
            RegisterFunction("double3x2", (Func<object[], Kalk.Core.KalkMatrix<double>>)CreateDouble3x2);
            RegisterFunction("double3x3", (Func<object[], Kalk.Core.KalkMatrix<double>>)CreateDouble3x3);
            RegisterFunction("double3x4", (Func<object[], Kalk.Core.KalkMatrix<double>>)CreateDouble3x4);
            RegisterFunction("double4x2", (Func<object[], Kalk.Core.KalkMatrix<double>>)CreateDouble4x2);
            RegisterFunction("double4x3", (Func<object[], Kalk.Core.KalkMatrix<double>>)CreateDouble4x3);
            RegisterFunction("double4x4", (Func<object[], Kalk.Core.KalkMatrix<double>>)CreateDouble4x4);
            RegisterFunction("half2x2", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkHalf>>)CreateHalf2x2);
            RegisterFunction("half2x3", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkHalf>>)CreateHalf2x3);
            RegisterFunction("half2x4", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkHalf>>)CreateHalf2x4);
            RegisterFunction("half3x2", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkHalf>>)CreateHalf3x2);
            RegisterFunction("half3x3", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkHalf>>)CreateHalf3x3);
            RegisterFunction("half3x4", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkHalf>>)CreateHalf3x4);
            RegisterFunction("half4x2", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkHalf>>)CreateHalf4x2);
            RegisterFunction("half4x3", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkHalf>>)CreateHalf4x3);
            RegisterFunction("half4x4", (Func<object[], Kalk.Core.KalkMatrix<Kalk.Core.KalkHalf>>)CreateHalf4x4);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["byte"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates an unsigned byte value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"An unsigned byte value";
                descriptor.Example = @"    >>> byte
    # byte
    out = 0
    >>> byte 0
    # byte(0)
    out = 0
    >>> byte 255
    # byte(255)
    out = 255
";
            }
            {
                var descriptor = Descriptors["sbyte"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates a signed-byte value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"A signed-byte value";
                descriptor.Example = @"    >>> sbyte
    # sbyte
    out = 0
    >>> sbyte 0
    # sbyte(0)
    out = 0
    >>> sbyte 127
    # sbyte(127)
    out = 127
    >>> sbyte(-128)
    # sbyte(-128)
    out = -128
";
            }
            {
                var descriptor = Descriptors["short"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates a signed-short (16-bit) value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"A signed-short (16-bit) value";
                descriptor.Example = @"    >>> short
    # short
    out = 0
    >>> short 0
    # short(0)
    out = 0
    >>> short 32767
    # short(32767)
    out = 32_767
    >>> short(-32768)
    # short(-32768)
    out = -32_768
    >>> short 32768
    Unable to convert type `int` to `short`
";
            }
            {
                var descriptor = Descriptors["ushort"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates an unsigned short (16-bit) value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"An unsigned short (16-bit) value";
                descriptor.Example = @"    >>> ushort
    # ushort
    out = 0
    >>> ushort 0
    # ushort(0)
    out = 0
    >>> ushort 65535
    # ushort(65535)
    out = 65_535
";
            }
            {
                var descriptor = Descriptors["uint"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates an unsigned int (32-bit) value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"An unsigned int (32-bit) value";
                descriptor.Example = @"    >>> uint
    # uint
    out = 0
    >>> uint 0
    # uint(0)
    out = 0
    >>> uint(1<<32 - 1)
    # uint(1 << 32 - 1)
    out = 4_294_967_295
";
            }
            {
                var descriptor = Descriptors["int"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates a signed-int (32-bit) value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"A signed-int (32-bit) value";
                descriptor.Example = @"    >>> int
    # int
    out = 0
    >>> int 0
    # int(0)
    out = 0
    >>> int(1 << 31 - 1)
    # int(1 << 31 - 1)
    out = 2_147_483_647
    >>> int(-(1<<31))
    # int(-(1 << 31))
    out = -2_147_483_648
";
            }
            {
                var descriptor = Descriptors["ulong"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates an unsigned long (64-bit) value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"An unsigned long (64-bit) value";
                descriptor.Example = @"    >>> ulong
    # ulong
    out = 0
    >>> ulong 0
    # ulong(0)
    out = 0
    >>> ulong(1 << 64 - 1)
    # ulong(1 << 64 - 1)
    out = 18_446_744_073_709_551_615
";
            }
            {
                var descriptor = Descriptors["long"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates a signed-long (64-bit) value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"A signed-long (64-bit) value";
                descriptor.Example = @"    >>> long
    # long
    out = 0
    >>> long 0
    # long(0)
    out = 0
    >>> long(1 << 63 - 1)
    # long(1 << 63 - 1)
    out = 9_223_372_036_854_775_807
    >>> long(-(1<<63))
    # long(-(1 << 63))
    out = -9_223_372_036_854_775_808
";
            }
            {
                var descriptor = Descriptors["bool"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates a boolean value (32-bit) value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"A boolean (32-bit) value";
                descriptor.Example = @"    >>> bool 1
    # bool(1)
    out = true
    >>> bool 0
    # bool(0)
    out = false
    >>> bool true
    # bool(true)
    out = true
    >>> bool false
    # bool(false)
    out = false
";
            }
            {
                var descriptor = Descriptors["float"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates a float value (32-bit) value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"A float (32-bit) value";
                descriptor.Example = @"    >>> float(1)
    # float(1)
    out = 1
    >>> float(-1)
    # float(-1)
    out = -1
    >>> float(100000000000)
    # float(100000000000)
    out = 1E+11
";
            }
            {
                var descriptor = Descriptors["half"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates a half float value (16-bit) value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"A half float (16-bit) value";
                descriptor.Example = @"    >>> half(1)
    # half(1)
    out = 1
    >>> half(-1)
    # half(-1)
    out = -1
    >>> half(1000.5)
    # half(1000.5)
    out = 1000.5
    >>> kind out
    # kind(out)
    out = ""half""
";
            }
            {
                var descriptor = Descriptors["double"];
                descriptor.Category = "Type Constructors";
                descriptor.Description = @"Creates a double value (64-bit) value.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"The input value.")  { IsOptional = true });
                descriptor.Returns = @"A double (64-bit) value";
                descriptor.Example = @"    >>> double(1)
    # double(1)
    out = 1
    >>> double(-1)
    # double(-1)
    out = -1
    >>> double(100000000000)
    # double(100000000000)
    out = 100000000000
    >>> double(1<<200)
    # double(1 << 200)
    out = 1.6069380442589903E+60
";
            }
            {
                var descriptor = Descriptors["vector"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of the specified element type, with the number of elements and optional values.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("name", @"The element type of the vector (e.g float).")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("dimension", @"The dimension of the vector.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The optional values (must have 1 or dimension elements).")  { IsOptional = false });
                descriptor.Returns = @"A matrix of the specified row x column.";
                descriptor.Example = @"    >>> vector(float, 4, 5..8)
    # vector(float, 4, 5..8)
    out = float4(5, 6, 7, 8)
";
            }
            {
                var descriptor = Descriptors["rgb"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates an rgb vector type with the specified argument values.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector (3). The arguments can be:
    - No values: All items of the rgb vector are initialized with the value 0.
    - an integer value: `rgb(0xAABBCC)` will extract the RGB 8-bits component values (AA: R, BB: G, CC: B).
    - a string value: `rgb(""#AABBCC"")` or `rgb(""AABBCC"")` will extract the RGB 8-bits component values (AA: R, BB: G, CC: B).
    - an array value: `rgb([0xAA,0xBB,0xCC])` will initialize rgb elements with the array elements. The size of the array must match the size of the rgb vector (3).
    - A combination of vectors/single values (e.g `rgb(float3(0.1, 0.2, 0.3)`).")  { IsOptional = false });
                descriptor.Returns = @"A rgb vector initialized with the specified arguments";
                descriptor.Example = @"    >>> rgb(0xAABBCC)
    # rgb(11189196)
    out = rgb(170, 187, 204) ## AABBCC ##
    >>> rgb(""#AABBCC"")
    # rgb(""#AABBCC"")
    out = rgb(170, 187, 204) ## AABBCC ##
    >>> rgb(""AABBCC"")
    # rgb(""AABBCC"")
    out = rgb(170, 187, 204) ## AABBCC ##
    >>> rgb([0xAA,0xBB,0xCC])
    # rgb([170,187,204])
    out = rgb(170, 187, 204) ## AABBCC ##
    >>> out.xyz
    # out.xyz
    out = float3(0.6666667, 0.73333335, 0.8)
    >>> rgb(out)
    # rgb(out)
    out = rgb(170, 187, 204) ## AABBCC ##
";
            }
            {
                var descriptor = Descriptors["rgba"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates an rgba vector type with the specified argument values.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector (4). The arguments can be:
    - No values: All items of the rgba vector are initialized with the value 0.
    - an integer value: `rgba(0xFFAABBCC)` will extract the RGB 8-bits component values (FF: A, AA: R, BB: G, CC: B).
    - a string value: `rgba(""#FFAABBCC"")` or `rgba(""FFAABBCC"")` will extract the RGB 8-bits component values (FF: A, AA: R, BB: G, CC: B).
    - an array value: `rgba([0xAA,0xBB,0xCC,0xFF])` will initialize rgba elements with the array elements. The size of the array must match the size of the rgb vector (3).
    - A combination of vectors/single values (e.g `rgba(float4(0.1, 0.2, 0.3, 1.0)`).")  { IsOptional = false });
                descriptor.Returns = @"A rgb vector initialized with the specified arguments";
                descriptor.Example = @"    >>> rgba(0xFFAABBCC)
    # rgba(-5588020)
    out = rgba(170, 187, 204, 255) ## AABBCCFF ##
    >>> rgba(""#FFAABBCC"")
    # rgba(""#FFAABBCC"")
    out = rgba(170, 187, 204, 255) ## AABBCCFF ##
    >>> rgba(""FFAABBCC"")
    # rgba(""FFAABBCC"")
    out = rgba(170, 187, 204, 255) ## AABBCCFF ##
    >>> rgba([0xAA,0xBB,0xCC,0xFF])
    # rgba([170,187,204,255])
    out = rgba(170, 187, 204, 255) ## AABBCCFF ##
    >>> out.xyzw
    # out.xyzw
    out = float4(0.6666667, 0.73333335, 0.8, 1)
    >>> rgba(out)
    # rgba(out)
    out = rgba(170, 187, 204, 255) ## AABBCCFF ##
";
            }
            {
                var descriptor = Descriptors["matrix"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a matrix of the specified element type, number of rows and columns and optional values.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("name", @"The element type of the matrix (e.g float).")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("row", @"The number of rows.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("column", @"The number of columns.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The optional values (must have 1 or row x column elements).")  { IsOptional = false });
                descriptor.Returns = @"A matrix of the specified row x column.";
                descriptor.Example = @"    >>> matrix(float,4,3,1..12)
    # matrix(float, 4, 3, 1..12)
    out = float4x3(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
          # col  0           1           2           / row
          float3(1         , 2         , 3         ) # 0
          float3(4         , 5         , 6         ) # 1
          float3(7         , 8         , 9         ) # 2
          float3(10        , 11        , 12        ) # 3
";
            }
            {
                var descriptor = Descriptors["byte16"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 16 `byte` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `byte16(123)` will initialize all elements with 123.
    - an array value: `byte16(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `byte4(byte2(1,2), byte2(3,4))` or `byte4(byte3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A byte16 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> byte16
    # byte16
    out = byte16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> byte16(1..16)
    # byte16(1..16)
    out = byte16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
    >>> byte16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    # byte16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    out = byte16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
";
            }
            {
                var descriptor = Descriptors["byte32"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 32 `byte` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `byte32(123)` will initialize all elements with 123.
    - an array value: `byte32(1..32)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `byte4(byte2(1,2), byte2(3,4))` or `byte4(byte3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A byte32 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> byte32
    # byte32
    out = byte32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> byte32(1..32)
    # byte32(1..32)
    out = byte32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
";
            }
            {
                var descriptor = Descriptors["byte64"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 64 `byte` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `byte64(123)` will initialize all elements with 123.
    - an array value: `byte64(1..64)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `byte4(byte2(1,2), byte2(3,4))` or `byte4(byte3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A byte64 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> byte64
    # byte64
    out = byte64(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> byte64(1..64)
    # byte64(1..64)
    out = byte64(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64)
";
            }
            {
                var descriptor = Descriptors["sbyte16"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 16 `sbyte` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `sbyte16(123)` will initialize all elements with 123.
    - an array value: `sbyte16(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `sbyte4(sbyte2(1,2), sbyte2(3,4))` or `sbyte4(sbyte3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A sbyte16 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> sbyte16
    # sbyte16
    out = sbyte16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> sbyte16(1..16)
    # sbyte16(1..16)
    out = sbyte16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
    >>> sbyte16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    # sbyte16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    out = sbyte16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
";
            }
            {
                var descriptor = Descriptors["sbyte32"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 32 `sbyte` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `sbyte32(123)` will initialize all elements with 123.
    - an array value: `sbyte32(1..32)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `sbyte4(sbyte2(1,2), sbyte2(3,4))` or `sbyte4(sbyte3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A sbyte32 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> sbyte32
    # sbyte32
    out = sbyte32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> sbyte32(1..32)
    # sbyte32(1..32)
    out = sbyte32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
";
            }
            {
                var descriptor = Descriptors["sbyte64"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 64 `sbyte` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `sbyte64(123)` will initialize all elements with 123.
    - an array value: `sbyte64(1..64)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `sbyte4(sbyte2(1,2), sbyte2(3,4))` or `sbyte4(sbyte3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A sbyte64 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> sbyte64
    # sbyte64
    out = sbyte64(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> sbyte64(1..64)
    # sbyte64(1..64)
    out = sbyte64(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64)
";
            }
            {
                var descriptor = Descriptors["short2"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 2 `short` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `short2(123)` will initialize all elements with 123.
    - an array value: `short2(1..2)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `short4(short2(1,2), short2(3,4))` or `short4(short3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A short2 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> short2
    # short2
    out = short2(0, 0)
    >>> short2(1..2)
    # short2(1..2)
    out = short2(1, 2)
    >>> short2(10, 11)
    # short2(10, 11)
    out = short2(10, 11)
";
            }
            {
                var descriptor = Descriptors["short4"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 4 `short` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `short4(123)` will initialize all elements with 123.
    - an array value: `short4(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `short4(short2(1,2), short2(3,4))` or `short4(short3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A short4 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> short4
    # short4
    out = short4(0, 0, 0, 0)
    >>> short4(1..4)
    # short4(1..4)
    out = short4(1, 2, 3, 4)
    >>> short4(10, 11, 12, 13)
    # short4(10, 11, 12, 13)
    out = short4(10, 11, 12, 13)
";
            }
            {
                var descriptor = Descriptors["short8"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 8 `short` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `short8(123)` will initialize all elements with 123.
    - an array value: `short8(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `short4(short2(1,2), short2(3,4))` or `short4(short3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A short8 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> short8
    # short8
    out = short8(0, 0, 0, 0, 0, 0, 0, 0)
    >>> short8(1..8)
    # short8(1..8)
    out = short8(1, 2, 3, 4, 5, 6, 7, 8)
    >>> short8(10, 11, 12, 13, 14, 15, 16, 17)
    # short8(10, 11, 12, 13, 14, 15, 16, 17)
    out = short8(10, 11, 12, 13, 14, 15, 16, 17)
";
            }
            {
                var descriptor = Descriptors["short16"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 16 `short` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `short16(123)` will initialize all elements with 123.
    - an array value: `short16(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `short4(short2(1,2), short2(3,4))` or `short4(short3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A short16 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> short16
    # short16
    out = short16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> short16(1..16)
    # short16(1..16)
    out = short16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
    >>> short16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    # short16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    out = short16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
";
            }
            {
                var descriptor = Descriptors["short32"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 32 `short` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `short32(123)` will initialize all elements with 123.
    - an array value: `short32(1..32)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `short4(short2(1,2), short2(3,4))` or `short4(short3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A short32 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> short32
    # short32
    out = short32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> short32(1..32)
    # short32(1..32)
    out = short32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
";
            }
            {
                var descriptor = Descriptors["ushort2"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 2 `ushort` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `ushort2(123)` will initialize all elements with 123.
    - an array value: `ushort2(1..2)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `ushort4(ushort2(1,2), ushort2(3,4))` or `ushort4(ushort3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A ushort2 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> ushort2
    # ushort2
    out = ushort2(0, 0)
    >>> ushort2(1..2)
    # ushort2(1..2)
    out = ushort2(1, 2)
    >>> ushort2(10, 11)
    # ushort2(10, 11)
    out = ushort2(10, 11)
";
            }
            {
                var descriptor = Descriptors["ushort4"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 4 `ushort` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `ushort4(123)` will initialize all elements with 123.
    - an array value: `ushort4(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `ushort4(ushort2(1,2), ushort2(3,4))` or `ushort4(ushort3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A ushort4 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> ushort4
    # ushort4
    out = ushort4(0, 0, 0, 0)
    >>> ushort4(1..4)
    # ushort4(1..4)
    out = ushort4(1, 2, 3, 4)
    >>> ushort4(10, 11, 12, 13)
    # ushort4(10, 11, 12, 13)
    out = ushort4(10, 11, 12, 13)
";
            }
            {
                var descriptor = Descriptors["ushort8"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 8 `ushort` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `ushort8(123)` will initialize all elements with 123.
    - an array value: `ushort8(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `ushort4(ushort2(1,2), ushort2(3,4))` or `ushort4(ushort3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A ushort8 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> ushort8
    # ushort8
    out = ushort8(0, 0, 0, 0, 0, 0, 0, 0)
    >>> ushort8(1..8)
    # ushort8(1..8)
    out = ushort8(1, 2, 3, 4, 5, 6, 7, 8)
    >>> ushort8(10, 11, 12, 13, 14, 15, 16, 17)
    # ushort8(10, 11, 12, 13, 14, 15, 16, 17)
    out = ushort8(10, 11, 12, 13, 14, 15, 16, 17)
";
            }
            {
                var descriptor = Descriptors["ushort16"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 16 `ushort` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `ushort16(123)` will initialize all elements with 123.
    - an array value: `ushort16(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `ushort4(ushort2(1,2), ushort2(3,4))` or `ushort4(ushort3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A ushort16 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> ushort16
    # ushort16
    out = ushort16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> ushort16(1..16)
    # ushort16(1..16)
    out = ushort16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
    >>> ushort16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    # ushort16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    out = ushort16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
";
            }
            {
                var descriptor = Descriptors["ushort32"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 32 `ushort` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `ushort32(123)` will initialize all elements with 123.
    - an array value: `ushort32(1..32)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `ushort4(ushort2(1,2), ushort2(3,4))` or `ushort4(ushort3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A ushort32 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> ushort32
    # ushort32
    out = ushort32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> ushort32(1..32)
    # ushort32(1..32)
    out = ushort32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
";
            }
            {
                var descriptor = Descriptors["int2"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 2 `int` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int2(123)` will initialize all elements with 123.
    - an array value: `int2(1..2)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int4(int2(1,2), int2(3,4))` or `int4(int3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A int2 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> int2
    # int2
    out = int2(0, 0)
    >>> int2(1..2)
    # int2(1..2)
    out = int2(1, 2)
    >>> int2(10, 11)
    # int2(10, 11)
    out = int2(10, 11)
";
            }
            {
                var descriptor = Descriptors["int3"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 3 `int` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int3(123)` will initialize all elements with 123.
    - an array value: `int3(1..3)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int4(int2(1,2), int2(3,4))` or `int4(int3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A int3 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> int3
    # int3
    out = int3(0, 0, 0)
    >>> int3(1..3)
    # int3(1..3)
    out = int3(1, 2, 3)
    >>> int3(10, 11, 12)
    # int3(10, 11, 12)
    out = int3(10, 11, 12)
";
            }
            {
                var descriptor = Descriptors["int4"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 4 `int` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int4(123)` will initialize all elements with 123.
    - an array value: `int4(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int4(int2(1,2), int2(3,4))` or `int4(int3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A int4 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> int4
    # int4
    out = int4(0, 0, 0, 0)
    >>> int4(1..4)
    # int4(1..4)
    out = int4(1, 2, 3, 4)
    >>> int4(10, 11, 12, 13)
    # int4(10, 11, 12, 13)
    out = int4(10, 11, 12, 13)
";
            }
            {
                var descriptor = Descriptors["int8"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 8 `int` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int8(123)` will initialize all elements with 123.
    - an array value: `int8(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int4(int2(1,2), int2(3,4))` or `int4(int3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A int8 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> int8
    # int8
    out = int8(0, 0, 0, 0, 0, 0, 0, 0)
    >>> int8(1..8)
    # int8(1..8)
    out = int8(1, 2, 3, 4, 5, 6, 7, 8)
    >>> int8(10, 11, 12, 13, 14, 15, 16, 17)
    # int8(10, 11, 12, 13, 14, 15, 16, 17)
    out = int8(10, 11, 12, 13, 14, 15, 16, 17)
";
            }
            {
                var descriptor = Descriptors["int16"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 16 `int` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int16(123)` will initialize all elements with 123.
    - an array value: `int16(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int4(int2(1,2), int2(3,4))` or `int4(int3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A int16 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> int16
    # int16
    out = int16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> int16(1..16)
    # int16(1..16)
    out = int16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
    >>> int16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    # int16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    out = int16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
";
            }
            {
                var descriptor = Descriptors["uint2"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 2 `uint` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `uint2(123)` will initialize all elements with 123.
    - an array value: `uint2(1..2)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `uint4(uint2(1,2), uint2(3,4))` or `uint4(uint3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A uint2 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> uint2
    # uint2
    out = uint2(0, 0)
    >>> uint2(1..2)
    # uint2(1..2)
    out = uint2(1, 2)
    >>> uint2(10, 11)
    # uint2(10, 11)
    out = uint2(10, 11)
";
            }
            {
                var descriptor = Descriptors["uint3"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 3 `uint` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `uint3(123)` will initialize all elements with 123.
    - an array value: `uint3(1..3)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `uint4(uint2(1,2), uint2(3,4))` or `uint4(uint3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A uint3 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> uint3
    # uint3
    out = uint3(0, 0, 0)
    >>> uint3(1..3)
    # uint3(1..3)
    out = uint3(1, 2, 3)
    >>> uint3(10, 11, 12)
    # uint3(10, 11, 12)
    out = uint3(10, 11, 12)
";
            }
            {
                var descriptor = Descriptors["uint4"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 4 `uint` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `uint4(123)` will initialize all elements with 123.
    - an array value: `uint4(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `uint4(uint2(1,2), uint2(3,4))` or `uint4(uint3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A uint4 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> uint4
    # uint4
    out = uint4(0, 0, 0, 0)
    >>> uint4(1..4)
    # uint4(1..4)
    out = uint4(1, 2, 3, 4)
    >>> uint4(10, 11, 12, 13)
    # uint4(10, 11, 12, 13)
    out = uint4(10, 11, 12, 13)
";
            }
            {
                var descriptor = Descriptors["uint8"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 8 `uint` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `uint8(123)` will initialize all elements with 123.
    - an array value: `uint8(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `uint4(uint2(1,2), uint2(3,4))` or `uint4(uint3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A uint8 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> uint8
    # uint8
    out = uint8(0, 0, 0, 0, 0, 0, 0, 0)
    >>> uint8(1..8)
    # uint8(1..8)
    out = uint8(1, 2, 3, 4, 5, 6, 7, 8)
    >>> uint8(10, 11, 12, 13, 14, 15, 16, 17)
    # uint8(10, 11, 12, 13, 14, 15, 16, 17)
    out = uint8(10, 11, 12, 13, 14, 15, 16, 17)
";
            }
            {
                var descriptor = Descriptors["uint16"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 16 `uint` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `uint16(123)` will initialize all elements with 123.
    - an array value: `uint16(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `uint4(uint2(1,2), uint2(3,4))` or `uint4(uint3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A uint16 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> uint16
    # uint16
    out = uint16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> uint16(1..16)
    # uint16(1..16)
    out = uint16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
    >>> uint16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    # uint16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    out = uint16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
";
            }
            {
                var descriptor = Descriptors["long2"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 2 `long` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `long2(123)` will initialize all elements with 123.
    - an array value: `long2(1..2)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `long4(long2(1,2), long2(3,4))` or `long4(long3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A long2 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> long2
    # long2
    out = long2(0, 0)
    >>> long2(1..2)
    # long2(1..2)
    out = long2(1, 2)
    >>> long2(10, 11)
    # long2(10, 11)
    out = long2(10, 11)
";
            }
            {
                var descriptor = Descriptors["long3"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 3 `long` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `long3(123)` will initialize all elements with 123.
    - an array value: `long3(1..3)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `long4(long2(1,2), long2(3,4))` or `long4(long3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A long3 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> long3
    # long3
    out = long3(0, 0, 0)
    >>> long3(1..3)
    # long3(1..3)
    out = long3(1, 2, 3)
    >>> long3(10, 11, 12)
    # long3(10, 11, 12)
    out = long3(10, 11, 12)
";
            }
            {
                var descriptor = Descriptors["long4"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 4 `long` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `long4(123)` will initialize all elements with 123.
    - an array value: `long4(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `long4(long2(1,2), long2(3,4))` or `long4(long3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A long4 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> long4
    # long4
    out = long4(0, 0, 0, 0)
    >>> long4(1..4)
    # long4(1..4)
    out = long4(1, 2, 3, 4)
    >>> long4(10, 11, 12, 13)
    # long4(10, 11, 12, 13)
    out = long4(10, 11, 12, 13)
";
            }
            {
                var descriptor = Descriptors["long8"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 8 `long` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `long8(123)` will initialize all elements with 123.
    - an array value: `long8(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `long4(long2(1,2), long2(3,4))` or `long4(long3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A long8 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> long8
    # long8
    out = long8(0, 0, 0, 0, 0, 0, 0, 0)
    >>> long8(1..8)
    # long8(1..8)
    out = long8(1, 2, 3, 4, 5, 6, 7, 8)
    >>> long8(10, 11, 12, 13, 14, 15, 16, 17)
    # long8(10, 11, 12, 13, 14, 15, 16, 17)
    out = long8(10, 11, 12, 13, 14, 15, 16, 17)
";
            }
            {
                var descriptor = Descriptors["ulong2"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 2 `ulong` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `ulong2(123)` will initialize all elements with 123.
    - an array value: `ulong2(1..2)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `ulong4(ulong2(1,2), ulong2(3,4))` or `ulong4(ulong3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A ulong2 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> ulong2
    # ulong2
    out = ulong2(0, 0)
    >>> ulong2(1..2)
    # ulong2(1..2)
    out = ulong2(1, 2)
    >>> ulong2(10, 11)
    # ulong2(10, 11)
    out = ulong2(10, 11)
";
            }
            {
                var descriptor = Descriptors["ulong3"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 3 `ulong` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `ulong3(123)` will initialize all elements with 123.
    - an array value: `ulong3(1..3)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `ulong4(ulong2(1,2), ulong2(3,4))` or `ulong4(ulong3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A ulong3 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> ulong3
    # ulong3
    out = ulong3(0, 0, 0)
    >>> ulong3(1..3)
    # ulong3(1..3)
    out = ulong3(1, 2, 3)
    >>> ulong3(10, 11, 12)
    # ulong3(10, 11, 12)
    out = ulong3(10, 11, 12)
";
            }
            {
                var descriptor = Descriptors["ulong4"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 4 `ulong` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `ulong4(123)` will initialize all elements with 123.
    - an array value: `ulong4(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `ulong4(ulong2(1,2), ulong2(3,4))` or `ulong4(ulong3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A ulong4 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> ulong4
    # ulong4
    out = ulong4(0, 0, 0, 0)
    >>> ulong4(1..4)
    # ulong4(1..4)
    out = ulong4(1, 2, 3, 4)
    >>> ulong4(10, 11, 12, 13)
    # ulong4(10, 11, 12, 13)
    out = ulong4(10, 11, 12, 13)
";
            }
            {
                var descriptor = Descriptors["ulong8"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 8 `ulong` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `ulong8(123)` will initialize all elements with 123.
    - an array value: `ulong8(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `ulong4(ulong2(1,2), ulong2(3,4))` or `ulong4(ulong3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A ulong8 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> ulong8
    # ulong8
    out = ulong8(0, 0, 0, 0, 0, 0, 0, 0)
    >>> ulong8(1..8)
    # ulong8(1..8)
    out = ulong8(1, 2, 3, 4, 5, 6, 7, 8)
    >>> ulong8(10, 11, 12, 13, 14, 15, 16, 17)
    # ulong8(10, 11, 12, 13, 14, 15, 16, 17)
    out = ulong8(10, 11, 12, 13, 14, 15, 16, 17)
";
            }
            {
                var descriptor = Descriptors["bool2"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 2 `bool` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: The vector is initialized with false values.
    - a single value: `bool2(true)` will initialize all elements with 123.
    - an array value: `bool2([true, false, ...])` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool4(bool2(true,false), bool2(false,true))` or `bool4(bool3(false,true,true), false)`)")  { IsOptional = false });
                descriptor.Returns = @"A bool2 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> bool2(true)
    # bool2(true)
    out = bool2(true, true)
";
            }
            {
                var descriptor = Descriptors["bool3"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 3 `bool` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: The vector is initialized with false values.
    - a single value: `bool3(true)` will initialize all elements with 123.
    - an array value: `bool3([true, false, ...])` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool4(bool2(true,false), bool2(false,true))` or `bool4(bool3(false,true,true), false)`)")  { IsOptional = false });
                descriptor.Returns = @"A bool3 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> bool3(true)
    # bool3(true)
    out = bool3(true, true, true)
";
            }
            {
                var descriptor = Descriptors["bool4"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 4 `bool` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: The vector is initialized with false values.
    - a single value: `bool4(true)` will initialize all elements with 123.
    - an array value: `bool4([true, false, ...])` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool4(bool2(true,false), bool2(false,true))` or `bool4(bool3(false,true,true), false)`)")  { IsOptional = false });
                descriptor.Returns = @"A bool4 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> bool4(true)
    # bool4(true)
    out = bool4(true, true, true, true)
";
            }
            {
                var descriptor = Descriptors["bool8"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 8 `bool` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: The vector is initialized with false values.
    - a single value: `bool8(true)` will initialize all elements with 123.
    - an array value: `bool8([true, false, ...])` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool4(bool2(true,false), bool2(false,true))` or `bool4(bool3(false,true,true), false)`)")  { IsOptional = false });
                descriptor.Returns = @"A bool8 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> bool8(true)
    # bool8(true)
    out = bool8(true, true, true, true, true, true, true, true)
";
            }
            {
                var descriptor = Descriptors["bool16"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 16 `bool` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: The vector is initialized with false values.
    - a single value: `bool16(true)` will initialize all elements with 123.
    - an array value: `bool16([true, false, ...])` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool4(bool2(true,false), bool2(false,true))` or `bool4(bool3(false,true,true), false)`)")  { IsOptional = false });
                descriptor.Returns = @"A bool16 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> bool16(true)
    # bool16(true)
    out = bool16(true, true, true, true, true, true, true, true, true, true, true, true, true, true, true, true)
";
            }
            {
                var descriptor = Descriptors["float2"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 2 `float` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float2(123)` will initialize all elements with 123.
    - an array value: `float2(1..2)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float4(float2(1,2), float2(3,4))` or `float4(float3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A float2 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> float2
    # float2
    out = float2(0, 0)
    >>> float2(1..2)
    # float2(1..2)
    out = float2(1, 2)
    >>> float2(10, 11)
    # float2(10, 11)
    out = float2(10, 11)
";
            }
            {
                var descriptor = Descriptors["float3"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 3 `float` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float3(123)` will initialize all elements with 123.
    - an array value: `float3(1..3)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float4(float2(1,2), float2(3,4))` or `float4(float3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A float3 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> float3
    # float3
    out = float3(0, 0, 0)
    >>> float3(1..3)
    # float3(1..3)
    out = float3(1, 2, 3)
    >>> float3(10, 11, 12)
    # float3(10, 11, 12)
    out = float3(10, 11, 12)
";
            }
            {
                var descriptor = Descriptors["float4"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 4 `float` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float4(123)` will initialize all elements with 123.
    - an array value: `float4(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float4(float2(1,2), float2(3,4))` or `float4(float3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A float4 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> float4
    # float4
    out = float4(0, 0, 0, 0)
    >>> float4(1..4)
    # float4(1..4)
    out = float4(1, 2, 3, 4)
    >>> float4(10, 11, 12, 13)
    # float4(10, 11, 12, 13)
    out = float4(10, 11, 12, 13)
";
            }
            {
                var descriptor = Descriptors["float8"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 8 `float` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float8(123)` will initialize all elements with 123.
    - an array value: `float8(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float4(float2(1,2), float2(3,4))` or `float4(float3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A float8 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> float8
    # float8
    out = float8(0, 0, 0, 0, 0, 0, 0, 0)
    >>> float8(1..8)
    # float8(1..8)
    out = float8(1, 2, 3, 4, 5, 6, 7, 8)
    >>> float8(10, 11, 12, 13, 14, 15, 16, 17)
    # float8(10, 11, 12, 13, 14, 15, 16, 17)
    out = float8(10, 11, 12, 13, 14, 15, 16, 17)
";
            }
            {
                var descriptor = Descriptors["float16"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 16 `float` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float16(123)` will initialize all elements with 123.
    - an array value: `float16(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float4(float2(1,2), float2(3,4))` or `float4(float3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A float16 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> float16
    # float16
    out = float16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> float16(1..16)
    # float16(1..16)
    out = float16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
    >>> float16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    # float16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    out = float16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
";
            }
            {
                var descriptor = Descriptors["double2"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 2 `double` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double2(123)` will initialize all elements with 123.
    - an array value: `double2(1..2)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double4(double2(1,2), double2(3,4))` or `double4(double3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A double2 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> double2
    # double2
    out = double2(0, 0)
    >>> double2(1..2)
    # double2(1..2)
    out = double2(1, 2)
    >>> double2(10, 11)
    # double2(10, 11)
    out = double2(10, 11)
";
            }
            {
                var descriptor = Descriptors["double3"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 3 `double` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double3(123)` will initialize all elements with 123.
    - an array value: `double3(1..3)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double4(double2(1,2), double2(3,4))` or `double4(double3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A double3 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> double3
    # double3
    out = double3(0, 0, 0)
    >>> double3(1..3)
    # double3(1..3)
    out = double3(1, 2, 3)
    >>> double3(10, 11, 12)
    # double3(10, 11, 12)
    out = double3(10, 11, 12)
";
            }
            {
                var descriptor = Descriptors["double4"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 4 `double` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double4(123)` will initialize all elements with 123.
    - an array value: `double4(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double4(double2(1,2), double2(3,4))` or `double4(double3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A double4 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> double4
    # double4
    out = double4(0, 0, 0, 0)
    >>> double4(1..4)
    # double4(1..4)
    out = double4(1, 2, 3, 4)
    >>> double4(10, 11, 12, 13)
    # double4(10, 11, 12, 13)
    out = double4(10, 11, 12, 13)
";
            }
            {
                var descriptor = Descriptors["double8"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 8 `double` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double8(123)` will initialize all elements with 123.
    - an array value: `double8(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double4(double2(1,2), double2(3,4))` or `double4(double3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A double8 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> double8
    # double8
    out = double8(0, 0, 0, 0, 0, 0, 0, 0)
    >>> double8(1..8)
    # double8(1..8)
    out = double8(1, 2, 3, 4, 5, 6, 7, 8)
    >>> double8(10, 11, 12, 13, 14, 15, 16, 17)
    # double8(10, 11, 12, 13, 14, 15, 16, 17)
    out = double8(10, 11, 12, 13, 14, 15, 16, 17)
";
            }
            {
                var descriptor = Descriptors["half2"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 2 `half` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half2(123)` will initialize all elements with 123.
    - an array value: `half2(1..2)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half4(half2(1,2), half2(3,4))` or `half4(half3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A half2 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> half2
    # half2
    out = half2(0, 0)
    >>> half2(1..2)
    # half2(1..2)
    out = half2(1, 2)
    >>> half2(10, 11)
    # half2(10, 11)
    out = half2(10, 11)
";
            }
            {
                var descriptor = Descriptors["half3"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 3 `half` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half3(123)` will initialize all elements with 123.
    - an array value: `half3(1..3)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half4(half2(1,2), half2(3,4))` or `half4(half3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A half3 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> half3
    # half3
    out = half3(0, 0, 0)
    >>> half3(1..3)
    # half3(1..3)
    out = half3(1, 2, 3)
    >>> half3(10, 11, 12)
    # half3(10, 11, 12)
    out = half3(10, 11, 12)
";
            }
            {
                var descriptor = Descriptors["half4"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 4 `half` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half4(123)` will initialize all elements with 123.
    - an array value: `half4(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half4(half2(1,2), half2(3,4))` or `half4(half3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A half4 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> half4
    # half4
    out = half4(0, 0, 0, 0)
    >>> half4(1..4)
    # half4(1..4)
    out = half4(1, 2, 3, 4)
    >>> half4(10, 11, 12, 13)
    # half4(10, 11, 12, 13)
    out = half4(10, 11, 12, 13)
";
            }
            {
                var descriptor = Descriptors["half8"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 8 `half` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half8(123)` will initialize all elements with 123.
    - an array value: `half8(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half4(half2(1,2), half2(3,4))` or `half4(half3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A half8 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> half8
    # half8
    out = half8(0, 0, 0, 0, 0, 0, 0, 0)
    >>> half8(1..8)
    # half8(1..8)
    out = half8(1, 2, 3, 4, 5, 6, 7, 8)
    >>> half8(10, 11, 12, 13, 14, 15, 16, 17)
    # half8(10, 11, 12, 13, 14, 15, 16, 17)
    out = half8(10, 11, 12, 13, 14, 15, 16, 17)
";
            }
            {
                var descriptor = Descriptors["half16"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 16 `half` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half16(123)` will initialize all elements with 123.
    - an array value: `half16(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half4(half2(1,2), half2(3,4))` or `half4(half3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A half16 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> half16
    # half16
    out = half16(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> half16(1..16)
    # half16(1..16)
    out = half16(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16)
    >>> half16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    # half16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
    out = half16(10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
";
            }
            {
                var descriptor = Descriptors["half32"];
                descriptor.Category = "Type Vector Constructors";
                descriptor.Description = @"Creates a vector of 32 `half` items.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The vector item values. The total number of values must equal the dimension of the vector. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half32(123)` will initialize all elements with 123.
    - an array value: `half32(1..32)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half4(half2(1,2), half2(3,4))` or `half4(half3(1,2,3), 4)`.")  { IsOptional = false });
                descriptor.Returns = @"A half32 vector initialized with the specified arguments";
                descriptor.Example = @"    >>> half32
    # half32
    out = half32(0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
    >>> half32(1..32)
    # half32(1..32)
    out = half32(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
";
            }
            {
                var descriptor = Descriptors["bool2x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 2 (columns) matrix of bool.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `bool2x2(123)` will initialize all elements with 123.
    - an array value: `bool2x2(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool3x4(bool4(1), bool4(2), bool4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A bool2x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["bool2x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 3 (columns) matrix of bool.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `bool2x3(123)` will initialize all elements with 123.
    - an array value: `bool2x3(1..6)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool3x4(bool4(1), bool4(2), bool4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A bool2x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["bool2x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 4 (columns) matrix of bool.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `bool2x4(123)` will initialize all elements with 123.
    - an array value: `bool2x4(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool3x4(bool4(1), bool4(2), bool4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A bool2x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["bool3x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 2 (columns) matrix of bool.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `bool3x2(123)` will initialize all elements with 123.
    - an array value: `bool3x2(1..6)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool3x4(bool4(1), bool4(2), bool4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A bool3x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["bool3x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 3 (columns) matrix of bool.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `bool3x3(123)` will initialize all elements with 123.
    - an array value: `bool3x3(1..9)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool3x4(bool4(1), bool4(2), bool4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A bool3x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["bool3x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 4 (columns) matrix of bool.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `bool3x4(123)` will initialize all elements with 123.
    - an array value: `bool3x4(1..12)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool3x4(bool4(1), bool4(2), bool4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A bool3x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["bool4x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 2 (columns) matrix of bool.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `bool4x2(123)` will initialize all elements with 123.
    - an array value: `bool4x2(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool3x4(bool4(1), bool4(2), bool4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A bool4x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["bool4x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 3 (columns) matrix of bool.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `bool4x3(123)` will initialize all elements with 123.
    - an array value: `bool4x3(1..12)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool3x4(bool4(1), bool4(2), bool4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A bool4x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["bool4x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 4 (columns) matrix of bool.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `bool4x4(123)` will initialize all elements with 123.
    - an array value: `bool4x4(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `bool3x4(bool4(1), bool4(2), bool4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A bool4x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["int2x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 2 (columns) matrix of int.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int2x2(123)` will initialize all elements with 123.
    - an array value: `int2x2(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int3x4(int4(1), int4(2), int4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A int2x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["int2x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 3 (columns) matrix of int.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int2x3(123)` will initialize all elements with 123.
    - an array value: `int2x3(1..6)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int3x4(int4(1), int4(2), int4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A int2x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["int2x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 4 (columns) matrix of int.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int2x4(123)` will initialize all elements with 123.
    - an array value: `int2x4(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int3x4(int4(1), int4(2), int4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A int2x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["int3x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 2 (columns) matrix of int.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int3x2(123)` will initialize all elements with 123.
    - an array value: `int3x2(1..6)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int3x4(int4(1), int4(2), int4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A int3x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["int3x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 3 (columns) matrix of int.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int3x3(123)` will initialize all elements with 123.
    - an array value: `int3x3(1..9)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int3x4(int4(1), int4(2), int4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A int3x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["int3x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 4 (columns) matrix of int.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int3x4(123)` will initialize all elements with 123.
    - an array value: `int3x4(1..12)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int3x4(int4(1), int4(2), int4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A int3x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["int4x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 2 (columns) matrix of int.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int4x2(123)` will initialize all elements with 123.
    - an array value: `int4x2(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int3x4(int4(1), int4(2), int4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A int4x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["int4x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 3 (columns) matrix of int.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int4x3(123)` will initialize all elements with 123.
    - an array value: `int4x3(1..12)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int3x4(int4(1), int4(2), int4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A int4x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["int4x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 4 (columns) matrix of int.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `int4x4(123)` will initialize all elements with 123.
    - an array value: `int4x4(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `int3x4(int4(1), int4(2), int4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A int4x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["float2x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 2 (columns) matrix of float.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float2x2(123)` will initialize all elements with 123.
    - an array value: `float2x2(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float3x4(float4(1), float4(2), float4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A float2x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["float2x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 3 (columns) matrix of float.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float2x3(123)` will initialize all elements with 123.
    - an array value: `float2x3(1..6)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float3x4(float4(1), float4(2), float4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A float2x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["float2x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 4 (columns) matrix of float.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float2x4(123)` will initialize all elements with 123.
    - an array value: `float2x4(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float3x4(float4(1), float4(2), float4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A float2x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["float3x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 2 (columns) matrix of float.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float3x2(123)` will initialize all elements with 123.
    - an array value: `float3x2(1..6)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float3x4(float4(1), float4(2), float4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A float3x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["float3x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 3 (columns) matrix of float.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float3x3(123)` will initialize all elements with 123.
    - an array value: `float3x3(1..9)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float3x4(float4(1), float4(2), float4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A float3x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["float3x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 4 (columns) matrix of float.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float3x4(123)` will initialize all elements with 123.
    - an array value: `float3x4(1..12)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float3x4(float4(1), float4(2), float4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A float3x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["float4x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 2 (columns) matrix of float.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float4x2(123)` will initialize all elements with 123.
    - an array value: `float4x2(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float3x4(float4(1), float4(2), float4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A float4x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["float4x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 3 (columns) matrix of float.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float4x3(123)` will initialize all elements with 123.
    - an array value: `float4x3(1..12)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float3x4(float4(1), float4(2), float4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A float4x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["float4x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 4 (columns) matrix of float.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `float4x4(123)` will initialize all elements with 123.
    - an array value: `float4x4(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `float3x4(float4(1), float4(2), float4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A float4x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["double2x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 2 (columns) matrix of double.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double2x2(123)` will initialize all elements with 123.
    - an array value: `double2x2(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double3x4(double4(1), double4(2), double4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A double2x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["double2x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 3 (columns) matrix of double.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double2x3(123)` will initialize all elements with 123.
    - an array value: `double2x3(1..6)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double3x4(double4(1), double4(2), double4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A double2x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["double2x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 4 (columns) matrix of double.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double2x4(123)` will initialize all elements with 123.
    - an array value: `double2x4(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double3x4(double4(1), double4(2), double4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A double2x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["double3x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 2 (columns) matrix of double.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double3x2(123)` will initialize all elements with 123.
    - an array value: `double3x2(1..6)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double3x4(double4(1), double4(2), double4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A double3x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["double3x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 3 (columns) matrix of double.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double3x3(123)` will initialize all elements with 123.
    - an array value: `double3x3(1..9)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double3x4(double4(1), double4(2), double4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A double3x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["double3x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 4 (columns) matrix of double.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double3x4(123)` will initialize all elements with 123.
    - an array value: `double3x4(1..12)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double3x4(double4(1), double4(2), double4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A double3x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["double4x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 2 (columns) matrix of double.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double4x2(123)` will initialize all elements with 123.
    - an array value: `double4x2(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double3x4(double4(1), double4(2), double4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A double4x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["double4x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 3 (columns) matrix of double.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double4x3(123)` will initialize all elements with 123.
    - an array value: `double4x3(1..12)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double3x4(double4(1), double4(2), double4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A double4x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["double4x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 4 (columns) matrix of double.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `double4x4(123)` will initialize all elements with 123.
    - an array value: `double4x4(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `double3x4(double4(1), double4(2), double4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A double4x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["half2x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 2 (columns) matrix of half.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half2x2(123)` will initialize all elements with 123.
    - an array value: `half2x2(1..4)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half3x4(half4(1), half4(2), half4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A half2x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["half2x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 3 (columns) matrix of half.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half2x3(123)` will initialize all elements with 123.
    - an array value: `half2x3(1..6)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half3x4(half4(1), half4(2), half4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A half2x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["half2x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 2 (rows) x 4 (columns) matrix of half.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half2x4(123)` will initialize all elements with 123.
    - an array value: `half2x4(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half3x4(half4(1), half4(2), half4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A half2x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["half3x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 2 (columns) matrix of half.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half3x2(123)` will initialize all elements with 123.
    - an array value: `half3x2(1..6)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half3x4(half4(1), half4(2), half4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A half3x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["half3x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 3 (columns) matrix of half.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half3x3(123)` will initialize all elements with 123.
    - an array value: `half3x3(1..9)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half3x4(half4(1), half4(2), half4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A half3x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["half3x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 3 (rows) x 4 (columns) matrix of half.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half3x4(123)` will initialize all elements with 123.
    - an array value: `half3x4(1..12)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half3x4(half4(1), half4(2), half4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A half3x4 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["half4x2"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 2 (columns) matrix of half.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half4x2(123)` will initialize all elements with 123.
    - an array value: `half4x2(1..8)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half3x4(half4(1), half4(2), half4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A half4x2 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["half4x3"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 3 (columns) matrix of half.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half4x3(123)` will initialize all elements with 123.
    - an array value: `half4x3(1..12)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half3x4(half4(1), half4(2), half4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A half4x3 matrix initialized with the specified arguments";
            }
            {
                var descriptor = Descriptors["half4x4"];
                descriptor.Category = "Type Matrix Constructors";
                descriptor.Description = @"Creates a 4 (rows) x 4 (columns) matrix of half.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("arguments", @"The matrix item values. The total number of values must equal the total dimension of the matrix. The arguments can be:
    - No values: All items of the vector are initialized with the value 0.
    - a single value: `half4x4(123)` will initialize all elements with 123.
    - an array value: `half4x4(1..16)` will initialize all elements with the array elements. The size of the array must match the size of the vector.
    - A combination of vectors/single values (e.g `half3x4(half4(1), half4(2), half4(3))`.")  { IsOptional = false });
                descriptor.Returns = @"A half4x4 matrix initialized with the specified arguments";
            }
        }        
    }
}
namespace Kalk.Core.Modules
{
    public partial class VectorModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("length", (Func<object, object>)Length);
            RegisterFunction("normalize", (Func<object, object>)Normalize);
            RegisterFunction("dot", (Func<object, object, object>)Dot);
            RegisterFunction("cross", (Func<Kalk.Core.KalkVector, Kalk.Core.KalkVector, object>)Cross);
            RegisterFunction("transpose", (Func<Kalk.Core.KalkMatrix, Kalk.Core.KalkMatrix>)Transpose);
            RegisterFunction("identity", (Func<Kalk.Core.KalkMatrix, Kalk.Core.KalkMatrix>)Identity);
            RegisterFunction("determinant", (Func<Kalk.Core.KalkMatrix, object>)Determinant);
            RegisterFunction("inverse", (Func<Kalk.Core.KalkMatrix, Kalk.Core.KalkMatrix>)Inverse);
            RegisterFunction("diag", (Func<object, object>)Diagonal);
            RegisterFunction("row", (Func<Kalk.Core.KalkMatrix, int, Kalk.Core.KalkVector>)GetRow);
            RegisterFunction("col", (Func<Kalk.Core.KalkMatrix, int, Kalk.Core.KalkVector>)GetColumn);
            RegisterFunction("mul", (Func<object, object, object>)Multiply);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptors["length"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Returns the length of the specified floating-point vector.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The specified floating-point vector.")  { IsOptional = false });
                descriptor.Returns = @"A floating-point scalar that represents the length of the x parameter.";
                descriptor.Example = @"    >>> length float2(1, 2)
    # length(float2(1, 2))
    out = 2.23606797749979
    >>> length(-5)
    # length(-5)
    out = 5
";
            }
            {
                var descriptor = Descriptors["normalize"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Normalizes the specified floating-point vector according to x / length(x).";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"he specified floating-point vector.")  { IsOptional = false });
                descriptor.Returns = @"The normalized x parameter. If the length of the x parameter is 0, the result is indefinite.";
                descriptor.Example = @"    >>> normalize float2(1,2)
    # normalize(float2(1, 2))
    out = float2(0.4472136, 0.8944272)
";
            }
            {
                var descriptor = Descriptors["dot"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Returns the dot product of two vectors.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The first vector.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("y", @"The second vector.")  { IsOptional = false });
                descriptor.Returns = @"The dot product of the x parameter and the y parameter.";
                descriptor.Example = @"    >>> dot(float3(1,2,3), float3(4,5,6))
    # dot(float3(1, 2, 3), float3(4, 5, 6))
    out = 32
    >>> dot(float3(1,2,3), 4)
    # dot(float3(1, 2, 3), 4)
    out = 24
    >>> dot(4, float3(1,2,3))
    # dot(4, float3(1, 2, 3))
    out = 24
    >>> dot(5,6)
    # dot(5, 6)
    out = 30
";
            }
            {
                var descriptor = Descriptors["cross"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Returns the cross product of two floating-point, 3D vectors.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The first floating-point, 3D vector.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("y", @"The second floating-point, 3D vector.")  { IsOptional = false });
                descriptor.Returns = @"The cross product of the x parameter and the y parameter.";
                descriptor.Example = @"    >>> cross(float3(1,2,3), float3(4,5,6))
    # cross(float3(1, 2, 3), float3(4, 5, 6))
    out = float3(-3, 6, -3)
    >>> cross(float3(1,0,0), float3(0,1,0))
    # cross(float3(1, 0, 0), float3(0, 1, 0))
    out = float3(0, 0, 1)
    >>> cross(float3(0,0,1), float3(0,1,0))
    # cross(float3(0, 0, 1), float3(0, 1, 0))
    out = float3(-1, 0, 0)
";
            }
            {
                var descriptor = Descriptors["transpose"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Transposes the specified matrix.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("m", @"The matrix to transpose.")  { IsOptional = false });
                descriptor.Returns = @"The transposed matrix.";
                descriptor.Example = @"    >>> transpose float3x4(1..12)
    # transpose(float3x4(1..12))
    out = float4x3(1, 5, 9, 2, 6, 10, 3, 7, 11, 4, 8, 12)
          # col  0           1           2           / row
          float3(1         , 5         , 9         ) # 0
          float3(2         , 6         , 10        ) # 1
          float3(3         , 7         , 11        ) # 2
          float3(4         , 8         , 12        ) # 3
    >>> transpose(out)
    # transpose(out)
    out = float3x4(1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
          # col  0           1           2           3           / row
          float4(1         , 2         , 3         , 4         ) # 0
          float4(5         , 6         , 7         , 8         ) # 1
          float4(9         , 10        , 11        , 12        ) # 2
";
            }
            {
                var descriptor = Descriptors["identity"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Creates an identity of a squared matrix.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("m", @"The type of the squared matrix.")  { IsOptional = false });
                descriptor.Returns = @"The identity matrix of the squared matrix type.";
                descriptor.Example = @"    >>> identity(float4x4)
    # identity(float4x4)
    out = float4x4(1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1, 0, 0, 0, 0, 1)
          # col  0           1           2           3           / row
          float4(1         , 0         , 0         , 0         ) # 0
          float4(0         , 1         , 0         , 0         ) # 1
          float4(0         , 0         , 1         , 0         ) # 2
          float4(0         , 0         , 0         , 1         ) # 3
";
            }
            {
                var descriptor = Descriptors["determinant"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Calculates the determinant of the specified matrix.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("m", @"The matrix to calculate the determinant for.")  { IsOptional = false });
                descriptor.Returns = @"A scalar representing the determinant of the matrix.";
                descriptor.Example = @"    >>> float4x4(4,3,2,2,0,1,-3,3,0,-1,3,3,0,3,1,1)
    # float4x4(4, 3, 2, 2, 0, 1, -3, 3, 0, -1, 3, 3, 0, 3, 1, 1)
    out = float4x4(4, 3, 2, 2, 0, 1, -3, 3, 0, -1, 3, 3, 0, 3, 1, 1)
          # col  0            1           2          3           / row
          float4(4         ,  3        ,  2        , 2         ) # 0
          float4(0         ,  1        , -3        , 3         ) # 1
          float4(0         , -1        ,  3        , 3         ) # 2
          float4(0         ,  3        ,  1        , 1         ) # 3
    >>> determinant out
    # determinant(out)
    out = -240
";
            }
            {
                var descriptor = Descriptors["inverse"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Calculates the inverse of the specified matrix.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("m", @"The matrix to calculate the inverse for.")  { IsOptional = false });
                descriptor.Returns = @"The inverse matrix of the specified matrix.";
                descriptor.Example = @"    >>> inverse(float3x3(10,20,10,4,5,6,2,3,5))
    # inverse(float3x3(10, 20, 10, 4, 5, 6, 2, 3, 5))
    out = float3x3(-0.1, 1, -1, 0.11428571, -0.42857143, 0.28571427, -0.028571427, -0.14285715, 0.42857143)
          # col   0             1            2           / row
          float3(-0.1        ,  1         , -1         ) # 0
          float3( 0.11428571 , -0.42857143,  0.28571427) # 1
          float3(-0.028571427, -0.14285715,  0.42857143) # 2
";
            }
            {
                var descriptor = Descriptors["diag"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Returns the diagonal vector of a squared matrix or a diagonal matrix from the specified vector.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"A vector or matrix to return the associated diagonal for.")  { IsOptional = false });
                descriptor.Returns = @"A diagonal vector of a matrix or a diagonal matrix of a vector.";
                descriptor.Example = @"     >>> diag(float4x4(1..16))
     # diag(float4x4(1..16))
     out = float4(1, 6, 11, 16)
     >>> diag(float4(1,2,3,4))
     # diag(float4(1, 2, 3, 4))
     out = float4x4(1, 0, 0, 0, 0, 2, 0, 0, 0, 0, 3, 0, 0, 0, 0, 4)
           # col  0           1           2           3           / row
           float4(1         , 0         , 0         , 0         ) # 0
           float4(0         , 2         , 0         , 0         ) # 1
           float4(0         , 0         , 3         , 0         ) # 2
           float4(0         , 0         , 0         , 4         ) # 3
";
            }
            {
                var descriptor = Descriptors["row"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Extract a row from the specified matrix.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The matrix to extract a row from.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("index", @"The index of the row (zero based).")  { IsOptional = false });
                descriptor.Returns = @"A vector extracted from the matrix.";
                descriptor.Example = @"    >>> row(float4x4(1..16), 2)
    # row(float4x4(1..16), 2)
    out = float4(9, 10, 11, 12)
";
            }
            {
                var descriptor = Descriptors["col"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Extract a column from the specified matrix.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"The matrix to extract a column from.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("index", @"The index of the column (zero based).")  { IsOptional = false });
                descriptor.Returns = @"A vector extracted from the matrix.";
                descriptor.Example = @"    >>> col(float4x4(1..16), 2)
    # col(float4x4(1..16), 2)
    out = float4(3, 7, 11, 15)
";
            }
            {
                var descriptor = Descriptors["mul"];
                descriptor.Category = "Math Vector/Matrix Functions";
                descriptor.Description = @"Multiplies a vector x vector (dot product), or a vector x matrix, or a matrix x vector or a matrix x matrix.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("x", @"A left vector or a matrix.")  { IsOptional = false });
                descriptor.Params.Add(new KalkParamDescriptor("y", @"A right vector or matrix.")  { IsOptional = false });
                descriptor.Returns = @"The result of the multiplication.";
                descriptor.Example = @"    >>> mul(float4(1,2,3,4), float4(5,6,7,8))
    # mul(float4(1, 2, 3, 4), float4(5, 6, 7, 8))
    out = 70
    >>> mul(float3(3,7,5), float3x3(2,3,-4,11,8,7,2,5,3))
    # mul(float3(3, 7, 5), float3x3(2, 3, -4, 11, 8, 7, 2, 5, 3))
    out = float3(7, 124, 56)
    >>> mul(float3x3(2,3,-4,11,8,7,2,5,3), float3(3,7,5))
    # mul(float3x3(2, 3, -4, 11, 8, 7, 2, 5, 3), float3(3, 7, 5))
    out = float3(93, 90, 52)
    >>> mul(float3x3(2,7,4,3,2,1,9,-1,2), float3x3(1,4,6,-1,-2,5,8,7,6))
    # mul(float3x3(2, 7, 4, 3, 2, 1, 9, -1, 2), float3x3(1, 4, 6, -1, -2, 5, 8, 7, 6))
    out = float3x3(68, 9, 20, 37, -16, 4, 91, 64, 51)
          # col  0            1          2           / row
          float3(68        ,  9        , 20        ) # 0
          float3(37        , -16       , 4         ) # 1
          float3(91        ,  64       , 51        ) # 2
";
            }
        }        
    }
}
namespace Kalk.Core.Modules
{
    public partial class WebModule
    {
        protected override void RegisterFunctionsAuto()
        {
            RegisterFunction("url_encode", (Func<string, string>)UrlEncode);
            RegisterFunction("url_decode", (Func<string, string>)UrlDecode);
            RegisterFunction("url_escape", (Func<string, string>)UrlEscape);
            RegisterFunction("html_encode", (Func<string, string>)HtmlEncode);
            RegisterFunction("html_decode", (Func<string, string>)HtmlDecode);
            RegisterFunction("json", (Func<object, object>)Json);
            RegisterFunction("html_strip", (Func<string, string>)HtmlStrip);
            RegisterFunction("wget", (Func<string, Scriban.Runtime.ScriptObject>)WebGet);
            RegisterDocumentationAuto();
        }

        private void RegisterDocumentationAuto()
        {
            {
                var descriptor = Descriptor;
                descriptor.Category = "Modules (e.g `import Files`)";
                descriptor.Description = @"Module that provides Web functions (e.g `url_encode`, `json`, `wget`...)";
                descriptor.IsCommand = false;
            }
            {
                var descriptor = Descriptors["url_encode"];
                descriptor.Category = "Web & Html Functions";
                descriptor.Description = @"Converts a specified URL text into a URL-encoded.
    
     URL encoding converts characters that are not allowed in a URL into character-entity equivalents.
     For example, when the characters < and > are embedded in a block of text to be transmitted in a URL, they are encoded as %3c and %3e.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("url", @"The url text to encode as an URL.")  { IsOptional = false });
                descriptor.Returns = @"An encoded URL.";
                descriptor.Example = @"     >>> url_encode ""this<is>an:url and another part""
     # url_encode(""this<is>an:url and another part"")
     out = ""this%3Cis%3Ean%3Aurl+and+another+part""
";
            }
            {
                var descriptor = Descriptors["url_decode"];
                descriptor.Category = "Web & Html Functions";
                descriptor.Description = @"Converts a URL-encoded string into a decoded string.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("url", @"The URL to decode.")  { IsOptional = false });
                descriptor.Returns = @"The decoded URL";
                descriptor.Example = @"    >>> url_decode ""this%3Cis%3Ean%3Aurl+and+another+part""
    # url_decode(""this%3Cis%3Ean%3Aurl+and+another+part"")
    out = ""this<is>an:url and another part""
";
            }
            {
                var descriptor = Descriptors["url_escape"];
                descriptor.Category = "Web & Html Functions";
                descriptor.Description = @"Identifies all characters in a string that are not allowed in URLS, and replaces the characters with their escaped variants.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("url", @"The input string.")  { IsOptional = false });
                descriptor.Returns = @"The input string url escaped";
                descriptor.Example = @"    >>> ""<hello> & <scriban>"" |> url_escape
    # ""<hello> & <scriban>"" |> url_escape
    out = ""%3Chello%3E%20&%20%3Cscriban%3E""
";
            }
            {
                var descriptor = Descriptors["html_encode"];
                descriptor.Category = "Web & Html Functions";
                descriptor.Description = @"Encodes a HTML input string (replacing `&` by `&amp;`)";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The input string with HTML entities.";
                descriptor.Example = @"    >>> ""<p>This is a paragraph</p>"" |> html_encode
    # ""<p>This is a paragraph</p>"" |> html_encode
    out = ""&lt;p&gt;This is a paragraph&lt;/p&gt;""
    >>> out |> html_decode
    # out |> html_decode
    out = ""<p>This is a paragraph</p>""
";
            }
            {
                var descriptor = Descriptors["html_decode"];
                descriptor.Category = "Web & Html Functions";
                descriptor.Description = @"Decodes a HTML input string (replacing `&amp;` by `&`)";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The input string removed with any HTML entities.";
                descriptor.Example = @"    >>> ""<p>This is a paragraph</p>"" |> html_encode
    # ""<p>This is a paragraph</p>"" |> html_encode
    out = ""&lt;p&gt;This is a paragraph&lt;/p&gt;""
    >>> out |> html_decode
    # out |> html_decode
    out = ""<p>This is a paragraph</p>""
";
            }
            {
                var descriptor = Descriptors["json"];
                descriptor.Category = "Web & Html Functions";
                descriptor.Description = @"Converts to or from a JSON object depending on the value argument.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("value", @"A value argument:
    - If the value is a string, it is expecting this string to be a JSON string and will convert it to the appropriate object.
    - If the value is an array or object, it will convert it to a JSON string representation.")  { IsOptional = false });
                descriptor.Returns = @"A JSON string or an object/array depending on the argument.";
                descriptor.Example = @"    >>> json {a: 1, b: 2, c: [4,5], d: ""Hello World""}
    # json({a: 1, b: 2, c: [4,5], d: ""Hello World""})
    out = ""{\""a\"": 1, \""b\"": 2, \""c\"": [4, 5], \""d\"": \""Hello World\""}""
    >>> json out
    # json(out)
    out = {a: 1, b: 2, c: [4, 5], d: ""Hello World""}
";
            }
            {
                var descriptor = Descriptors["html_strip"];
                descriptor.Category = "Web & Html Functions";
                descriptor.Description = @"Removes any HTML tags from the input string";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("text", @"The input string")  { IsOptional = false });
                descriptor.Returns = @"The input string removed with any HTML tags";
                descriptor.Example = @"    >>> ""<p>This is a paragraph</p>"" |> html_strip
    # ""<p>This is a paragraph</p>"" |> html_strip
    out = ""This is a paragraph""
";
            }
            {
                var descriptor = Descriptors["wget"];
                descriptor.Category = "Web & Html Functions";
                descriptor.Description = @"Retrieves the content of the following URL by issuing a HTTP GET request.";
                descriptor.IsCommand = false;
                descriptor.Params.Add(new KalkParamDescriptor("url", @"The URL to retrieve the content for.")  { IsOptional = false });
                descriptor.Returns = @"An object with the result of the request. This object contains the following members:
    - `version`: the protocol of the version.
    - `code`: the HTTP return code.
    - `reason`: the HTTP reason phrase.
    - `headers`: the HTTP returned headers.
    - `content`: the HTTP content. Either a string if the mime type is `text/*` or an object if the mime type is `application/json` otherwise it will return a bytebuffer.";
                descriptor.Remarks = @"```
    >>> wget ""https://markdig.azurewebsites.net/""
    # wget(""https://markdig.azurewebsites.net/"")
    out = {version: ""1.1"", code: 200, reason: ""OK"", headers: {""Content-Type"": ""text/plain; charset=utf-8"", ""Content-Length"": 0}, content: """"}
    ```";
            }
        }        
    }
}